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[35.187.92.245]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3c074d43b9asm3464410f8f.24.2025.08.19.05.10.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Aug 2025 05:10:30 -0700 (PDT) From: Tudor Ambarus Date: Tue, 19 Aug 2025 12:10:20 +0000 Subject: [PATCH 1/3] arm64: dts: exynos: gs101: add google,gs101-acpm-dvfs-clocks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250819-acpm-dvfs-dt-v1-1-4e38b95408c4@linaro.org> References: <20250819-acpm-dvfs-dt-v1-0-4e38b95408c4@linaro.org> In-Reply-To: <20250819-acpm-dvfs-dt-v1-0-4e38b95408c4@linaro.org> To: Peter Griffin , =?utf-8?q?Andr=C3=A9_Draszik?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar , Catalin Marinas , Will Deacon Cc: linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, willmcvicker@google.com, kernel-team@android.com, Tudor Ambarus X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1755605429; l=844; i=tudor.ambarus@linaro.org; s=20241212; h=from:subject:message-id; bh=ea6fVOF/ZPzXpkLEtEhf8jo7+yKf1XzprUPMMimndVQ=; b=8NbHtnuer4XrqcxrU770zSH39wnsQWVoGXwzK2B/dmhKJyngAV87tT11N+xcYhCnrDVYTi6as xZEWhZ3g+nSDl9nwr+EDjC5c1libRfq5lZFXoXinj4P0CMBBy7et+BJ X-Developer-Key: i=tudor.ambarus@linaro.org; a=ed25519; pk=uQzE0NXo3dIjeowMTOPCpIiPHEz12IA/MbyzrZVh9WI= Define the clocks exposed by the ACPM interface. Signed-off-by: Tudor Ambarus --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot= /dts/exynos/google/gs101.dtsi index c0f8c25861a9ddb5bbd256b62c66a645922ca74e..d010b8ffc4e09562519d6796691= fe573c68b7ac7 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -204,6 +204,11 @@ acpm_ipc: power-management { compatible =3D "google,gs101-acpm-ipc"; mboxes =3D <&ap2apm_mailbox>; shmem =3D <&apm_sram>; + + acpm_dvfs_clocks: clocks { + compatible =3D "google,gs101-acpm-dvfs-clocks"; + #clock-cells =3D <1>; + }; }; }; =20 --=20 2.51.0.rc1.167.g924127e9c0-goog From nobody Sat Oct 4 06:27:55 2025 Received: from mail-wm1-f46.google.com (mail-wm1-f46.google.com [209.85.128.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 27F2C20C000 for ; Tue, 19 Aug 2025 12:10:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755605434; cv=none; b=jzEbUGnbmBwRfb+IGYsGaqIi7NCeKRZlc5oXLGNuovwBWfkhO2zwQ5LQqnqm3Wncf6T+0SQbzU8SjLcgmXI2/9SIwANNSi2k2glhK5zUQhT8tTFNr59y4yap7roTtb5ytSVO1kZIQwdZhNf5qjvo9pTe6UtqbKdSVGIdL5aVU4s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755605434; c=relaxed/simple; bh=nqRaXwOYUnbNG0j2pkHNtlxp7R1a7PqyphjeUytPpmQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=sR04ePA9ntnEOWaIytpkrcWft2E7PXNoKjdXXD8NehaimBFdXxT2l9frUz7I1NrtK0DUvthRXtZlgcoMhsyJSi5iUiOI4ej3H3u+56cvEazVyGwArSq8Br16zCJYCuWywlilSxE2MUa17d3ggyjhKxEho7EYCIQrXafnlX8QGvE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=MrRgKEKm; arc=none smtp.client-ip=209.85.128.46 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="MrRgKEKm" Received: by mail-wm1-f46.google.com with SMTP id 5b1f17b1804b1-45a15fd04d9so39716565e9.1 for ; Tue, 19 Aug 2025 05:10:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1755605431; x=1756210231; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=2R8D30km/KSA0O4LJJjN/QUo92gPxApdF/JdH5YvZSM=; b=MrRgKEKmifbADj5O9EzoyijMXjJ3Ds00E8WZjlEqINctrzxGyyATb67UO3k1lwpdr/ F+df57i7A0XP/RyYehUgvy1PEHw3ap7h00FVQtKztNUZGcXCwVKK5cezF3wP9E46E6E1 9n57cHM0aOESOJMoQARsmFLtgFtcRMYeDzl+b6O4aFd9WCUogXfazcpei1esjjcialp/ S/TRaRXNZg7EWuvSBsG9Tfz+O/x2zaXpW+uHErt6NoYvbjavwXcFhZVJGO1hWNq/yJGU 4HfiLvvGmhZl9WYMXP04OjbfAncWtzu06xNQxzwQw0GbH60Y9z6zHnuP1EUVp3fhfKO6 x+tw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1755605431; x=1756210231; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2R8D30km/KSA0O4LJJjN/QUo92gPxApdF/JdH5YvZSM=; b=jKRaSh9e4KleKByVzDkzLeuh/BwMltYjEqG6BZ9mmp21JEzHHAa/5i/WuLbNOFLF5v avpllp6fGnH7/0kQlMz2k2nRnYD8QrN8lrqYoKatJMcMug9GrMGiQWGu5RkCD1uCzRmt LdbaISsT+aof1862LybHFvbVeol68qnMU4XWXB0acRmy5T01y9TedRUk0S4jcgbxCG6o xlLMYowCZk+SWxP8RW4YP3hUJ+YQiAIQY8ySI1VJ0PCplWezzd3/GKd2GENIHG9BvAIC haIr4xPG+P9/n0S+XjzIyR9+iKMkVNBt8YilkRajrWikdOjaPGh0uuSRbYu69TfXyh0f +5xA== X-Forwarded-Encrypted: i=1; AJvYcCVNXRsz1sT4j5YgzxpY+v0RZ5D/oN1+FoJ0Xgzu/IM7qCc+k3ELrGQ5JIKl4NMvoTBIGvTFy7Jrc1beHQo=@vger.kernel.org X-Gm-Message-State: AOJu0YyAVn/5bXuw8YrKvwRaV9kDIhniyMLYz0QJGBHbRb9BErGmMMRs mgrgsuPe7GPkYWSjdLFUceKKZyrauk1Jzj+WEV27mG+Bq4bmE1J6+a/8Ii6dQNcWmh4= X-Gm-Gg: ASbGncs0b3mWe0GLtICGS7K4WVyHk3FeYD4I+A3WVJYEVDtZOirK+ZWWy+HpLlgdMat yW1GE/cBsSHiQeSNzu708ezBIRCBs7dpOvA2PjJntGqYLJ0eULCwBCIHge23SBurRZLC4VYnEY9 ARYYOwBNOm0VkEyk4Y+ZI31wXniVjblsTEa0v9x1DCJ/IM7qss4LJU1IAZQPycj1SOu8LBOWUkt jKGU7mWbYDFhZO59c1xn7N0V7ICmfBJyh8WqrnPoHwCsaTJ/+31PfziTGL+iY9FNH2DGuJm7D35 Otxv7BYVy2tS4dcUUPerQ+DQUKbmxoZb5pd+KRuumv+eZAgmj1Lhpz/kVvSfh0zkBbhEY9dNlH6 cDChfMgYnEDDuJ7Ok/7YsgPwtOOqcXMvkc3MlzrbHu2auwztAdtgQ2M16WNJAzMPxw//e4NHob6 vC3w== X-Google-Smtp-Source: AGHT+IFppDDMa2VTL2CIGZHM9gzBH35t1wQZSmplPnzJjHi59FMlVUz9oCZUMUh1Ng+uHKmRdhHOVw== X-Received: by 2002:a5d:5d0a:0:b0:3b7:8acf:1887 with SMTP id ffacd0b85a97d-3c1333b5d05mr1714373f8f.13.1755605431436; Tue, 19 Aug 2025 05:10:31 -0700 (PDT) Received: from ta2.c.googlers.com (245.92.187.35.bc.googleusercontent.com. [35.187.92.245]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3c074d43b9asm3464410f8f.24.2025.08.19.05.10.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Aug 2025 05:10:30 -0700 (PDT) From: Tudor Ambarus Date: Tue, 19 Aug 2025 12:10:21 +0000 Subject: [PATCH 2/3] arm64: dts: exynos: gs101: add CPU clocks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250819-acpm-dvfs-dt-v1-2-4e38b95408c4@linaro.org> References: <20250819-acpm-dvfs-dt-v1-0-4e38b95408c4@linaro.org> In-Reply-To: <20250819-acpm-dvfs-dt-v1-0-4e38b95408c4@linaro.org> To: Peter Griffin , =?utf-8?q?Andr=C3=A9_Draszik?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar , Catalin Marinas , Will Deacon Cc: linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, willmcvicker@google.com, kernel-team@android.com, Tudor Ambarus X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1755605429; l=2818; i=tudor.ambarus@linaro.org; s=20241212; h=from:subject:message-id; bh=nqRaXwOYUnbNG0j2pkHNtlxp7R1a7PqyphjeUytPpmQ=; b=pFUBFj/DVmeY+1QROIBAVpK6j8hChOM2KVuU6gLsrewVj4sNAL6TBghVOuWhfLXWLQ2nbVtIP K8YHpySm5NaC08vEfS1NamJQbC18pPnsZa5Tc0q0R/snEt9EkN0plWQ X-Developer-Key: i=tudor.ambarus@linaro.org; a=ed25519; pk=uQzE0NXo3dIjeowMTOPCpIiPHEz12IA/MbyzrZVh9WI= The GS101 CPU clocks are exposed through the ACPM protocol. Add them. Signed-off-by: Tudor Ambarus --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot= /dts/exynos/google/gs101.dtsi index d010b8ffc4e09562519d6796691fe573c68b7ac7..42926f8bde8889ec99ecf9fc551= 629a0453e788f 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -72,6 +72,7 @@ cpu0: cpu@0 { device_type =3D "cpu"; compatible =3D "arm,cortex-a55"; reg =3D <0x0000>; + clocks =3D <&acpm_dvfs_clocks CLK_ACPM_DVFS_CPUCL0>; enable-method =3D "psci"; cpu-idle-states =3D <&ananke_cpu_sleep>; capacity-dmips-mhz =3D <250>; @@ -82,6 +83,7 @@ cpu1: cpu@100 { device_type =3D "cpu"; compatible =3D "arm,cortex-a55"; reg =3D <0x0100>; + clocks =3D <&acpm_dvfs_clocks CLK_ACPM_DVFS_CPUCL0>; enable-method =3D "psci"; cpu-idle-states =3D <&ananke_cpu_sleep>; capacity-dmips-mhz =3D <250>; @@ -92,6 +94,7 @@ cpu2: cpu@200 { device_type =3D "cpu"; compatible =3D "arm,cortex-a55"; reg =3D <0x0200>; + clocks =3D <&acpm_dvfs_clocks CLK_ACPM_DVFS_CPUCL0>; enable-method =3D "psci"; cpu-idle-states =3D <&ananke_cpu_sleep>; capacity-dmips-mhz =3D <250>; @@ -102,6 +105,7 @@ cpu3: cpu@300 { device_type =3D "cpu"; compatible =3D "arm,cortex-a55"; reg =3D <0x0300>; + clocks =3D <&acpm_dvfs_clocks CLK_ACPM_DVFS_CPUCL0>; enable-method =3D "psci"; cpu-idle-states =3D <&ananke_cpu_sleep>; capacity-dmips-mhz =3D <250>; @@ -112,6 +116,7 @@ cpu4: cpu@400 { device_type =3D "cpu"; compatible =3D "arm,cortex-a76"; reg =3D <0x0400>; + clocks =3D <&acpm_dvfs_clocks CLK_ACPM_DVFS_CPUCL1>; enable-method =3D "psci"; cpu-idle-states =3D <&enyo_cpu_sleep>; capacity-dmips-mhz =3D <620>; @@ -122,6 +127,7 @@ cpu5: cpu@500 { device_type =3D "cpu"; compatible =3D "arm,cortex-a76"; reg =3D <0x0500>; + clocks =3D <&acpm_dvfs_clocks CLK_ACPM_DVFS_CPUCL1>; enable-method =3D "psci"; cpu-idle-states =3D <&enyo_cpu_sleep>; capacity-dmips-mhz =3D <620>; @@ -132,6 +138,7 @@ cpu6: cpu@600 { device_type =3D "cpu"; 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[35.187.92.245]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3c074d43b9asm3464410f8f.24.2025.08.19.05.10.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Aug 2025 05:10:31 -0700 (PDT) From: Tudor Ambarus Date: Tue, 19 Aug 2025 12:10:22 +0000 Subject: [PATCH 3/3] arm64: dts: exynos: gs101: add OPPs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250819-acpm-dvfs-dt-v1-3-4e38b95408c4@linaro.org> References: <20250819-acpm-dvfs-dt-v1-0-4e38b95408c4@linaro.org> In-Reply-To: <20250819-acpm-dvfs-dt-v1-0-4e38b95408c4@linaro.org> To: Peter Griffin , =?utf-8?q?Andr=C3=A9_Draszik?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar , Catalin Marinas , Will Deacon Cc: linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, willmcvicker@google.com, kernel-team@android.com, Tudor Ambarus X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1755605429; l=8502; i=tudor.ambarus@linaro.org; s=20241212; h=from:subject:message-id; bh=a6PZI+tjZrmUg6w8G2uTeLCpE/pt0ZaCvCKU3fNi5Gw=; b=VHVnXzOLTTEgHy3PRapQ2DpiSk2f3PV2HmXhzrM77UxMkHCaAnS1joG5fcZS2vcpK5NnKpJ08 YAM+PFCydyaBXyqSkyULZ629pZxk+fLLr7xvwiO6rmdO0pwi4Kg5QOM X-Developer-Key: i=tudor.ambarus@linaro.org; a=ed25519; pk=uQzE0NXo3dIjeowMTOPCpIiPHEz12IA/MbyzrZVh9WI= Add operating performance points (OPPs). Signed-off-by: Tudor Ambarus --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 275 +++++++++++++++++++++++= ++++ 1 file changed, 275 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot= /dts/exynos/google/gs101.dtsi index 42926f8bde8889ec99ecf9fc551629a0453e788f..b2303b3a3d176ef9b825d24bbe0= bb0d51ef81246 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -77,6 +77,7 @@ cpu0: cpu@0 { cpu-idle-states =3D <&ananke_cpu_sleep>; capacity-dmips-mhz =3D <250>; dynamic-power-coefficient =3D <70>; + operating-points-v2 =3D <&cpucl0_opp_table>; }; =20 cpu1: cpu@100 { @@ -88,6 +89,7 @@ cpu1: cpu@100 { cpu-idle-states =3D <&ananke_cpu_sleep>; capacity-dmips-mhz =3D <250>; dynamic-power-coefficient =3D <70>; + operating-points-v2 =3D <&cpucl0_opp_table>; }; =20 cpu2: cpu@200 { @@ -99,6 +101,7 @@ cpu2: cpu@200 { cpu-idle-states =3D <&ananke_cpu_sleep>; capacity-dmips-mhz =3D <250>; dynamic-power-coefficient =3D <70>; + operating-points-v2 =3D <&cpucl0_opp_table>; }; =20 cpu3: cpu@300 { @@ -110,6 +113,7 @@ cpu3: cpu@300 { cpu-idle-states =3D <&ananke_cpu_sleep>; capacity-dmips-mhz =3D <250>; dynamic-power-coefficient =3D <70>; + operating-points-v2 =3D <&cpucl0_opp_table>; }; =20 cpu4: cpu@400 { @@ -121,6 +125,7 @@ cpu4: cpu@400 { cpu-idle-states =3D <&enyo_cpu_sleep>; capacity-dmips-mhz =3D <620>; dynamic-power-coefficient =3D <284>; + operating-points-v2 =3D <&cpucl1_opp_table>; }; =20 cpu5: cpu@500 { @@ -132,6 +137,7 @@ cpu5: cpu@500 { cpu-idle-states =3D <&enyo_cpu_sleep>; capacity-dmips-mhz =3D <620>; dynamic-power-coefficient =3D <284>; + operating-points-v2 =3D <&cpucl1_opp_table>; }; =20 cpu6: cpu@600 { @@ -143,6 +149,7 @@ cpu6: cpu@600 { cpu-idle-states =3D <&hera_cpu_sleep>; capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <650>; + operating-points-v2 =3D <&cpucl2_opp_table>; }; =20 cpu7: cpu@700 { @@ -154,6 +161,7 @@ cpu7: cpu@700 { cpu-idle-states =3D <&hera_cpu_sleep>; capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <650>; + operating-points-v2 =3D <&cpucl2_opp_table>; }; =20 idle-states { @@ -191,6 +199,273 @@ hera_cpu_sleep: cpu-hera-sleep { }; }; =20 + cpucl0_opp_table: opp-table-0 { + compatible =3D "operating-points-v2"; + opp-shared; + + opp-300000000 { + opp-hz =3D /bits/ 64 <300000000>; + opp-microvolt =3D <537500>; + clock-latency-ns =3D <5000000>; + }; + + opp-574000000 { + opp-hz =3D /bits/ 64 <574000000>; + opp-microvolt =3D <600000>; + clock-latency-ns =3D <5000000>; + }; + + opp-738000000 { + opp-hz =3D /bits/ 64 <738000000>; + opp-microvolt =3D <618750>; + clock-latency-ns =3D <5000000>; + }; + + opp-930000000 { + opp-hz =3D /bits/ 64 <930000000>; + opp-microvolt =3D <668750>; + clock-latency-ns =3D <5000000>; + }; + + opp-1098000000 { + opp-hz =3D /bits/ 64 <1098000000>; + opp-microvolt =3D <712500>; + clock-latency-ns =3D <5000000>; + }; + + opp-1197000000 { + opp-hz =3D /bits/ 64 <1197000000>; + opp-microvolt =3D <731250>; + clock-latency-ns =3D <5000000>; + }; + + opp-1328000000 { + opp-hz =3D /bits/ 64 <1328000000>; + opp-microvolt =3D <762500>; + clock-latency-ns =3D <5000000>; + }; + + opp-1401000000 { + opp-hz =3D /bits/ 64 <1401000000>; + opp-microvolt =3D <781250>; + clock-latency-ns =3D <5000000>; + }; + + opp-1598000000 { + opp-hz =3D /bits/ 64 <1598000000>; + opp-microvolt =3D <831250>; + clock-latency-ns =3D <5000000>; + }; + + opp-1704000000 { + opp-hz =3D /bits/ 64 <1704000000>; + opp-microvolt =3D <862500>; + clock-latency-ns =3D <5000000>; + }; + + opp-1803000000 { + opp-hz =3D /bits/ 64 <1803000000>; + opp-microvolt =3D <906250>; + clock-latency-ns =3D <5000000>; + }; + }; + + cpucl1_opp_table: opp-table-1 { + compatible =3D "operating-points-v2"; + opp-shared; + + opp-400000000 { + opp-hz =3D /bits/ 64 <400000000>; + opp-microvolt =3D <506250>; + clock-latency-ns =3D <5000000>; + }; + + opp-553000000 { + opp-hz =3D /bits/ 64 <553000000>; + opp-microvolt =3D <537500>; + clock-latency-ns =3D <5000000>; + }; + + opp-696000000 { + opp-hz =3D /bits/ 64 <696000000>; + opp-microvolt =3D <562500>; + clock-latency-ns =3D <5000000>; + }; + + opp-799000000 { + opp-hz =3D /bits/ 64 <799000000>; + opp-microvolt =3D <581250>; + clock-latency-ns =3D <5000000>; + }; + + opp-910000000 { + opp-hz =3D /bits/ 64 <910000000>; + opp-microvolt =3D <606250>; + clock-latency-ns =3D <5000000>; + }; + + opp-1024000000 { + opp-hz =3D /bits/ 64 <1024000000>; + opp-microvolt =3D <625000>; + clock-latency-ns =3D <5000000>; + }; + + opp-1197000000 { + opp-hz =3D /bits/ 64 <1197000000>; + opp-microvolt =3D <662500>; + clock-latency-ns =3D <5000000>; + }; + + opp-1328000000 { + opp-hz =3D /bits/ 64 <1328000000>; + opp-microvolt =3D <687500>; + clock-latency-ns =3D <5000000>; + }; + + opp-1491000000 { + opp-hz =3D /bits/ 64 <1491000000>; + opp-microvolt =3D <731250>; + clock-latency-ns =3D <5000000>; + }; + + opp-1663000000 { + opp-hz =3D /bits/ 64 <1663000000>; + opp-microvolt =3D <775000>; + clock-latency-ns =3D <5000000>; + }; + + opp-1836000000 { + opp-hz =3D /bits/ 64 <1836000000>; + opp-microvolt =3D <818750>; + clock-latency-ns =3D <5000000>; + }; + + opp-1999000000 { + opp-hz =3D /bits/ 64 <1999000000>; + opp-microvolt =3D <868750>; + clock-latency-ns =3D <5000000>; + }; + + opp-2130000000 { + opp-hz =3D /bits/ 64 <2130000000>; + opp-microvolt =3D <918750>; + clock-latency-ns =3D <5000000>; + }; + + opp-2253000000 { + opp-hz =3D /bits/ 64 <2253000000>; + opp-microvolt =3D <968750>; + clock-latency-ns =3D <5000000>; + }; + }; + + cpucl2_opp_table: opp-table-2 { + compatible =3D "operating-points-v2"; + opp-shared; + + opp-500000000 { + opp-hz =3D /bits/ 64 <500000000>; + opp-microvolt =3D <500000>; + clock-latency-ns =3D <5000000>; + }; + + opp-851000000 { + opp-hz =3D /bits/ 64 <851000000>; + opp-microvolt =3D <556250>; + clock-latency-ns =3D <5000000>; + }; + + opp-984000000 { + opp-hz =3D /bits/ 64 <984000000>; + opp-microvolt =3D <575000>; + clock-latency-ns =3D <5000000>; + }; + + opp-1106000000 { + opp-hz =3D /bits/ 64 <1106000000>; + opp-microvolt =3D <606250>; + clock-latency-ns =3D <5000000>; + }; + + opp-1277000000 { + opp-hz =3D /bits/ 64 <1277000000>; + opp-microvolt =3D <631250>; + clock-latency-ns =3D <5000000>; + }; + + opp-1426000000 { + opp-hz =3D /bits/ 64 <1426000000>; + opp-microvolt =3D <662500>; + clock-latency-ns =3D <5000000>; + }; + + opp-1582000000 { + opp-hz =3D /bits/ 64 <1582000000>; + opp-microvolt =3D <693750>; + clock-latency-ns =3D <5000000>; + }; + + opp-1745000000 { + opp-hz =3D /bits/ 64 <1745000000>; + opp-microvolt =3D <731250>; + clock-latency-ns =3D <5000000>; + }; + + opp-1826000000 { + opp-hz =3D /bits/ 64 <1826000000>; + opp-microvolt =3D <750000>; + clock-latency-ns =3D <5000000>; + }; + + opp-2048000000 { + opp-hz =3D /bits/ 64 <2048000000>; + opp-microvolt =3D <793750>; + clock-latency-ns =3D <5000000>; + }; + + opp-2188000000 { + opp-hz =3D /bits/ 64 <2188000000>; + opp-microvolt =3D <831250>; + clock-latency-ns =3D <5000000>; + }; + + opp-2252000000 { + opp-hz =3D /bits/ 64 <2252000000>; + opp-microvolt =3D <850000>; + clock-latency-ns =3D <5000000>; + }; + + opp-2401000000 { + opp-hz =3D /bits/ 64 <2401000000>; + opp-microvolt =3D <887500>; + clock-latency-ns =3D <5000000>; + }; + + opp-2507000000 { + opp-hz =3D /bits/ 64 <2507000000>; + opp-microvolt =3D <925000>; + clock-latency-ns =3D <5000000>; + }; + + opp-2630000000 { + opp-hz =3D /bits/ 64 <2630000000>; + opp-microvolt =3D <968750>; + clock-latency-ns =3D <5000000>; + }; + + opp-2704000000 { + opp-hz =3D /bits/ 64 <2704000000>; + opp-microvolt =3D <1000000>; + clock-latency-ns =3D <5000000>; + }; + + opp-2802000000 { + opp-hz =3D /bits/ 64 <2802000000>; + opp-microvolt =3D <1056250>; + clock-latency-ns =3D <5000000>; + }; + }; + /* ect node is required to be present by bootloader */ ect { }; --=20 2.51.0.rc1.167.g924127e9c0-goog