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[35.187.92.245]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3c077788df7sm3430817f8f.48.2025.08.19.04.45.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Aug 2025 04:45:53 -0700 (PDT) From: Tudor Ambarus Date: Tue, 19 Aug 2025 11:45:36 +0000 Subject: [PATCH 1/3] dt-bindings: firmware: google,gs101-acpm-ipc: add clocks node Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250819-acpm-clk-v1-1-6bbd97474671@linaro.org> References: <20250819-acpm-clk-v1-0-6bbd97474671@linaro.org> In-Reply-To: <20250819-acpm-clk-v1-0-6bbd97474671@linaro.org> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Peter Griffin , =?utf-8?q?Andr=C3=A9_Draszik?= , Michael Turquette , Stephen Boyd , Krzysztof Kozlowski , Alim Akhtar , Sylwester Nawrocki , Chanwoo Choi Cc: linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, willmcvicker@google.com, kernel-team@android.com, Tudor Ambarus X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1755603952; l=2971; i=tudor.ambarus@linaro.org; s=20241212; h=from:subject:message-id; bh=RHgzxERFqXBJayCLtp1I/QWWv579hP721Hv537Vxp6E=; b=0VhemtYEBOAIemXpjyQfMxDu+WLHs0AJDariMAZ3V8vjYybaLCcOrMVRTwR064RJ8oH8Qlkro INmqzkQoG67CliO24U9NMFfvexZ3ErbbkxnpAIzvSJXbHEqDgAb42pu X-Developer-Key: i=tudor.ambarus@linaro.org; a=ed25519; pk=uQzE0NXo3dIjeowMTOPCpIiPHEz12IA/MbyzrZVh9WI= The firmware exposes clocks that can be controlled via the ACPM interface. Describe the clocks exposed by the APM firmware. Signed-off-by: Tudor Ambarus --- .../bindings/firmware/google,gs101-acpm-ipc.yaml | 28 ++++++++++++++++++= ++++ include/dt-bindings/clock/google,gs101.h | 15 ++++++++++++ 2 files changed, 43 insertions(+) diff --git a/Documentation/devicetree/bindings/firmware/google,gs101-acpm-i= pc.yaml b/Documentation/devicetree/bindings/firmware/google,gs101-acpm-ipc.= yaml index 9785aac3b5f34955bbfe2718eec48581d050954f..27cdf9c881ca680e78e77a0e14f= fcffeba970871 100644 --- a/Documentation/devicetree/bindings/firmware/google,gs101-acpm-ipc.yaml +++ b/Documentation/devicetree/bindings/firmware/google,gs101-acpm-ipc.yaml @@ -27,6 +27,29 @@ properties: mboxes: maxItems: 1 =20 + clocks: + description: + Clocks that are variable and index based. These clocks don't provide + an entire range of values between the limits but only discrete points + within the range. The firmware also manages the voltage scaling + appropriately with the clock scaling. + type: object + additionalProperties: false + + properties: + compatible: + const: google,gs101-acpm-dvfs-clocks + + "#clock-cells": + const: 1 + description: + The argument is the ID of the clock contained by the firmware + messages. + + required: + - compatible + - "#clock-cells" + pmic: description: Child node describing the main PMIC. type: object @@ -59,6 +82,11 @@ examples: mboxes =3D <&ap2apm_mailbox>; shmem =3D <&apm_sram>; =20 + clocks { + compatible =3D "google,gs101-acpm-dvfs-clocks"; + #clock-cells =3D <1>; + }; + pmic { compatible =3D "samsung,s2mpg10-pmic"; interrupts-extended =3D <&gpa0 6 IRQ_TYPE_LEVEL_LOW>; diff --git a/include/dt-bindings/clock/google,gs101.h b/include/dt-bindings= /clock/google,gs101.h index 442f9e9037dc33198a1cee20af62fc70bbd96605..f1d0df412fdd49b300db4ba88bc= 0b1674cf0cdf8 100644 --- a/include/dt-bindings/clock/google,gs101.h +++ b/include/dt-bindings/clock/google,gs101.h @@ -634,4 +634,19 @@ #define CLK_GOUT_PERIC1_CLK_PERIC1_USI9_USI_CLK 45 #define CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK 46 =20 +#define CLK_ACPM_DVFS_MIF 0 +#define CLK_ACPM_DVFS_INT 1 +#define CLK_ACPM_DVFS_CPUCL0 2 +#define CLK_ACPM_DVFS_CPUCL1 3 +#define CLK_ACPM_DVFS_CPUCL2 4 +#define CLK_ACPM_DVFS_G3D 5 +#define CLK_ACPM_DVFS_G3DL2 6 +#define CLK_ACPM_DVFS_TPU 7 +#define CLK_ACPM_DVFS_INTCAM 8 +#define CLK_ACPM_DVFS_TNR 9 +#define CLK_ACPM_DVFS_CAM 10 +#define CLK_ACPM_DVFS_MFC 11 +#define CLK_ACPM_DVFS_DISP 12 +#define CLK_ACPM_DVFS_BO 13 + #endif /* _DT_BINDINGS_CLOCK_GOOGLE_GS101_H */ --=20 2.51.0.rc1.167.g924127e9c0-goog From nobody Sat Oct 4 06:27:54 2025 Received: from mail-wr1-f49.google.com (mail-wr1-f49.google.com [209.85.221.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9E7A132C31C for ; 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[35.187.92.245]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3c077788df7sm3430817f8f.48.2025.08.19.04.45.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Aug 2025 04:45:54 -0700 (PDT) From: Tudor Ambarus Date: Tue, 19 Aug 2025 11:45:37 +0000 Subject: [PATCH 2/3] firmware: exynos-acpm: add DVFS protocol Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250819-acpm-clk-v1-2-6bbd97474671@linaro.org> References: <20250819-acpm-clk-v1-0-6bbd97474671@linaro.org> In-Reply-To: <20250819-acpm-clk-v1-0-6bbd97474671@linaro.org> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Peter Griffin , =?utf-8?q?Andr=C3=A9_Draszik?= , Michael Turquette , Stephen Boyd , Krzysztof Kozlowski , Alim Akhtar , Sylwester Nawrocki , Chanwoo Choi Cc: linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, willmcvicker@google.com, kernel-team@android.com, Tudor Ambarus X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1755603952; l=6621; i=tudor.ambarus@linaro.org; s=20241212; h=from:subject:message-id; bh=j0BnWAhDqW93980MJMTG4FCn6QvHbgEEGRYAeb0s4W0=; b=KTiIalOm1UBeH7L/m3ZP8PgxAwNUu4gW37VVDI7lJrJMmvBPyeXjemeUn04pDogpe84GEjvVP QLEWsW4HaFSAa3LCLpnOovFdrk8Ou6Qwe8TRNrqJYzNzY0FnEyM9Ce1 X-Developer-Key: i=tudor.ambarus@linaro.org; a=ed25519; pk=uQzE0NXo3dIjeowMTOPCpIiPHEz12IA/MbyzrZVh9WI= Add ACPM DVFS protocol handler. It constructs DVFS messages that the APM firmware can understand. Signed-off-by: Tudor Ambarus --- drivers/firmware/samsung/Makefile | 4 +- drivers/firmware/samsung/exynos-acpm-dvfs.c | 85 ++++++++++++++++++= ++++ drivers/firmware/samsung/exynos-acpm-dvfs.h | 21 ++++++ drivers/firmware/samsung/exynos-acpm.c | 5 ++ .../linux/firmware/samsung/exynos-acpm-protocol.h | 10 +++ 5 files changed, 124 insertions(+), 1 deletion(-) diff --git a/drivers/firmware/samsung/Makefile b/drivers/firmware/samsung/M= akefile index 7b4c9f6f34f54fd731886d97a615fe1aa97ba9a0..80d4f89b33a9558b68c9083da67= 5c70ec3d05f19 100644 --- a/drivers/firmware/samsung/Makefile +++ b/drivers/firmware/samsung/Makefile @@ -1,4 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only =20 -acpm-protocol-objs :=3D exynos-acpm.o exynos-acpm-pmic.o +acpm-protocol-objs :=3D exynos-acpm.o +acpm-protocol-objs +=3D exynos-acpm-pmic.o +acpm-protocol-objs +=3D exynos-acpm-dvfs.o obj-$(CONFIG_EXYNOS_ACPM_PROTOCOL) +=3D acpm-protocol.o diff --git a/drivers/firmware/samsung/exynos-acpm-dvfs.c b/drivers/firmware= /samsung/exynos-acpm-dvfs.c new file mode 100644 index 0000000000000000000000000000000000000000..ee457c1a3de2ff2e4395d9fc3ff= 4c13294473b2d --- /dev/null +++ b/drivers/firmware/samsung/exynos-acpm-dvfs.c @@ -0,0 +1,85 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2020 Samsung Electronics Co., Ltd. + * Copyright 2020 Google LLC. + * Copyright 2025 Linaro Ltd. + */ + +#include +#include +#include +#include +#include + +#include "exynos-acpm.h" +#include "exynos-acpm-dvfs.h" + +#define ACPM_DVFS_ID GENMASK(11, 0) +#define ACPM_DVFS_REQ_TYPE GENMASK(15, 0) + +enum exynos_acpm_dvfs_func { + ACPM_DVFS_FREQ_REQ, + ACPM_DVFS_FREQ_GET, +}; + +static void acpm_dvfs_set_xfer(struct acpm_xfer *xfer, u32 *cmd, size_t cm= dlen, + unsigned int acpm_chan_id, bool response) +{ + xfer->acpm_chan_id =3D acpm_chan_id; + xfer->txd =3D cmd; + xfer->txlen =3D cmdlen; + + if (response) { + xfer->rxd =3D cmd; + xfer->rxlen =3D cmdlen; + } +} + +static void acpm_dvfs_init_set_rate_cmd(u32 cmd[4], unsigned int clk_id, + unsigned long rate) +{ + cmd[0] =3D FIELD_PREP(ACPM_DVFS_ID, clk_id); + cmd[1] =3D rate / HZ_PER_KHZ; + cmd[2] =3D FIELD_PREP(ACPM_DVFS_REQ_TYPE, ACPM_DVFS_FREQ_REQ); + cmd[3] =3D ktime_to_ms(ktime_get()); +} + +int acpm_dvfs_set_rate(const struct acpm_handle *handle, + unsigned int acpm_chan_id, unsigned int clk_id, + unsigned long rate) +{ + struct acpm_xfer xfer =3D {0}; + u32 cmd[4]; + + acpm_dvfs_init_set_rate_cmd(cmd, clk_id, rate); + acpm_dvfs_set_xfer(&xfer, cmd, sizeof(cmd), acpm_chan_id, false); + + return acpm_do_xfer(handle, &xfer); +} + +static void acpm_dvfs_init_get_rate_cmd(u32 cmd[4], unsigned int clk_id, + u32 dbg_val) +{ + cmd[0] =3D FIELD_PREP(ACPM_DVFS_ID, clk_id); + cmd[1] =3D dbg_val; + cmd[2] =3D FIELD_PREP(ACPM_DVFS_REQ_TYPE, ACPM_DVFS_FREQ_GET); + cmd[3] =3D ktime_to_ms(ktime_get()); +} + +unsigned long acpm_dvfs_get_rate(const struct acpm_handle *handle, + unsigned int acpm_chan_id, unsigned int clk_id, + u32 dbg_val) +{ + struct acpm_xfer xfer; + unsigned int cmd[4]; + int ret; + + acpm_dvfs_init_get_rate_cmd(cmd, clk_id, dbg_val); + acpm_dvfs_set_xfer(&xfer, cmd, sizeof(cmd), acpm_chan_id, true); + + ret =3D acpm_do_xfer(handle, &xfer); + if (ret) + return 0; + + return xfer.rxd[1] * HZ_PER_KHZ; +} diff --git a/drivers/firmware/samsung/exynos-acpm-dvfs.h b/drivers/firmware= /samsung/exynos-acpm-dvfs.h new file mode 100644 index 0000000000000000000000000000000000000000..85a10bd535d118f2f36e9888e41= b9b705b08ea59 --- /dev/null +++ b/drivers/firmware/samsung/exynos-acpm-dvfs.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright 2020 Samsung Electronics Co., Ltd. + * Copyright 2020 Google LLC. + * Copyright 2025 Linaro Ltd. + */ +#ifndef __EXYNOS_ACPM_DVFS_H__ +#define __EXYNOS_ACPM_DVFS_H__ + +#include + +struct acpm_handle; + +int acpm_dvfs_set_rate(const struct acpm_handle *handle, + unsigned int acpm_chan_id, unsigned int id, + unsigned long rate); +unsigned long acpm_dvfs_get_rate(const struct acpm_handle *handle, + unsigned int acpm_chan_id, unsigned int clk_id, + u32 dbg_val); + +#endif /* __EXYNOS_ACPM_DVFS_H__ */ diff --git a/drivers/firmware/samsung/exynos-acpm.c b/drivers/firmware/sams= ung/exynos-acpm.c index 3a69fe3234c75e0b5a93cbea6bb210dc6f69d2a6..9fa0335ccf5db32892fdf09e8d4= b0a885a8f8fb5 100644 --- a/drivers/firmware/samsung/exynos-acpm.c +++ b/drivers/firmware/samsung/exynos-acpm.c @@ -29,6 +29,7 @@ #include =20 #include "exynos-acpm.h" +#include "exynos-acpm-dvfs.h" #include "exynos-acpm-pmic.h" =20 #define ACPM_PROTOCOL_SEQNUM GENMASK(21, 16) @@ -590,8 +591,12 @@ static int acpm_channels_init(struct acpm_info *acpm) */ static void acpm_setup_ops(struct acpm_info *acpm) { + struct acpm_dvfs_ops *dvfs_ops =3D &acpm->handle.ops.dvfs_ops; struct acpm_pmic_ops *pmic_ops =3D &acpm->handle.ops.pmic_ops; =20 + dvfs_ops->set_rate =3D acpm_dvfs_set_rate; + dvfs_ops->get_rate =3D acpm_dvfs_get_rate; + pmic_ops->read_reg =3D acpm_pmic_read_reg; pmic_ops->bulk_read =3D acpm_pmic_bulk_read; pmic_ops->write_reg =3D acpm_pmic_write_reg; diff --git a/include/linux/firmware/samsung/exynos-acpm-protocol.h b/includ= e/linux/firmware/samsung/exynos-acpm-protocol.h index f628bf1862c25fa018a2fe5e7e123bf05c5254b9..e41055316bb578bb8250a1b1177= f1059eeeb2611 100644 --- a/include/linux/firmware/samsung/exynos-acpm-protocol.h +++ b/include/linux/firmware/samsung/exynos-acpm-protocol.h @@ -13,6 +13,15 @@ struct acpm_handle; struct device_node; =20 +struct acpm_dvfs_ops { + int (*set_rate)(const struct acpm_handle *handle, + unsigned int acpm_chan_id, unsigned int clk_id, + unsigned long rate); + unsigned long (*get_rate)(const struct acpm_handle *handle, + unsigned int acpm_chan_id, + unsigned int clk_id, u32 dbg_val); +}; + struct acpm_pmic_ops { int (*read_reg)(const struct acpm_handle *handle, unsigned int acpm_chan_id, u8 type, u8 reg, u8 chan, @@ -32,6 +41,7 @@ struct acpm_pmic_ops { }; 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[35.187.92.245]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3c077788df7sm3430817f8f.48.2025.08.19.04.45.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Aug 2025 04:45:55 -0700 (PDT) From: Tudor Ambarus Date: Tue, 19 Aug 2025 11:45:38 +0000 Subject: [PATCH 3/3] clk: samsung: add Exynos ACPM clock driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250819-acpm-clk-v1-3-6bbd97474671@linaro.org> References: <20250819-acpm-clk-v1-0-6bbd97474671@linaro.org> In-Reply-To: <20250819-acpm-clk-v1-0-6bbd97474671@linaro.org> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Peter Griffin , =?utf-8?q?Andr=C3=A9_Draszik?= , Michael Turquette , Stephen Boyd , Krzysztof Kozlowski , Alim Akhtar , Sylwester Nawrocki , Chanwoo Choi Cc: linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, willmcvicker@google.com, kernel-team@android.com, Tudor Ambarus X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1755603952; l=7617; i=tudor.ambarus@linaro.org; s=20241212; h=from:subject:message-id; bh=8q8yoH0OH0fUK6u5BVFDQi4Ifhan8hzBsvGgsfXDGMU=; b=jxt0eQAwhd6DT9TsOur1oHjS9c7qn2o8JHVXwh1iXrKemD+TMGRIF/c1A3mQ6S8uUBRB/Gj+w JSq9nsCgOR8C9NcNGgFYfkyO5z5ydEhAoZC8DCIZ2Wuhdkgo3JIYJTs X-Developer-Key: i=tudor.ambarus@linaro.org; a=ed25519; pk=uQzE0NXo3dIjeowMTOPCpIiPHEz12IA/MbyzrZVh9WI= Add the Exynos ACPM clock driver. It provides support for clocks that are controlled by firmware that implements the ACPM interface. Signed-off-by: Tudor Ambarus --- drivers/clk/samsung/Kconfig | 10 +++ drivers/clk/samsung/Makefile | 1 + drivers/clk/samsung/clk-acpm.c | 192 +++++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 203 insertions(+) diff --git a/drivers/clk/samsung/Kconfig b/drivers/clk/samsung/Kconfig index 76a494e95027af26272e30876a87ac293bd56dfa..fe05212d7dd882adde9cd5c656c= d0d58d501c42f 100644 --- a/drivers/clk/samsung/Kconfig +++ b/drivers/clk/samsung/Kconfig @@ -95,6 +95,16 @@ config EXYNOS_CLKOUT status of the certains clocks from SoC, but it could also be tied to other devices as an input clock. =20 +config EXYNOS_ACPM_CLK + tristate "Clock driver controlled via ACPM interface" + depends on EXYNOS_ACPM_PROTOCOL || COMPILE_TEST + help + This driver provides support for clocks that are controlled by + firmware that implements the ACPM interface. + + This driver uses the ACPM interface to interact with the firmware + providing all the clock controlls. + config TESLA_FSD_COMMON_CLK bool "Tesla FSD clock controller support" if COMPILE_TEST depends on COMMON_CLK_SAMSUNG diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile index b77fe288e4bb484c68d1ff497acc0b83d132ea03..04b63436b12f6f5169575d74f54= b105e97bbb052 100644 --- a/drivers/clk/samsung/Makefile +++ b/drivers/clk/samsung/Makefile @@ -27,6 +27,7 @@ obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) +=3D clk-exynos990.o obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) +=3D clk-exynosautov9.o obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) +=3D clk-exynosautov920.o obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) +=3D clk-gs101.o +obj-$(CONFIG_EXYNOS_ACPM_CLK) +=3D clk-acpm.o obj-$(CONFIG_S3C64XX_COMMON_CLK) +=3D clk-s3c64xx.o obj-$(CONFIG_S5PV210_COMMON_CLK) +=3D clk-s5pv210.o clk-s5pv210-audss.o obj-$(CONFIG_TESLA_FSD_COMMON_CLK) +=3D clk-fsd.o diff --git a/drivers/clk/samsung/clk-acpm.c b/drivers/clk/samsung/clk-acpm.c new file mode 100644 index 0000000000000000000000000000000000000000..e3e648331ad54072876f52a63b1= 1fe259a0b9be2 --- /dev/null +++ b/drivers/clk/samsung/clk-acpm.c @@ -0,0 +1,192 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Samsung Exynos ACPM protocol based clock driver. + * + * Copyright 2025 Linaro Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +struct acpm_clk { + u32 id; + struct clk_hw hw; + unsigned int acpm_chan_id; + const struct acpm_handle *handle; +}; + +#define to_acpm_clk(clk) container_of(clk, struct acpm_clk, hw) + +struct acpm_clk_variant { + unsigned int id; + const char *name; +}; + +struct acpm_clk_match_data { + const struct acpm_clk_variant *clks; + unsigned int nr_clks; + unsigned int acpm_chan_id; +}; + +static unsigned long acpm_clk_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct acpm_clk *clk =3D to_acpm_clk(hw); + + return clk->handle->ops.dvfs_ops.get_rate(clk->handle, + clk->acpm_chan_id, clk->id, 0); +} + +static long acpm_clk_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *parent_rate) +{ + /* + * We can't figure out what rate it will be, so just return the + * rate back to the caller. acpm_clk_recalc_rate() will be called + * after the rate is set and we'll know what rate the clock is + * running at then. + */ + return rate; +} + +static int acpm_clk_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct acpm_clk *clk =3D to_acpm_clk(hw); + + return clk->handle->ops.dvfs_ops.set_rate(clk->handle, + clk->acpm_chan_id, clk->id, rate); +} + +static const struct clk_ops acpm_clk_ops =3D { + .recalc_rate =3D acpm_clk_recalc_rate, + .round_rate =3D acpm_clk_round_rate, + .set_rate =3D acpm_clk_set_rate, +}; + +static int __init acpm_clk_ops_init(struct device *dev, struct acpm_clk *a= clk, + const char *name) +{ + struct clk_init_data init =3D {}; + + init.name =3D name; + init.ops =3D &acpm_clk_ops; + aclk->hw.init =3D &init; + + return devm_clk_hw_register(dev, &aclk->hw); +} + +static int __init acpm_clk_probe(struct platform_device *pdev) +{ + const struct acpm_clk_match_data *match_data; + const struct acpm_handle *acpm_handle; + struct clk_hw_onecell_data *clk_data; + struct clk_hw **hws; + struct device *dev =3D &pdev->dev; + struct acpm_clk *aclks; + unsigned int acpm_chan_id; + int i, err, count; + + acpm_handle =3D devm_acpm_get_by_node(dev, dev->parent->of_node); + if (IS_ERR(acpm_handle)) + return dev_err_probe(dev, PTR_ERR(acpm_handle), + "Failed to get acpm handle.\n"); + + match_data =3D of_device_get_match_data(dev); + if (!match_data) + return dev_err_probe(dev, -EINVAL, + "Failed to get match data.\n"); + + count =3D match_data->nr_clks; + acpm_chan_id =3D match_data->acpm_chan_id; + + clk_data =3D devm_kzalloc(dev, struct_size(clk_data, hws, count), + GFP_KERNEL); + if (!clk_data) + return -ENOMEM; + + clk_data->num =3D count; + hws =3D clk_data->hws; + + aclks =3D devm_kcalloc(dev, count, sizeof(*aclks), GFP_KERNEL); + if (!aclks) + return -ENOMEM; + + for (i =3D 0; i < count; i++) { + const struct acpm_clk_variant *variant =3D &match_data->clks[i]; + struct acpm_clk *aclk =3D &aclks[i]; + + hws[i] =3D &aclk->hw; + + aclk->id =3D variant->id; + aclk->handle =3D acpm_handle; + aclk->acpm_chan_id =3D acpm_chan_id; + + err =3D acpm_clk_ops_init(dev, aclk, variant->name); + if (err) + return dev_err_probe(dev, err, + "Failed to register clock.\n"); + } + + return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, + clk_data); +} + +#define ACPM_CLK(_id, cname) \ + { \ + .id =3D _id, \ + .name =3D cname, \ + } + +static const struct acpm_clk_variant gs101_acpm_clks[] __initconst =3D { + ACPM_CLK(CLK_ACPM_DVFS_MIF, "mif"), + ACPM_CLK(CLK_ACPM_DVFS_INT, "int"), + ACPM_CLK(CLK_ACPM_DVFS_CPUCL0, "cpucl0"), + ACPM_CLK(CLK_ACPM_DVFS_CPUCL1, "cpucl1"), + ACPM_CLK(CLK_ACPM_DVFS_CPUCL2, "cpucl2"), + ACPM_CLK(CLK_ACPM_DVFS_G3D, "g3d"), + ACPM_CLK(CLK_ACPM_DVFS_G3DL2, "g3dl2"), + ACPM_CLK(CLK_ACPM_DVFS_TPU, "tpu"), + ACPM_CLK(CLK_ACPM_DVFS_INTCAM, "intcam"), + ACPM_CLK(CLK_ACPM_DVFS_TNR, "tnr"), + ACPM_CLK(CLK_ACPM_DVFS_CAM, "cam"), + ACPM_CLK(CLK_ACPM_DVFS_MFC, "mfc"), + ACPM_CLK(CLK_ACPM_DVFS_DISP, "disp"), + ACPM_CLK(CLK_ACPM_DVFS_BO, "b0"), +}; + +static const struct acpm_clk_match_data acpm_clk_gs101 __initconst =3D { + .clks =3D gs101_acpm_clks, + .nr_clks =3D ARRAY_SIZE(gs101_acpm_clks), + .acpm_chan_id =3D 0, +}; + +static const struct of_device_id acpm_clk_ids[] __initconst =3D { + { + .compatible =3D "google,gs101-acpm-dvfs-clocks", + .data =3D &acpm_clk_gs101, + }, + {} +}; +MODULE_DEVICE_TABLE(of, acpm_clk_ids); + +static struct platform_driver acpm_clk_driver __refdata =3D { + .driver =3D { + .name =3D "acpm-clocks", + .of_match_table =3D acpm_clk_ids, + }, + .probe =3D acpm_clk_probe, +}; +module_platform_driver(acpm_clk_driver); + +MODULE_AUTHOR("Tudor Ambarus "); +MODULE_DESCRIPTION("Samsung Exynos ACPM clock driver"); +MODULE_LICENSE("GPL"); --=20 2.51.0.rc1.167.g924127e9c0-goog