From nobody Sat Oct 4 11:13:56 2025 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 9774D2566D9; Mon, 18 Aug 2025 16:29:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755534599; cv=none; b=exFJ57or6svsvqT38o6h9/D8y0U+8KoEqmNwOL0X4w9KV54N7aFfwgs01ixaTdZeuVZ5W8kovmCjRbfaJUlxHQmRPTTyk7UT1wKUbjfI/BQ8bizLUJx0eHjnVlPo1U7n+yHvPa6pSkrHwbXoH4U7Frlf/VUuuGsb+LPpejAcKsA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755534599; c=relaxed/simple; bh=T+CHYMosa15j4q7JMOZVBhxCiDrqz/IMhhJuUgjlXoE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Vn3z/0HOKXDFC3Uk7xYbVK6rqwz5GYqwv+FNtnqVPQJEMAYqchTOvsX5sagcJk45d2UeNF5llVJNIBkHf9ylk0dY4uTUDfpxtg8OjiA2B/6qiOXNohHFZb/HIJa6HsdJLnn/YyQL74wf0CNkeMHcBOboixulWQ9LE+zeq+wtkfQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: mfvhLB+iQfaiD0bNA8RsfQ== X-CSE-MsgGUID: D7XIspMhRoKIeJnF8u4MMg== Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 19 Aug 2025 01:29:54 +0900 Received: from ubuntu.adwin.renesas.com (unknown [10.24.0.173]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 64E2D4016EE4; Tue, 19 Aug 2025 01:29:47 +0900 (JST) From: John Madieu To: geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, rafael@kernel.org, daniel.lezcano@linaro.org, rui.zhang@intel.com, lukasz.luba@arm.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, catalin.marinas@arm.com, will@kernel.org Cc: john.madieu@gmail.com, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, biju.das.jz@bp.renesas.com, linux-arm-kernel@lists.infradead.org, John Madieu Subject: [PATCH v7 5/6] arm64: dts: renesas: r9a09g047: Add TSU node Date: Mon, 18 Aug 2025 18:28:51 +0200 Message-ID: <20250818162859.9661-6-john.madieu.xa@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250818162859.9661-1-john.madieu.xa@bp.renesas.com> References: <20250818162859.9661-1-john.madieu.xa@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add TSU node along with thermal zones and keep it enabled in the SoC DTSI. Signed-off-by: John Madieu --- Changes: v1 -> v2: Fix IRQ names v2 -> v3: remove useless 'renesas,tsu-operating-mode' property' v3 -> v4: no changes v5: no changes v6: no changes v7: updated both property name and specifier () for trim pr= operty. arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 48 ++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/d= ts/renesas/r9a09g047.dtsi index 7cbba492edd5..6744e17ae127 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi @@ -64,6 +64,7 @@ cpu0: cpu@0 { next-level-cache =3D <&L3_CA55>; enable-method =3D "psci"; clocks =3D <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK0>; + #cooling-cells =3D <2>; operating-points-v2 =3D <&cluster0_opp>; }; =20 @@ -74,6 +75,7 @@ cpu1: cpu@100 { next-level-cache =3D <&L3_CA55>; enable-method =3D "psci"; clocks =3D <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK1>; + #cooling-cells =3D <2>; operating-points-v2 =3D <&cluster0_opp>; }; =20 @@ -84,6 +86,7 @@ cpu2: cpu@200 { next-level-cache =3D <&L3_CA55>; enable-method =3D "psci"; clocks =3D <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK2>; + #cooling-cells =3D <2>; operating-points-v2 =3D <&cluster0_opp>; }; =20 @@ -94,6 +97,7 @@ cpu3: cpu@300 { next-level-cache =3D <&L3_CA55>; enable-method =3D "psci"; clocks =3D <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK3>; + #cooling-cells =3D <2>; operating-points-v2 =3D <&cluster0_opp>; }; =20 @@ -413,6 +417,19 @@ wdt3: watchdog@13000400 { status =3D "disabled"; }; =20 + tsu: thermal@14002000 { + compatible =3D "renesas,r9a09g047-tsu"; + reg =3D <0 0x14002000 0 0x1000>; + interrupts =3D , + ; + interrupt-names =3D "adi", "adcmpi"; + clocks =3D <&cpg CPG_MOD 0x10a>; + resets =3D <&cpg 0xf8>; + power-domains =3D <&cpg>; + #thermal-sensor-cells =3D <0>; + renesas,tsu-trim =3D <&sys 0x330>; + }; + i2c0: i2c@14400400 { compatible =3D "renesas,riic-r9a09g047", "renesas,riic-r9a09g057"; reg =3D <0 0x14400400 0 0x400>; @@ -971,6 +988,37 @@ stmmac_axi_setup: stmmac-axi-config { snps,blen =3D <16 8 4 0 0 0 0>; }; =20 + thermal-zones { + cpu-thermal { + polling-delay =3D <1000>; + polling-delay-passive =3D <250>; + thermal-sensors =3D <&tsu>; + + cooling-maps { + map0 { + trip =3D <&target>; + cooling-device =3D <&cpu0 0 3>, <&cpu1 0 3>, + <&cpu2 0 3>, <&cpu3 0 3>; + contribution =3D <1024>; + }; + }; + + trips { + target: trip-point { + temperature =3D <95000>; + hysteresis =3D <1000>; + type =3D "passive"; + }; + + sensor_crit: sensor-crit { + temperature =3D <120000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + }; + timer { compatible =3D "arm,armv8-timer"; interrupts-extended =3D <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, --=20 2.25.1