From nobody Sat Oct 4 11:11:51 2025 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 117E7341ABA; Mon, 18 Aug 2025 16:34:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755534870; cv=none; b=N9V+xMP/Gp0VLRETGkmVTP+RQElRPIagSJTFsEolGwnOgX8FxHIOKJdG7jSw14T0KPsXw16Dh4ya15ck4V+7XpQw6hZUElwr1OcuerXN/D+BjCpDhWhKBO35cRZ0j48K0UamFye7ajma8UDvdABi7qeqxyQo1VVickVZNc2l2wU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755534870; c=relaxed/simple; bh=gICgLMDOvtCTooddIieMsQo98ka/WDTW80yOCjIBDPc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=OjMiEYmhP5EaejZziWoDg9Pvk2TQN61GUvuTc9ayxpFDFxoApDwgeeADlK+t6cu4DBIzO/qAC3MwPi7X0ACBxmvU55C0YJP5qY7EDK/PtEX2OMkzYZi/ol3BfHwPaRohMU1Mis60G27XO38caZJW6v2rnIqL7y1MiAPwKAnoyUc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: 4g7Tkn3oTzCGLch2gNB06w== X-CSE-MsgGUID: 4N+q+AU8T5CZyn7pobnHyA== Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 19 Aug 2025 01:29:22 +0900 Received: from ubuntu.adwin.renesas.com (unknown [10.24.0.173]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 8465B4016EDD; Tue, 19 Aug 2025 01:29:15 +0900 (JST) From: John Madieu To: geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, rafael@kernel.org, daniel.lezcano@linaro.org, rui.zhang@intel.com, lukasz.luba@arm.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, catalin.marinas@arm.com, will@kernel.org Cc: john.madieu@gmail.com, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, biju.das.jz@bp.renesas.com, linux-arm-kernel@lists.infradead.org, John Madieu , Claudiu Beznea Subject: [PATCH v7 1/6] soc: renesas: rz-sysc: Add syscon/regmap support Date: Mon, 18 Aug 2025 18:28:47 +0200 Message-ID: <20250818162859.9661-2-john.madieu.xa@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250818162859.9661-1-john.madieu.xa@bp.renesas.com> References: <20250818162859.9661-1-john.madieu.xa@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The RZ/G3E system controller has various registers that control or report some properties specific to individual IPs. The regmap is registered as a syscon device to allow these IP drivers to access the registers through the regmap API. As other RZ SoCs might have custom read/write callbacks or max-offsets, register a custom regmap configuration. Signed-off-by: John Madieu [claudiu.beznea: - do not check the match->data validity in rz_sysc_probe() as it is always valid - dinamically allocate regmap_cfg] Signed-off-by: Claudiu Beznea Reviewed-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Tested-by: Claudiu Beznea # on RZ/G3S --- Changes: v1 -> v2: no changes v2 -> v3: no changes v3 -> v4: no changes v4 -> v5: no changes v6: Addressed the review comments received at [1] v7: As this is a duplicate of [2], address comment received there, that is, use kzalloc() + kfree() for regmap_cfg. [1] https://lore.kernel.org/all/20250330214945.185725-2-john.madieu.xa@bp.r= enesas.com/ [2] https://lore.kernel.org/all/20250808061806.2729274-1-claudiu.beznea.uj@= bp.renesas.com/ drivers/soc/renesas/Kconfig | 1 + drivers/soc/renesas/r9a08g045-sysc.c | 1 + drivers/soc/renesas/r9a09g047-sys.c | 1 + drivers/soc/renesas/r9a09g057-sys.c | 1 + drivers/soc/renesas/rz-sysc.c | 28 +++++++++++++++++++++++++++- drivers/soc/renesas/rz-sysc.h | 2 ++ 6 files changed, 33 insertions(+), 1 deletion(-) diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig index 719b7f4f376f..c97e2a183388 100644 --- a/drivers/soc/renesas/Kconfig +++ b/drivers/soc/renesas/Kconfig @@ -449,6 +449,7 @@ config RST_RCAR =20 config SYSC_RZ bool "System controller for RZ SoCs" if COMPILE_TEST + select MFD_SYSCON =20 config SYSC_R9A08G045 bool "Renesas System controller support for R9A08G045 (RZ/G3S)" if COMPIL= E_TEST diff --git a/drivers/soc/renesas/r9a08g045-sysc.c b/drivers/soc/renesas/r9a= 08g045-sysc.c index f4db1431e036..0504d4e68761 100644 --- a/drivers/soc/renesas/r9a08g045-sysc.c +++ b/drivers/soc/renesas/r9a08g045-sysc.c @@ -20,4 +20,5 @@ static const struct rz_sysc_soc_id_init_data rzg3s_sysc_s= oc_id_init_data __initc =20 const struct rz_sysc_init_data rzg3s_sysc_init_data __initconst =3D { .soc_id_init_data =3D &rzg3s_sysc_soc_id_init_data, + .max_register =3D 0xe20, }; diff --git a/drivers/soc/renesas/r9a09g047-sys.c b/drivers/soc/renesas/r9a0= 9g047-sys.c index cd2eb7782cfe..2e8426c03050 100644 --- a/drivers/soc/renesas/r9a09g047-sys.c +++ b/drivers/soc/renesas/r9a09g047-sys.c @@ -64,4 +64,5 @@ static const struct rz_sysc_soc_id_init_data rzg3e_sys_so= c_id_init_data __initco =20 const struct rz_sysc_init_data rzg3e_sys_init_data =3D { .soc_id_init_data =3D &rzg3e_sys_soc_id_init_data, + .max_register =3D 0x170c, }; diff --git a/drivers/soc/renesas/r9a09g057-sys.c b/drivers/soc/renesas/r9a0= 9g057-sys.c index 4c21cc29edbc..e3390e7c7fe5 100644 --- a/drivers/soc/renesas/r9a09g057-sys.c +++ b/drivers/soc/renesas/r9a09g057-sys.c @@ -64,4 +64,5 @@ static const struct rz_sysc_soc_id_init_data rzv2h_sys_so= c_id_init_data __initco =20 const struct rz_sysc_init_data rzv2h_sys_init_data =3D { .soc_id_init_data =3D &rzv2h_sys_soc_id_init_data, + .max_register =3D 0x170c, }; diff --git a/drivers/soc/renesas/rz-sysc.c b/drivers/soc/renesas/rz-sysc.c index ffa65fb4dade..c06758faf19f 100644 --- a/drivers/soc/renesas/rz-sysc.c +++ b/drivers/soc/renesas/rz-sysc.c @@ -6,8 +6,10 @@ */ =20 #include +#include #include #include +#include #include =20 #include "rz-sysc.h" @@ -100,14 +102,23 @@ MODULE_DEVICE_TABLE(of, rz_sysc_match); =20 static int rz_sysc_probe(struct platform_device *pdev) { + const struct rz_sysc_init_data *data; const struct of_device_id *match; struct device *dev =3D &pdev->dev; + struct regmap *regmap; struct rz_sysc *sysc; + int ret; + + struct regmap_config *regmap_cfg __free(kfree) =3D kzalloc(sizeof(*regmap= _cfg), GFP_KERNEL); + if (!regmap_cfg) + return -ENOMEM; =20 match =3D of_match_node(rz_sysc_match, dev->of_node); if (!match) return -ENODEV; =20 + data =3D match->data; + sysc =3D devm_kzalloc(dev, sizeof(*sysc), GFP_KERNEL); if (!sysc) return -ENOMEM; @@ -117,7 +128,22 @@ static int rz_sysc_probe(struct platform_device *pdev) return PTR_ERR(sysc->base); =20 sysc->dev =3D dev; - return rz_sysc_soc_init(sysc, match); + ret =3D rz_sysc_soc_init(sysc, match); + if (ret) + return ret; + + regmap_cfg->name =3D "rz_sysc_regs"; + regmap_cfg->reg_bits =3D 32; + regmap_cfg->reg_stride =3D 4; + regmap_cfg->val_bits =3D 32; + regmap_cfg->fast_io =3D true; + regmap_cfg->max_register =3D data->max_register; + + regmap =3D devm_regmap_init_mmio(dev, sysc->base, regmap_cfg); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + return of_syscon_register_regmap(dev->of_node, regmap); } =20 static struct platform_driver rz_sysc_driver =3D { diff --git a/drivers/soc/renesas/rz-sysc.h b/drivers/soc/renesas/rz-sysc.h index 56bc047a1bff..8eec355d5d56 100644 --- a/drivers/soc/renesas/rz-sysc.h +++ b/drivers/soc/renesas/rz-sysc.h @@ -34,9 +34,11 @@ struct rz_sysc_soc_id_init_data { /** * struct rz_sysc_init_data - RZ SYSC initialization data * @soc_id_init_data: RZ SYSC SoC ID initialization data + * @max_register: Maximum SYSC register offset to be used by the regmap co= nfig */ struct rz_sysc_init_data { const struct rz_sysc_soc_id_init_data *soc_id_init_data; + u32 max_register; }; =20 extern const struct rz_sysc_init_data rzg3e_sys_init_data; --=20 2.25.1