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[151.229.67.101]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-45a1c6bd172sm187895305e9.6.2025.08.18.08.08.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Aug 2025 08:08:02 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Andrew Lunn , Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Florian Fainelli , Geert Uytterhoeven Cc: linux-renesas-soc@vger.kernel.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Prabhakar , stable@kernel.org Subject: [PATCH] net: pcs-rzn1-miic: Correct MODCTRL register offset Date: Mon, 18 Aug 2025 16:07:57 +0100 Message-ID: <20250818150757.3977908-1-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.50.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Correct the Mode Control Register (MODCTRL) offset for RZ/N MIIC. According to the R-IN Engine and Ethernet Peripherals Manual (Rev.1.30) [0], Table 10.1 "Ethernet Accessory Register List", MODCTRL is at offset 0x8, not 0x20 as previously defined. [0] https://www.renesas.com/en/document/mah/rzn1d-group-rzn1s-group-rzn1l-g= roup-users-manual-r-engine-and-ethernet-peripherals?r=3D1054571 Fixes: 7dc54d3b8d91 ("net: pcs: add Renesas MII converter driver") Cc: stable@kernel.org Signed-off-by: Lad Prabhakar Reviewed-by: Wolfram Sang --- drivers/net/pcs/pcs-rzn1-miic.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/pcs/pcs-rzn1-miic.c b/drivers/net/pcs/pcs-rzn1-mii= c.c index d79bb9b06cd2..ce73d9474d5b 100644 --- a/drivers/net/pcs/pcs-rzn1-miic.c +++ b/drivers/net/pcs/pcs-rzn1-miic.c @@ -19,7 +19,7 @@ #define MIIC_PRCMD 0x0 #define MIIC_ESID_CODE 0x4 =20 -#define MIIC_MODCTRL 0x20 +#define MIIC_MODCTRL 0x8 #define MIIC_MODCTRL_SW_MODE GENMASK(4, 0) =20 #define MIIC_CONVCTRL(port) (0x100 + (port) * 4) --=20 2.50.1