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([178.197.219.123]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-afcdce73e2esm837537366b.39.2025.08.18.07.21.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Aug 2025 07:21:43 -0700 (PDT) From: Krzysztof Kozlowski To: Bjorn Helgaas , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thippeswamy Havalige , Bjorn Andersson , linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH] dt-bindings: PCI: Correct example indentation Date: Mon, 18 Aug 2025 16:21:39 +0200 Message-ID: <20250818142138.129327-2-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.48.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=5299; i=krzysztof.kozlowski@linaro.org; h=from:subject; bh=BBC/SN2tgiFfIsTJ+RWHDHrb8tIq6PdDhwdUXUNjggU=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBoozbyzFA4VT4xhvO6BqBHnVAKh8r0Z9h+iH/0x gojCib/ZkSJAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCaKM28gAKCRDBN2bmhouD 14ETEACSPncNUXTEglIktU9uqeatZH8RnHvdlDUwFWcuMAhCUrRz5U6n1/4x6YmKc4l41O4TNLu zzbmcXSUWZNOTbIGRDRYRix4ty7ZGv5YV7mLrRF+TRa6MN1VLbifTO0u7TA2oy6adpWTwKcZOzP GOJulwGkApHzONM4skSr64yIon8AvUEzmk45fsdT/MC99hzwAEfNOpJS6jShJoT4V4z1Wy5y0Q9 D+RmLw5CKPYA3iE5V7FPQE0zNTcGyVUh3d7yu1VzWhrnFEW6LplJtY3X9WBuT1yFqBHoAFoYWxO 0HYMONO3Jbf64r65XYO2rULZYUdyhvuGNwn2Lkn2rZPFy1WKuDKxmXdMkbKubVnNWfdfeygXfKG j3v8TsjnQ5uOk1EiqiuQrpsD+G144Uhd/TDU3zqX1SzQ9CQdiBtmdmdYLyA0Y8f+qpFoan7MEFw Y16Nm9/9QOdLmQf1iTkt14YGc0HPkTLBk+qpOOYK7virTE2WUe6V15reLFV7e5MShp7R4VaZZ/4 eInn8TXB9dkdmIIT53wGxtf399h+1yPG65rsD5rr0LZJPyQfNUvrya603hPOBSgQ/VsfIFLlHLR aaYjG24LZ939Srmc/5ig7ohYl1OzatU+X9k2OgUXZjr5GoGJPmKyHkqWMwBrs+ercJLStqmIGzg OXt8qctGwamFf0g== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" DTS example in the bindings should be indented with 2- or 4-spaces, so correct a mixture of different styles to keep consistent 4-spaces. Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring (Arm) --- .../bindings/pci/amd,versal2-mdb-host.yaml | 2 +- .../bindings/pci/qcom,pcie-sa8255p.yaml | 74 +++++++++---------- 2 files changed, 38 insertions(+), 38 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/amd,versal2-mdb-host.yam= l b/Documentation/devicetree/bindings/pci/amd,versal2-mdb-host.yaml index 421e1116ae7e..406c15e1dee1 100644 --- a/Documentation/devicetree/bindings/pci/amd,versal2-mdb-host.yaml +++ b/Documentation/devicetree/bindings/pci/amd,versal2-mdb-host.yaml @@ -138,6 +138,6 @@ examples: #address-cells =3D <0>; #interrupt-cells =3D <1>; interrupt-controller; - }; + }; }; }; diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sa8255p.yaml b= /Documentation/devicetree/bindings/pci/qcom,pcie-sa8255p.yaml index ef705a02fcd9..bdddd4f499d1 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-sa8255p.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sa8255p.yaml @@ -77,46 +77,46 @@ examples: #size-cells =3D <2>; =20 pci@1c00000 { - compatible =3D "qcom,pcie-sa8255p"; - reg =3D <0x4 0x00000000 0 0x10000000>; - device_type =3D "pci"; - #address-cells =3D <3>; - #size-cells =3D <2>; - ranges =3D <0x02000000 0x0 0x40100000 0x0 0x40100000 0x0 0x1ff0= 0000>, - <0x43000000 0x4 0x10100000 0x4 0x10100000 0x0 0x400000= 00>; - bus-range =3D <0x00 0xff>; - dma-coherent; - linux,pci-domain =3D <0>; - power-domains =3D <&scmi5_pd 0>; - iommu-map =3D <0x0 &pcie_smmu 0x0000 0x1>, - <0x100 &pcie_smmu 0x0001 0x1>; - interrupt-parent =3D <&intc>; - interrupts =3D , - , - , - , - , - , - , - ; - interrupt-names =3D "msi0", "msi1", "msi2", "msi3", - "msi4", "msi5", "msi6", "msi7"; + compatible =3D "qcom,pcie-sa8255p"; + reg =3D <0x4 0x00000000 0 0x10000000>; + device_type =3D "pci"; + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges =3D <0x02000000 0x0 0x40100000 0x0 0x40100000 0x0 0x1ff= 00000>, + <0x43000000 0x4 0x10100000 0x4 0x10100000 0x0 0x40000= 000>; + bus-range =3D <0x00 0xff>; + dma-coherent; + linux,pci-domain =3D <0>; + power-domains =3D <&scmi5_pd 0>; + iommu-map =3D <0x0 &pcie_smmu 0x0000 0x1>, + <0x100 &pcie_smmu 0x0001 0x1>; + interrupt-parent =3D <&intc>; + interrupts =3D , + , + , + , + , + , + , + ; + interrupt-names =3D "msi0", "msi1", "msi2", "msi3", + "msi4", "msi5", "msi6", "msi7"; =20 - #interrupt-cells =3D <1>; - interrupt-map-mask =3D <0 0 0 0x7>; - interrupt-map =3D <0 0 0 1 &intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIG= H>, - <0 0 0 2 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &intc GIC_SPI 148 IRQ_TYPE_LEVEL_HI= GH>, + <0 0 0 2 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH= >, + <0 0 0 3 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH= >, + <0 0 0 4 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH= >; =20 - pcie@0 { - device_type =3D "pci"; - reg =3D <0x0 0x0 0x0 0x0 0x0>; - bus-range =3D <0x01 0xff>; + pcie@0 { + device_type =3D "pci"; + reg =3D <0x0 0x0 0x0 0x0 0x0>; + bus-range =3D <0x01 0xff>; =20 - #address-cells =3D <3>; - #size-cells =3D <2>; - ranges; + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges; }; }; }; --=20 2.48.1