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charset="utf-8" On some SoCs, regulators are shared between the QMP UFS PHY and other IP blocks. Hence convey maximum load requirement for UFS PHY to the regulator framework as supply's capabilities or mode(Low Power Mode or High Power Mode) change depending on the maximum potential load at any given time, which the regulator driver must be aware of. This helps to ensure stable operation and proper power management, set the regulator load before enabling the regulators. This patch adds: - vreg_load_uA field to qmp_phy_cfg structure for load value arrays. - Enhanced qmp_ufs_vreg_init() to set init_load_uA when loads are specified. Configurations without specific load requirements will continue to work unchanged, as init_load_uA remains zero-initialized when vreg_load_uA is not provided. Signed-off-by: Nitin Rawat --- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm= /phy-qcom-qmp-ufs.c index 9c69c77d10c8..f7a4a8334026 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -1110,6 +1110,9 @@ struct qmp_phy_cfg { const char * const *vreg_list; int num_vregs; + /* regulator load values in same order as vreg_list */ + const int *vreg_load_ua; + /* array of registers with different offsets */ const unsigned int *regs; @@ -1901,8 +1904,11 @@ static int qmp_ufs_vreg_init(struct qmp_ufs *qmp) if (!qmp->vregs) return -ENOMEM; - for (i =3D 0; i < num; i++) + for (i =3D 0; i < num; i++) { qmp->vregs[i].supply =3D cfg->vreg_list[i]; + if (cfg->vreg_load_ua) + qmp->vregs[i].init_load_uA =3D cfg->vreg_load_ua[i]; + } return devm_regulator_bulk_get(dev, num, qmp->vregs); } -- 2.48.1 From nobody Sat Oct 4 09:40:56 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E014127B342; 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charset="utf-8" Add regulator load configuration for SM8550 and SM8750 UFS PHY. This ensure proper regulator load management and mode selection for optimal power efficiency on these SoC platforms where regulators may be shared with other IP blocks. The load requirements are: - SM8550: vdda-phy=3D205000uA, vdda-pll=3D17500uA - SM8750: vdda-phy=3D213000uA, vdda-pll=3D18300uA Signed-off-by: Nitin Rawat --- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm= /phy-qcom-qmp-ufs.c index f7a4a8334026..50875d9609f6 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -1172,6 +1172,17 @@ static const char * const qmp_phy_vreg_l[] =3D { "vdda-phy", "vdda-pll", }; +/* Regulator load arrays for specific configurations */ +static const int sm8650_vreg_load_ua[] =3D { + 205000, /* vdda-phy */ + 17500, /* vdda-pll */ +}; + +static const int sm8750_vreg_load_ua[] =3D { + 213000, /* vdda-phy */ + 18300, /* vdda-pll */ +}; + static const struct qmp_ufs_offsets qmp_ufs_offsets =3D { .serdes =3D 0, .pcs =3D 0xc00, @@ -1642,6 +1653,7 @@ static const struct qmp_phy_cfg sm8650_ufsphy_cfg =3D= { .vreg_list =3D qmp_phy_vreg_l, .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), + .vreg_load_ua =3D sm8650_vreg_load_ua, .regs =3D ufsphy_v6_regs_layout, }; @@ -1680,6 +1692,7 @@ static const struct qmp_phy_cfg sm8750_ufsphy_cfg =3D= { .vreg_list =3D qmp_phy_vreg_l, .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), + .vreg_load_ua =3D sm8750_vreg_load_ua, .regs =3D ufsphy_v6_regs_layout, }; -- 2.48.1