From nobody Sat Oct 4 09:42:05 2025 Received: from mail-m49197.qiye.163.com (mail-m49197.qiye.163.com [45.254.49.197]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3CC9121CC49; Mon, 18 Aug 2025 10:00:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.254.49.197 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755511228; cv=none; b=HLrPkHw8GYH4QZMyng8G2TJThDu6hapK1N68lgjVNkeIraR5wXfRK6kmSLYva59WmLt6V8mM1t70A7644JkJMV6DcKQtFRokC53UASpFrT+SVnLXdc5o8rlYUkxm0YCOMMZvNRekGlasIhQzcllDPHgqvfjMZi2uloVEY3ZVtQo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755511228; c=relaxed/simple; bh=2NxO0Gc3+LC1yksxA/fojlVlxNxTP7hES0U6g0mu7B0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=MuVPZdcZ3Qn1dZp4BBJfWbk33infmEhofdJp7HNpnpiOJfTeqfX7J7MIhdlTDoMra36BiG4/blzR6iIEMwIPwVVcOR0yry8BO9F7wMCfJXNr1jzgEoaXCQAOWnThQNXVSs5MdtU+/8Dmyor2EHsli9IWfdyTddLMsO4kJ4bq/XY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=jmu.edu.cn; spf=pass smtp.mailfrom=jmu.edu.cn; arc=none smtp.client-ip=45.254.49.197 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=jmu.edu.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=jmu.edu.cn Received: from localhost.localdomain (unknown [119.122.213.154]) by smtp.qiye.163.com (Hmail) with ESMTP id 1fbaa9cfe; Mon, 18 Aug 2025 18:00:16 +0800 (GMT+08:00) From: Chukun Pan To: Heiko Stuebner Cc: Chukun Pan , Rob Herring , Conor Dooley , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 1/4] dt-bindings: vendor-prefixes: Add HINLINK Date: Mon, 18 Aug 2025 18:00:06 +0800 Message-Id: <20250818100009.170202-2-amadeus@jmu.edu.cn> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250818100009.170202-1-amadeus@jmu.edu.cn> References: <20250818100009.170202-1-amadeus@jmu.edu.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-HM-Tid: 0a98bc9f57fe03a2kunm3d9619f636a237 X-HM-MType: 10 X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFITzdXWS1ZQUlXWQ8JGhUIEh9ZQVkaQ0xMVh9MH05LGkwYGhpITFYeHw5VEwETFhoSFy QUDg9ZV1kYEgtZQVlKSkJVSklJVUlKSFVKTk9ZV1kWGg8SFR0UWUFZT0tIVUpLSEpOTE5VSktLVU pCS0tZBg++ Content-Type: text/plain; charset="utf-8" Add vendor prefix for HINLINK, which is an SBC manufacturer. Link: https://www.hinlink.cn/ Signed-off-by: Chukun Pan Acked-by: Conor Dooley --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Docum= entation/devicetree/bindings/vendor-prefixes.yaml index a92261b10c52..7ce1970d3125 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -648,6 +648,8 @@ patternProperties: description: HiDeep Inc. "^himax,.*": description: Himax Technologies, Inc. + "^hinlink,.*": + description: Shenzhen HINLINK Technology Co., Ltd. "^hirschmann,.*": description: Hirschmann Automation and Control GmbH "^hisi,.*": --=20 2.25.1 From nobody Sat Oct 4 09:42:05 2025 Received: from mail-m49198.qiye.163.com (mail-m49198.qiye.163.com [45.254.49.198]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7B22731062A; Mon, 18 Aug 2025 10:00:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.254.49.198 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755511229; cv=none; b=QcbZwJyruSQJRKk7H+w1BxjCzmwbixrJoR6GQJzb3GTAcshOHJz2UNX3RyZ0R76obaqqxQiDpozd/k6Itds1B+wJNWN7uZlx7pLE7kaYV+EOH2oTIRJlne4fyk/+FCSpWzg5ZlM5NINlJbM0MwmQFoc/r047Ug3m32Btb/Bb314= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755511229; c=relaxed/simple; bh=rQgEBfhbD+WshUYIJAJPehHZG8Trqro++lau4ggYLpA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=hOcJlEl0cGv4PKMLIoPewYsQiaTSbHYGx/2M6T9szoqMwRVlcAnfchHnv/fr3lhGx7JO/R7HP2zGiD3X6MjOmRZq6Jdxudjl2eHRTmUf9foamxglx6YuUwAIc/xX+KKzc7EJsnEZXAULWmRSp+N9YNkiczsqkEBgVbWct9EkMAU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=jmu.edu.cn; spf=pass smtp.mailfrom=jmu.edu.cn; arc=none smtp.client-ip=45.254.49.198 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=jmu.edu.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=jmu.edu.cn Received: from localhost.localdomain (unknown [119.122.213.154]) by smtp.qiye.163.com (Hmail) with ESMTP id 1fbaa9d00; Mon, 18 Aug 2025 18:00:17 +0800 (GMT+08:00) From: Chukun Pan To: Heiko Stuebner Cc: Chukun Pan , Rob Herring , Conor Dooley , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 2/4] dt-bindings: arm: rockchip: Add HINLINK H66K / H68K Date: Mon, 18 Aug 2025 18:00:07 +0800 Message-Id: <20250818100009.170202-3-amadeus@jmu.edu.cn> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250818100009.170202-1-amadeus@jmu.edu.cn> References: <20250818100009.170202-1-amadeus@jmu.edu.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-HM-Tid: 0a98bc9f5efc03a2kunm3d9619f636a240 X-HM-MType: 10 X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFITzdXWS1ZQUlXWQ8JGhUIEh9ZQVkZHkIeVktCGkMdGkkdHUxKSFYeHw5VEwETFhoSFy QUDg9ZV1kYEgtZQVlKSkJVSklJVUlKSFVKTk9ZV1kWGg8SFR0UWUFZT0tIVUpLSEpOTE5VSktLVU pCS0tZBg++ Content-Type: text/plain; charset="utf-8" The HINLINK H66K/H68K are 2.5GbE SBC based on the RK3568 SoC. Add devicetree binding documentation for them. Signed-off-by: Chukun Pan Acked-by: Conor Dooley --- Documentation/devicetree/bindings/arm/rockchip.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Document= ation/devicetree/bindings/arm/rockchip.yaml index 28db6bd6aa5b..870c318fc8d4 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -683,6 +683,13 @@ properties: - const: hardkernel,odroid-m2 - const: rockchip,rk3588s =20 + - description: HINLINK H66K / H68K + items: + - enum: + - hinlink,h66k + - hinlink,h68k + - const: rockchip,rk3568 + - description: Hugsun X99 TV Box items: - const: hugsun,x99 --=20 2.25.1 From nobody Sat Oct 4 09:42:05 2025 Received: from mail-m49198.qiye.163.com (mail-m49198.qiye.163.com [45.254.49.198]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 584E7310647; Mon, 18 Aug 2025 10:00:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.254.49.198 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755511231; cv=none; b=tIrW5g/CIUIaMvlwExzhK49Y3tuF/rSheChcQX4k8DAXzh5qxvidFaFmgIdqhix1gV22WebdWaeTUMhdi0XjaaaEXPAvj80fKodJ6FLCmeojEA8sq8kKcQ76F64GK6QEfEKjlJ9HxVU2soHVWXorYnlgIZE/SxT9zH8wP9D/Nq0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755511231; c=relaxed/simple; bh=wfWU/w6Ys2gcJWm2N/Ehy+GvHlMH+A+GYvYBMq6c2Z0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=FETXeNBlJC2ypAS5yydcNjiE6L/+HNt/UN773c+MKsKp8uY0cCCoxS+tAFMab62XSzGXPc4wTH74Pqr0fAE6Z7RmhUVdHCYMAeAGX+V84DYqdcTn61TGZtekycOt4HxB0fGv6DLG6z79ZBZ4DFYokMPTCDTEFo+mf8n6eQcSTgk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=jmu.edu.cn; spf=pass smtp.mailfrom=jmu.edu.cn; arc=none smtp.client-ip=45.254.49.198 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=jmu.edu.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=jmu.edu.cn Received: from localhost.localdomain (unknown [119.122.213.154]) by smtp.qiye.163.com (Hmail) with ESMTP id 1fbaa9d04; Mon, 18 Aug 2025 18:00:19 +0800 (GMT+08:00) From: Chukun Pan To: Heiko Stuebner Cc: Chukun Pan , Rob Herring , Conor Dooley , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 3/4] arm64: dts: rockchip: Add HINLINK H68K Date: Mon, 18 Aug 2025 18:00:08 +0800 Message-Id: <20250818100009.170202-4-amadeus@jmu.edu.cn> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250818100009.170202-1-amadeus@jmu.edu.cn> References: <20250818100009.170202-1-amadeus@jmu.edu.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-HM-Tid: 0a98bc9f65ab03a2kunm3d9619f636a256 X-HM-MType: 10 X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFITzdXWS1ZQUlXWQ8JGhUIEh9ZQVlDTRpIVkpJQkhDT0lLHhoZGVYeHw5VEwETFhoSFy QUDg9ZV1kYEgtZQVlKSkJVSklJVUlKSFVKTk9ZV1kWGg8SFR0UWUFZT0tIVUpLSU9PT0tVSktLVU tZBg++ Content-Type: text/plain; charset="utf-8" The HINLINK H68K is a development board with the Rockchip RK3568 SoC. It has the following features: - 2/4GB LPDDR4 - 1x HDMI Type A - 3.5mm jack with mic - 1x PCIE 2.0 WiFi slot - 1x USB 3.0, 2x USB 2.0 - 2x 1GbE RTL8211F Ethernet - 2x 2.5GbE RTL8125B Ethernet - MicroSD card slot / eMMC 32GB Signed-off-by: Chukun Pan Acked-by: Conor Dooley --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../boot/dts/rockchip/rk3568-hinlink-h68k.dts | 83 +++ .../boot/dts/rockchip/rk3568-hinlink-opc.dtsi | 666 ++++++++++++++++++ 3 files changed, 750 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-hinlink-h68k.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-hinlink-opc.dtsi diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/ro= ckchip/Makefile index 099520962ffb..09c810cb64a4 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -130,6 +130,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-bpi-r2-pro.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-evb1-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-fastrhino-r66s.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-fastrhino-r68s.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-hinlink-h68k.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-lubancat-2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-mecsbc.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-nanopi-r5c.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3568-hinlink-h68k.dts b/arch/ar= m64/boot/dts/rockchip/rk3568-hinlink-h68k.dts new file mode 100644 index 000000000000..793ee651b868 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-hinlink-h68k.dts @@ -0,0 +1,83 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include "rk3568-hinlink-opc.dtsi" + +/ { + model =3D "HINLINK H68K"; + compatible =3D "hinlink,h68k", "rockchip,rk3568"; + + aliases { + ethernet0 =3D &gmac0; + ethernet1 =3D &gmac1; + }; +}; + +&gmac0 { + assigned-clocks =3D <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; + assigned-clock-parents =3D <&cru SCLK_GMAC0_RGMII_SPEED>; + assigned-clock-rates =3D <0>, <125000000>; + clock_in_out =3D "output"; + phy-handle =3D <&rgmii_phy0>; + phy-mode =3D "rgmii-id"; + phy-supply =3D <&vcc3v3_sys>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus + &gmac0_rstn>; + status =3D "okay"; +}; + +&gmac1 { + assigned-clocks =3D <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; + assigned-clock-parents =3D <&cru SCLK_GMAC1_RGMII_SPEED>; + assigned-clock-rates =3D <0>, <125000000>; + clock_in_out =3D "output"; + phy-handle =3D <&rgmii_phy1>; + phy-mode =3D "rgmii-id"; + phy-supply =3D <&vcc3v3_sys>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&gmac1m1_miim + &gmac1m1_tx_bus2 + &gmac1m1_rx_bus2 + &gmac1m1_rgmii_clk + &gmac1m1_rgmii_bus + &gmac1_rstn>; + status =3D "okay"; +}; + +&mdio0 { + rgmii_phy0: ethernet-phy@1 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <0x1>; + reset-assert-us =3D <20000>; + reset-deassert-us =3D <100000>; + reset-gpios =3D <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>; + }; +}; + +&mdio1 { + rgmii_phy1: ethernet-phy@1 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <0x1>; + reset-assert-us =3D <20000>; + reset-deassert-us =3D <100000>; + reset-gpios =3D <&gpio1 RK_PB0 GPIO_ACTIVE_LOW>; + }; +}; + +&pinctrl { + gmac { + gmac0_rstn: gmac0-rstn { + rockchip,pins =3D <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + gmac1_rstn: gmac1-rstn { + rockchip,pins =3D <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-hinlink-opc.dtsi b/arch/ar= m64/boot/dts/rockchip/rk3568-hinlink-opc.dtsi new file mode 100644 index 000000000000..14f3839ca091 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-hinlink-opc.dtsi @@ -0,0 +1,666 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include +#include +#include +#include +#include +#include "rk3568.dtsi" + +/ { + aliases { + mmc0 =3D &sdhci; + mmc1 =3D &sdmmc0; + }; + + chosen { + stdout-path =3D "serial2:1500000n8"; + }; + + hdmi-con { + compatible =3D "hdmi-connector"; + type =3D "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint =3D <&hdmi_out_con>; + }; + }; + }; + + ir-receiver { + compatible =3D "gpio-ir-receiver"; + gpios =3D <&gpio0 RK_PC2 GPIO_ACTIVE_LOW>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pwm3_ir_m0>; + }; + + keys { + compatible =3D "gpio-keys"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&factory>; + + button-factory { + label =3D "factory"; + linux,code =3D ; + gpios =3D <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>; + debounce-interval =3D <50>; + }; + }; + + leds { + compatible =3D "gpio-leds"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&green_led>, <&red_led>, <&work_led>; + + led-0 { + color =3D ; + function =3D LED_FUNCTION_WAN; + gpios =3D <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>; + linux,default-trigger =3D "netdev"; + }; + + led-1 { + color =3D ; + function =3D LED_FUNCTION_DISK; + gpios =3D <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>; + }; + + led-2 { + color =3D ; + function =3D LED_FUNCTION_STATUS; + gpios =3D <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; + linux,default-trigger =3D "default-on"; + }; + }; + + vcc0v9_2g5: regulator-0v9-vcc-2g5 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc0v9_2g5"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <900000>; + vin-supply =3D <&vcc5v0_sys>; + }; + + vcc12v_dcinp: regulator-12v-vcc-dcinp { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc12v_dcinp"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <12000000>; + regulator-max-microvolt =3D <12000000>; + }; + + vcc3v3_pi6c_05: regulator-3v3-vcc-pi6c-05 { + compatible =3D "regulator-fixed"; + enable-active-high; + gpios =3D <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&lan_power_en>; + regulator-name =3D "vcc3v3_pi6c_05"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <&vcc5v0_sys>; + }; + + vcc3v3_sd: regulator-3v3-vcc-sd { + compatible =3D "regulator-fixed"; + enable-active-high; + gpios =3D <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&sd_pwren>; + regulator-name =3D "vcc3v3_sd"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <&vcc3v3_sys>; + }; + + vcc3v3_sys: regulator-3v3-vcc-sys { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <&vcc5v0_sys>; + }; + + vcc5v0_sys: regulator-5v0-vcc-sys { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <&vcc12v_dcinp>; + }; + + vcc5v0_usb30_otg0: regulator-5v0-vcc-usb30-otg0 { + compatible =3D "regulator-fixed"; + enable-active-high; + gpios =3D <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&usb_power_en>; + regulator-name =3D "vcc5v0_usb30_otg0"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <&vcc5v0_sys>; + }; +}; + +&combphy0 { + status =3D "okay"; +}; + +&combphy1 { + status =3D "okay"; +}; + +&combphy2 { + status =3D "okay"; +}; + +&cpu0 { + cpu-supply =3D <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply =3D <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply =3D <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply =3D <&vdd_cpu>; +}; + +&gpu { + mali-supply =3D <&vdd_gpu>; + status =3D "okay"; +}; + +&hdmi { + avdd-0v9-supply =3D <&vdda0v9_image>; + avdd-1v8-supply =3D <&vcca1v8_image>; + status =3D "okay"; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint =3D <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint =3D <&hdmi_con_in>; + }; +}; + +&hdmi_sound { + status =3D "okay"; +}; + +&i2c0 { + status =3D "okay"; + + vdd_cpu: regulator@1c { + compatible =3D "tcs,tcs4525"; + reg =3D <0x1c>; + fcs,suspend-voltage-selector =3D <1>; + regulator-name =3D "vdd_cpu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <800000>; + regulator-max-microvolt =3D <1150000>; + regulator-ramp-delay =3D <2300>; + vin-supply =3D <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk809: pmic@20 { + compatible =3D "rockchip,rk809"; + reg =3D <0x20>; + #clock-cells =3D <1>; + interrupt-parent =3D <&gpio0>; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pmic_int>; + system-power-controller; + wakeup-source; + + vcc1-supply =3D <&vcc3v3_sys>; + vcc2-supply =3D <&vcc3v3_sys>; + vcc3-supply =3D <&vcc3v3_sys>; + vcc4-supply =3D <&vcc3v3_sys>; + vcc5-supply =3D <&vcc3v3_sys>; + vcc6-supply =3D <&vcc3v3_sys>; + vcc7-supply =3D <&vcc3v3_sys>; + vcc8-supply =3D <&vcc3v3_sys>; + vcc9-supply =3D <&vcc3v3_sys>; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name =3D "vdd_logic"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode =3D <0x2>; + regulator-min-microvolt =3D <500000>; + regulator-max-microvolt =3D <1350000>; + regulator-ramp-delay =3D <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-name =3D "vdd_gpu"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode =3D <0x2>; + regulator-min-microvolt =3D <500000>; + regulator-max-microvolt =3D <1350000>; + regulator-ramp-delay =3D <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name =3D "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode =3D <0x2>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_npu: DCDC_REG4 { + regulator-name =3D "vdd_npu"; + regulator-initial-mode =3D <0x2>; + regulator-min-microvolt =3D <500000>; + regulator-max-microvolt =3D <1350000>; + regulator-ramp-delay =3D <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-name =3D "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_image: LDO_REG1 { + regulator-name =3D "vdda0v9_image"; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-name =3D "vdda_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-name =3D "vdda0v9_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <900000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-name =3D "vccio_acodec"; + regulator-always-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name =3D "vccio_sd"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-name =3D "vcc3v3_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-name =3D "vcca_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-name =3D "vcca1v8_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <1800000>; + }; + }; + + vcca1v8_image: LDO_REG9 { + regulator-name =3D "vcca1v8_image"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-name =3D "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3: SWITCH_REG2 { + regulator-name =3D "vcc3v3"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&i2c2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c2m1_xfer>; + status =3D "okay"; +}; + +&i2s0_8ch { + status =3D "okay"; +}; + +&pcie2x1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&wifi_perstn>; + reset-gpios =3D <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply =3D <&vcc3v3_pi6c_05>; + status =3D "okay"; +}; + +&pcie30phy { + data-lanes =3D <1 2>; + status =3D "okay"; +}; + +&pcie3x1 { + num-lanes =3D <1>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&lan_resetb>; + reset-gpios =3D <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply =3D <&vcc3v3_pi6c_05>; + status =3D "okay"; +}; + +&pcie3x2 { + num-lanes =3D <1>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&lan_reseta>; + reset-gpios =3D <&gpio2 RK_PD0 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply =3D <&vcc3v3_pi6c_05>; + status =3D "okay"; +}; + +&pinctrl { + keys { + factory: factory { + rockchip,pins =3D <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + leds { + green_led: green-led { + rockchip,pins =3D <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + red_led: red-led { + rockchip,pins =3D <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + work_led: work-led { + rockchip,pins =3D <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + ir { + pwm3_ir_m0: pwm3-ir-m0 { + rockchip,pins =3D <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + mmc { + sd_pwren: sd-pwren { + rockchip,pins =3D <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie { + lan_power_en: lan-power-en { + rockchip,pins =3D <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + lan_reseta: lan-reseta { + rockchip,pins =3D <2 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + lan_resetb: lan-resetb { + rockchip,pins =3D <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wifi_perstn: wifi-perstn { + rockchip,pins =3D <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int: pmic-int { + rockchip,pins =3D <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + usb_power_en: usb-power-en { + rockchip,pins =3D <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + pmuio1-supply =3D <&vcc3v3_pmu>; + pmuio2-supply =3D <&vcc3v3_pmu>; + vccio1-supply =3D <&vccio_acodec>; + vccio2-supply =3D <&vcc_1v8>; + vccio3-supply =3D <&vccio_sd>; + vccio4-supply =3D <&vcc_1v8>; + vccio5-supply =3D <&vcc_3v3>; + vccio6-supply =3D <&vcc_1v8>; + vccio7-supply =3D <&vcc_3v3>; + status =3D "okay"; +}; + +&pwm0 { + status =3D "okay"; +}; + +&saradc { + vref-supply =3D <&vcca_1v8>; + status =3D "okay"; +}; + +/* Via Type-C adapter */ +&sata0 { + status =3D "okay"; +}; + +&sdhci { + bus-width =3D <8>; + cap-mmc-highspeed; + max-frequency =3D <200000000>; + mmc-hs200-1_8v; + non-removable; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; + vmmc-supply =3D <&vcc_3v3>; + vqmmc-supply =3D <&vcc_1v8>; + status =3D "okay"; +}; + +&sdmmc0 { + bus-width =3D <4>; + cap-sd-highspeed; + cd-gpios =3D <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; + disable-wp; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + sd-uhs-sdr50; + vmmc-supply =3D <&vcc3v3_sd>; + vqmmc-supply =3D <&vccio_sd>; + status =3D "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode =3D <1>; + rockchip,hw-tshut-polarity =3D <0>; + status =3D "okay"; +}; + +&uart2 { + status =3D "okay"; +}; + +&usb_host0_ehci { + status =3D "okay"; +}; + +&usb_host0_ohci { + status =3D "okay"; +}; + +&usb_host1_ehci { + status =3D "okay"; +}; + +&usb_host1_ohci { + status =3D "okay"; +}; + +&usb_host1_xhci { + status =3D "okay"; +}; + +&usb2phy0 { + status =3D "okay"; +}; + +&usb2phy0_host { + phy-supply =3D <&vcc5v0_usb30_otg0>; + status =3D "okay"; +}; + +&usb2phy1 { + status =3D "okay"; +}; + +&usb2phy1_host { + phy-supply =3D <&vcc5v0_usb30_otg0>; + status =3D "okay"; +}; + +&usb2phy1_otg { + phy-supply =3D <&vcc5v0_usb30_otg0>; + status =3D "okay"; +}; + +&vop { + assigned-clocks =3D <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents =3D <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; + status =3D "okay"; +}; + +&vop_mmu { + status =3D "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg =3D ; + remote-endpoint =3D <&hdmi_in_vp0>; + }; +}; --=20 2.25.1 From nobody Sat Oct 4 09:42:05 2025 Received: from mail-m155101.qiye.163.com (mail-m155101.qiye.163.com [101.71.155.101]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 01E25317709; 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charset="utf-8" The HINLINK H66K is a development board with the Rockchip RK3568 SoC. It has the following features: - 2/4GB LPDDR4 - 1x HDMI Type A - 3.5mm jack with mic - 1x PCIE 2.0 WiFi slot - 1x USB 3.0, 2x USB 2.0 - 2x 2.5GbE RTL8125B Ethernet - MicroSD card slot / eMMC 32GB Signed-off-by: Chukun Pan Acked-by: Conor Dooley --- arch/arm64/boot/dts/rockchip/Makefile | 1 + arch/arm64/boot/dts/rockchip/rk3568-hinlink-h66k.dts | 10 ++++++++++ 2 files changed, 11 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-hinlink-h66k.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/ro= ckchip/Makefile index 09c810cb64a4..93e547a1c77b 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -130,6 +130,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-bpi-r2-pro.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-evb1-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-fastrhino-r66s.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-fastrhino-r68s.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-hinlink-h66k.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-hinlink-h68k.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-lubancat-2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-mecsbc.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3568-hinlink-h66k.dts b/arch/ar= m64/boot/dts/rockchip/rk3568-hinlink-h66k.dts new file mode 100644 index 000000000000..bc51123d53f5 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-hinlink-h66k.dts @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include "rk3568-hinlink-opc.dtsi" + +/ { + model =3D "HINLINK H66K"; + compatible =3D "hinlink,h66k", "rockchip,rk3568"; +}; --=20 2.25.1