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Mon, 18 Aug 2025 02:24:38 -0700 From: Kartik Rajput To: , , , , , , , , , , , , CC: Subject: [PATCH v4 3/5] i2c: tegra: Add HS mode support Date: Mon, 18 Aug 2025 14:54:09 +0530 Message-ID: <20250818092412.444755-4-kkartik@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250818092412.444755-1-kkartik@nvidia.com> References: <20250818092412.444755-1-kkartik@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000042AB:EE_|MN2PR12MB4269:EE_ X-MS-Office365-Filtering-Correlation-Id: e950d81f-e8a6-4ff9-1ad2-08ddde391a6f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|36860700013|376014|7416014|921020; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?h6YeSCFFMLlOWjP+Ig9LCv/oqMH7WkpBphPDsCck8Fq4lXUbddWVMl/eSpvb?= =?us-ascii?Q?Zq2TCfUw5GDmVyJIKqs1hSV9yG9GY6/FLlbV9qbCB1fG6zUatCAXHXkPY3vU?= =?us-ascii?Q?+tewVYceZt2cz+ugWJG10g7tZdtbRfCHyNQdgqhCJ5eGp1cOcaWvuJZCYKUB?= =?us-ascii?Q?PTe/6TBzIflwek8g8WfxNnj4CPd0dZQsXT10Mu4/iqsGWulvDQ6o0VvUpwrK?= =?us-ascii?Q?VbUFGC24WwL/LjlDnR3dg8QoDSes4BdaqPbMA1gjl2oVUZxuPppkH6njuyX1?= =?us-ascii?Q?hAh21YI/v6SQ+jN+cDB/EvnVhtXb8YQfyz4E6sBq0UZVwDVMeUPG3mL3V92v?= =?us-ascii?Q?IfMStCraV5NKdjdPhB5hmFdGAI1c7MfiZxxwdajH6cz73hElWtoRJ3n/xYI3?= =?us-ascii?Q?DGvrzOqW5xniFoWZ4wpvhD1TKwWjOqzEWbjBIxyUq8BnaL7uk6WMMVBQyizf?= =?us-ascii?Q?miMuI+kwr93AQFfujVQ3ZqIzO3qce0CkXvM1joclJwCddHaxgDom2OxKfHS5?= =?us-ascii?Q?83kbSakVQsVc+aVZa/s5gfs3RXFvcoSUHwg7+c0IAsEI7ytzKyHJD6kpGVDw?= =?us-ascii?Q?pD1GJ1IZ8khO4pur6pTYmzBeyyOd8HoEjsgUsfXKWw5OYHmV5bz46+jqaieD?= =?us-ascii?Q?sOpjKifq9qRQnUA2FDz6yoYm423o2OqlEmvUOneOtPPfx1HAeqpCYj3PhKvs?= =?us-ascii?Q?qFXNUHs6RMr0R0HMZHv9SwMygyujRzFdk+BZMppmAu60CUQekSsu1ejBq98b?= =?us-ascii?Q?apVhXdZIjhkgdeIO7lKj8oGsnM08j+l8Cw8qsonC/tNBQnYoQOKl+TPy+l4M?= =?us-ascii?Q?OMOIiULh/MAmtR1v2jkSi87FpgNuXwJfU1TZMVwPIA8lWsFAr2lVi7gzdT4i?= =?us-ascii?Q?1OFyD+Ll5XLmhWobtQDNLyuMwvLoAC5EaBEr3rWDiSIHBZQX6D8a+4xC5pa6?= =?us-ascii?Q?oLoXHZBWpWeRN6rl1yggn3qUZ5fI+MKT7IZ7wczlPwoauJIIO5mYdoDi6xVh?= =?us-ascii?Q?PL1muiGm9DPE3pUzY2TWPha14xJUmKO6CsKLezw62MogMvR1LehPCMMZmRxm?= =?us-ascii?Q?9Uv50qGsXK+Pt6AX5YzlKGBXHUbvppcCJFxCHw2i3T5LrGXIb1TSow4E2Bdv?= =?us-ascii?Q?JnPDwYCqY0uRAnCKL0b+J6tvxMJGxSu8YkOYvBou4EZ6NUlHp9ULVnc2YuFI?= =?us-ascii?Q?AnUzRmF4NbxFymz/LPfkyNBJjnuxg/VP2szOG1yhaiu4QM+a24wjJH6j5G3d?= =?us-ascii?Q?AESFvTmtzLQ+60FsW+FcPCmPouFpb7PLirGWVPt/vbMED7Lt/vjPyc0FBZo+?= =?us-ascii?Q?QEABJO05rWhrFwlIRU4C50+cUnF0TkRuOiFR7b6Iv+5JAs84Y9qk3rBpVX7O?= =?us-ascii?Q?SGbDzgNhS0lGCsVybL+hT1LCH0qIQyrLK7BjE7Z0viXhLT757KjaQN3g2Aav?= =?us-ascii?Q?CLk7QGZYealZxCRQLHDHIVTTN4UW42Y0ieO3syRrI5UqfHzLCEwmBdQ/z6t5?= =?us-ascii?Q?a/LOSiXkB0RyOLSgE7PiB6D8KQ6xSLkNGatXnnDY5VDJs3U55b6BV/GTTw?= =?us-ascii?Q?=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(36860700013)(376014)(7416014)(921020);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Aug 2025 09:24:59.3404 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e950d81f-e8a6-4ff9-1ad2-08ddde391a6f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000042AB.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4269 Content-Type: text/plain; charset="utf-8" From: Akhil R Add support for HS (High Speed) mode transfers, which is supported by Tegra194 onwards. Signed-off-by: Akhil R Signed-off-by: Kartik Rajput --- v2 -> v3: * Document tlow_hs_mode and thigh_hs_mode. v1 -> v2: * Document has_hs_mode_support. * Add a check to set the frequency to fastmode+ if the device does not support HS mode but the requested frequency is more than fastmode+. --- drivers/i2c/busses/i2c-tegra.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c index 0c428cba4df3..6e322dba42b1 100644 --- a/drivers/i2c/busses/i2c-tegra.c +++ b/drivers/i2c/busses/i2c-tegra.c @@ -91,6 +91,7 @@ #define I2C_HEADER_IE_ENABLE BIT(17) #define I2C_HEADER_REPEAT_START BIT(16) #define I2C_HEADER_CONTINUE_XFER BIT(15) +#define I2C_HEADER_HS_MODE BIT(22) #define I2C_HEADER_SLAVE_ADDR_SHIFT 1 =20 #define I2C_BUS_CLEAR_CNFG 0x084 @@ -198,6 +199,8 @@ enum msg_end_type { * @thigh_std_mode: High period of the clock in standard mode. * @tlow_fast_fastplus_mode: Low period of the clock in fast/fast-plus mod= es. * @thigh_fast_fastplus_mode: High period of the clock in fast/fast-plus m= odes. + * @tlow_hs_mode: Low period of the clock in HS mode. + * @thigh_hs_mode: High period of the clock in HS mode. * @setup_hold_time_std_mode: Setup and hold time for start and stop condi= tions * in standard mode. * @setup_hold_time_fast_fast_plus_mode: Setup and hold time for start and= stop @@ -206,6 +209,7 @@ enum msg_end_type { * in HS mode. * @has_interface_timing_reg: Has interface timing register to program the= tuned * timing settings. + * @has_hs_mode_support: Has support for high speed (HS) mode transfers. */ struct tegra_i2c_hw_feature { bool has_continue_xfer_support; @@ -226,10 +230,13 @@ struct tegra_i2c_hw_feature { u32 thigh_std_mode; u32 tlow_fast_fastplus_mode; u32 thigh_fast_fastplus_mode; + u32 tlow_hs_mode; + u32 thigh_hs_mode; u32 setup_hold_time_std_mode; u32 setup_hold_time_fast_fast_plus_mode; u32 setup_hold_time_hs_mode; bool has_interface_timing_reg; + bool has_hs_mode_support; }; =20 /** @@ -717,6 +724,20 @@ static int tegra_i2c_init(struct tegra_i2c_dev *i2c_de= v) if (i2c_dev->hw->has_interface_timing_reg && tsu_thd) i2c_writel(i2c_dev, tsu_thd, I2C_INTERFACE_TIMING_1); =20 + /* Write HS mode registers. These will get used only for HS mode*/ + if (i2c_dev->hw->has_hs_mode_support) { + tlow =3D i2c_dev->hw->tlow_hs_mode; + thigh =3D i2c_dev->hw->thigh_hs_mode; + tsu_thd =3D i2c_dev->hw->setup_hold_time_hs_mode; + + val =3D FIELD_PREP(I2C_HS_INTERFACE_TIMING_THIGH, thigh) | + FIELD_PREP(I2C_HS_INTERFACE_TIMING_TLOW, tlow); + i2c_writel(i2c_dev, val, I2C_HS_INTERFACE_TIMING_0); + i2c_writel(i2c_dev, tsu_thd, I2C_HS_INTERFACE_TIMING_1); + } else if (t->bus_freq_hz > I2C_MAX_FAST_MODE_PLUS_FREQ) { + t->bus_freq_hz =3D I2C_MAX_FAST_MODE_PLUS_FREQ; + } + clk_multiplier =3D (tlow + thigh + 2) * (non_hs_mode + 1); =20 err =3D clk_set_rate(i2c_dev->div_clk, @@ -1214,6 +1235,9 @@ static void tegra_i2c_push_packet_header(struct tegra= _i2c_dev *i2c_dev, if (msg->flags & I2C_M_RD) packet_header |=3D I2C_HEADER_READ; =20 + if (i2c_dev->timings.bus_freq_hz > I2C_MAX_FAST_MODE_PLUS_FREQ) + packet_header |=3D I2C_HEADER_HS_MODE; + if (i2c_dev->dma_mode && !i2c_dev->msg_read) *dma_buf++ =3D packet_header; else @@ -1648,10 +1672,13 @@ static const struct tegra_i2c_hw_feature tegra194_i= 2c_hw =3D { .thigh_std_mode =3D 0x7, .tlow_fast_fastplus_mode =3D 0x2, .thigh_fast_fastplus_mode =3D 0x2, + .tlow_hs_mode =3D 0x8, + .thigh_hs_mode =3D 0x3, .setup_hold_time_std_mode =3D 0x08080808, .setup_hold_time_fast_fast_plus_mode =3D 0x02020202, .setup_hold_time_hs_mode =3D 0x090909, .has_interface_timing_reg =3D true, + .has_hs_mode_support =3D true, }; =20 static const struct of_device_id tegra_i2c_of_match[] =3D { --=20 2.43.0