From nobody Sat Oct 4 09:40:53 2025 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 448FB25D549 for ; Mon, 18 Aug 2025 08:42:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.61.82.184 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755506581; cv=none; b=oO1ItKg2TXzugSILuIOtEpk9MU/pRND64Mb7C6FN7+lx+aF2WYNzklfqYGK2H4s0NbAClsuT2sdDJrH6YwAcAEm3pdlq0a8PUOhug9nHAUceV850wTT5UnkiSPhSfTvf8cENj5l8HiJx34Yj6TVPak4VMiv0zT3fhQVtxHrBxic= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755506581; c=relaxed/simple; bh=+uOz4NcMUj4DgMcB5calNycuKxf3I7WIu/7rLtSibn8=; h=From:To:CC:Subject:Date:Message-ID:MIME-Version:Content-Type; b=U2+NnDz/5cjTSwzvf06H8wNV4HnYOpHsuOwfpKL8zCTFwDQLYbMr/QQx5BEh5qXDr4B6xtk2IXlcNVuZZXtnmIq0oh6Levm1KHhV8txnzEyzDqtUKJkHS+Bl8sZiXSppoOrwksAnV+5HA/ZsqR01uynSuR15AYxNbXsVpxGPTpA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=GibQaDwu; arc=none smtp.client-ip=210.61.82.184 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="GibQaDwu" X-UUID: 525d23967c0f11f0b33aeb1e7f16c2b6-20250818 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:Message-ID:Date:Subject:CC:To:From; bh=zTc9ILZszspIergQBlX6+NhSE6Fs5a72JurzfDZwPEA=; b=GibQaDwujkcuFxcFtqCRQUOl63b5NIQ5C+sDQAXh8wK/KwkX3tZBtcy8/1QF9Z2XCvWBQgDqVdeFSr0J4dp0X3/MbHuLc3l4ltUslZbcp70MMfV6Xc7O94bQdD0Ear/dEHt5w0M7aNWNMeQjdV4w6n/yqRfslqKEehq41PLO2pc=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.3.3,REQID:74a47241-05da-433e-8bfd-c57d67ade219,IP:0,UR L:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION:r elease,TS:0 X-CID-META: VersionHash:f1326cf,CLOUDID:505f556d-c2f4-47a6-876f-59a53e9ecc6e,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:-5,Content:0|15|50,EDM:-3,IP: nil,URL:0,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,L ES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 2,SSN|SDN X-CID-BAS: 2,SSN|SDN,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-CID-RHF: D41D8CD98F00B204E9800998ECF8427E X-UUID: 525d23967c0f11f0b33aeb1e7f16c2b6-20250818 Received: from mtkmbs14n2.mediatek.inc [(172.21.101.76)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 521347145; Mon, 18 Aug 2025 16:42:49 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by MTKMBS14N1.mediatek.inc (172.21.101.75) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.39; Mon, 18 Aug 2025 16:42:48 +0800 Received: from mtksitap99.mediatek.inc (10.233.130.16) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.39 via Frontend Transport; Mon, 18 Aug 2025 16:42:48 +0800 From: payne.lin To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Simona Vetter , Matthias Brugger , AngeloGioacchino Del Regno CC: , , , , , , , , Bincai Liu , Payne Lin Subject: [PATCH] gpu: drm: mediatek: correct clk setting AUX_RX_UI_CNT_THR_AUX_FOR_26M Date: Mon, 18 Aug 2025 16:42:36 +0800 Message-ID: <20250818084242.1045095-1-payne.lin@mediatek.com> X-Mailer: git-send-email 2.45.2 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Content-Type: text/plain; charset="utf-8" From: Bincai Liu Updated the definition of AUX_RX_UI_CNT_THR_AUX_FOR_26M from 13 to 14. No other code or logic changes were made; only the macro value was modified. This change affects the timing configuration for AUX RX at 26MHz. The formula is xtal_clk / 2 + 1. Signed-off-by: Bincai Liu Signed-off-by: Payne Lin --- drivers/gpu/drm/mediatek/mtk_dp_reg.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dp_reg.h b/drivers/gpu/drm/mediat= ek/mtk_dp_reg.h index 8ad7a9cc259e..f8c7b3c0935f 100644 --- a/drivers/gpu/drm/mediatek/mtk_dp_reg.h +++ b/drivers/gpu/drm/mediatek/mtk_dp_reg.h @@ -301,7 +301,7 @@ #define AUX_TIMEOUT_THR_AUX_TX_P0_VAL 0x1595 #define MTK_DP_AUX_P0_3614 0x3614 #define AUX_RX_UI_CNT_THR_AUX_TX_P0_MASK GENMASK(6, 0) -#define AUX_RX_UI_CNT_THR_AUX_FOR_26M 13 +#define AUX_RX_UI_CNT_THR_AUX_FOR_26M 14 #define MTK_DP_AUX_P0_3618 0x3618 #define AUX_RX_FIFO_FULL_AUX_TX_P0_MASK BIT(9) #define AUX_RX_FIFO_WRITE_POINTER_AUX_TX_P0_MASK GENMASK(3, 0) --=20 2.45.2