From nobody Sat Oct 4 09:40:55 2025 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F28BA2FF665 for ; Mon, 18 Aug 2025 08:40:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.244.123.138 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755506441; cv=none; b=HVy7p+dZ9lMd9TP4Uij5rNea/zE9nMeqGGwuTMx+/QtBkNR34UPx7uyOoKfcMRX0IATZ4JKxSdU4oxMtQ7+qcl6+vE8LMLajErCc7QwcIT8ILq9ErFWLHc0RSC+cERG4b920SobtK3vdOpBogUg2cSTPgi/5yBoXxXi9BeJrI6s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755506441; c=relaxed/simple; bh=+uOz4NcMUj4DgMcB5calNycuKxf3I7WIu/7rLtSibn8=; h=From:To:CC:Subject:Date:Message-ID:MIME-Version:Content-Type; b=B1k6zzu1mab2Cc1TYYxNwUWi0DsH1RTT2f8z5HegposwxNfwvcIgt2VAFIgZFYABRBv5diOtAgKd024JUfyzXURDKHf7vYXtlq3w8ZOubeawjQ6KZ9Zcbe0L1WdwRvU53IhmaKu0Px7DJpzTqWUlf+sQz/dAr84O37/d4ldWAMs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=m6alafy7; arc=none smtp.client-ip=60.244.123.138 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="m6alafy7" X-UUID: 00bbb25a7c0f11f08729452bf625a8b4-20250818 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:Message-ID:Date:Subject:CC:To:From; bh=zTc9ILZszspIergQBlX6+NhSE6Fs5a72JurzfDZwPEA=; b=m6alafy7KwEt+jurtbsy7hDyb/+QEIfB7gYhJzobDe1UYJ0JtwAaqbjrY8E53yz09COZVIG9vOC/VWD2KgVbR9AEk/LMly+HbYl+Zhqs4oydBXUtmnB9VQtO4L0EZCvVXp1Pbv/we2Rhd5x2djYC9g+HHv29KXGBpux01xOAW2U=; X-CID-CACHE: Type:Local,Time:202508181634+08,HitQuantity:2 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.3.3,REQID:9f07d84b-73c4-47e0-95b9-c696bdaa5d14,IP:0,UR L:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION:r elease,TS:0 X-CID-META: VersionHash:f1326cf,CLOUDID:900b0bf4-66cd-4ff9-9728-6a6f64661009,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:-5,Content:0|15|50,EDM:-3,IP: nil,URL:0,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,L ES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 2,SSN|SDN X-CID-BAS: 2,SSN|SDN,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-CID-RHF: D41D8CD98F00B204E9800998ECF8427E X-UUID: 00bbb25a7c0f11f08729452bf625a8b4-20250818 Received: from mtkmbs13n2.mediatek.inc [(172.21.101.108)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 574988635; Mon, 18 Aug 2025 16:40:32 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.39; Mon, 18 Aug 2025 16:40:31 +0800 Received: from mtksitap99.mediatek.inc (10.233.130.16) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.39 via Frontend Transport; Mon, 18 Aug 2025 16:40:31 +0800 From: payne.lin To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Simona Vetter , Matthias Brugger , AngeloGioacchino Del Regno CC: , , , , Bincai Liu , Payne Lin Subject: [PATCH] gpu: drm: mediatek: correct clk setting AUX_RX_UI_CNT_THR_AUX_FOR_26M Date: Mon, 18 Aug 2025 16:40:23 +0800 Message-ID: <20250818084028.1043856-1-payne.lin@mediatek.com> X-Mailer: git-send-email 2.45.2 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Content-Type: text/plain; charset="utf-8" From: Bincai Liu Updated the definition of AUX_RX_UI_CNT_THR_AUX_FOR_26M from 13 to 14. No other code or logic changes were made; only the macro value was modified. This change affects the timing configuration for AUX RX at 26MHz. The formula is xtal_clk / 2 + 1. Signed-off-by: Bincai Liu Signed-off-by: Payne Lin --- drivers/gpu/drm/mediatek/mtk_dp_reg.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dp_reg.h b/drivers/gpu/drm/mediat= ek/mtk_dp_reg.h index 8ad7a9cc259e..f8c7b3c0935f 100644 --- a/drivers/gpu/drm/mediatek/mtk_dp_reg.h +++ b/drivers/gpu/drm/mediatek/mtk_dp_reg.h @@ -301,7 +301,7 @@ #define AUX_TIMEOUT_THR_AUX_TX_P0_VAL 0x1595 #define MTK_DP_AUX_P0_3614 0x3614 #define AUX_RX_UI_CNT_THR_AUX_TX_P0_MASK GENMASK(6, 0) -#define AUX_RX_UI_CNT_THR_AUX_FOR_26M 13 +#define AUX_RX_UI_CNT_THR_AUX_FOR_26M 14 #define MTK_DP_AUX_P0_3618 0x3618 #define AUX_RX_FIFO_FULL_AUX_TX_P0_MASK BIT(9) #define AUX_RX_FIFO_WRITE_POINTER_AUX_TX_P0_MASK GENMASK(3, 0) --=20 2.45.2