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Shenoy" , Babu Moger , Suravee Suthikulpanit , K Prateek Nayak Subject: [PATCH v3 2/4] x86/cpu/topology: Use initial APICID from XTOPOEXT on AMD/HYGON Date: Mon, 18 Aug 2025 06:04:33 +0000 Message-ID: <20250818060435.2452-3-kprateek.nayak@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250818060435.2452-1-kprateek.nayak@amd.com> References: <20250818060435.2452-1-kprateek.nayak@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002529D:EE_|DM6PR12MB4250:EE_ X-MS-Office365-Filtering-Correlation-Id: 09f16e7e-17ce-4a8e-947d-08ddde1d47ee X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|36860700013|7416014|376014|13003099007; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?AdJ4XXq5lX2zMir3ZtNjNwU8FqPBA1anFAkrzD4swS/yR8PAfw8lBRfkVZFw?= =?us-ascii?Q?YL+LJ4nRIhuEs7wVwy4/L4KHlj95Bia+/WcM2YJQOylamYC2fzDh+tjzd5rN?= =?us-ascii?Q?6dFxHjlA6hrUGJNIoTPzJyXqiuByo15Pnz3xasLrHPeOP2nMKPGs2+X10gsr?= =?us-ascii?Q?7JECRUFm0HpgKYiMo3d7EPqT3PwahfxRwuBgj8kPd71GLGYNqnvLqqZhVcwH?= =?us-ascii?Q?lt8sPaetd3Mg7js6FEDR+yYqPQfbPmCy1tONIR1VomqgnXwP+HveGMN156km?= =?us-ascii?Q?vGls7yKL/SCExM0q4ne3MreNFgQ8mCpiRAHpnY2FLcCOhzYXZmXS9K/oZdIl?= =?us-ascii?Q?8pOvhfy0dRF0Yft4MXXtBlam5xCrrRKIhvP5FBJrcXUiwNYAE5ajS/1Cld83?= =?us-ascii?Q?oow0njXuLkYYxI9mw0VUaifnxilhfmzFflQhhnE2/6EPC47XhAyAeVXWeoWA?= =?us-ascii?Q?ZgWXcvUy5nL5BUkN+WC6YUBTQUa1ea+IeYfgEHGzCM7MP+Fy3EyYniw/Ia/h?= =?us-ascii?Q?tsijttVJ47i51INtvl7dpysyhiz085v+wkvW/wAzZKvVCPw0r0jDYqKW2Imf?= =?us-ascii?Q?vWKFJcI5YozSyjLk8rGGRPCIfCvQUIQ3vv15jMQQxAn9Ta8vvFKnWWGwmOZb?= =?us-ascii?Q?q6xnBjz1Wqj405p2FQARK/8RZcK4jJhboe4kGhLP2BxAhBbBvoZmiL9nak7p?= =?us-ascii?Q?dbGT/2rsoQzaavtz2Kpo5L9V44dYJMMmTYzOsm51tfeXGHxqDe640p0pVLut?= =?us-ascii?Q?x8INtssVPZmbAiYLwfB9WM1HmmtcW/a6yOrQPcmhek6piAzV+Z3X08Mxe9t2?= =?us-ascii?Q?cgLxQtafBH1Tq3NH3PntDvOTXJhM26IWFXYt7QAwHnaJ8PnDkx3ksQF7WKWp?= =?us-ascii?Q?gYReVtBGnAz9SCQFB7UtBoKgBrYxrKlYBMysb8+WI04Vki/GPPIRDRofCZJV?= =?us-ascii?Q?ORW8ZTPjKJSN9L58RLepDrwn5rv47KKTfnQf67OMzHaTM8iRSorNs/owMRLa?= =?us-ascii?Q?Y1a21Mj0xkxfXccZ3dX5ONuRbbxE3F/W91bZ+DdmrHn4s5+0HiaUSCWzsB9D?= =?us-ascii?Q?WNYXL4oKzo1o0/QKCPVFmQlLAdgICk7cGRZcWjdPxOfhdY+f3/D3bU+ToFwG?= =?us-ascii?Q?Co7P1ah+pU/vwi25eyj1zUKF0XlQJMdfHncCDV10DvVmOir51redb/b7LJs9?= =?us-ascii?Q?2LXpBEYKaGqWtw/j2D4jvxer6II+//Yip62adySbRMds+YONwkoUYbaIHU98?= =?us-ascii?Q?gFnGJAUiGHVZO4HlHagGsB82viMXwph7ewG6KKSc57OEEJ4hgVn/pY04rM6Y?= =?us-ascii?Q?ihsQt+W2gZ2lGiNG0+HJzNFzNIqYn7x7J9iF/xn0qgV/YUfGtH/mcELACXnM?= =?us-ascii?Q?SLi/8sKtFlnc3NJ1G4hGZeW/Y9485CXkGSHqaU6N9pfETuIF7iECNKBwFhDn?= =?us-ascii?Q?4A2UbzOVVvfIjkRqWE0S3+8gkyVu6FiGF0noFqZXAod9FU27MMRuWw=3D=3D?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(36860700013)(7416014)(376014)(13003099007);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Aug 2025 06:05:49.8058 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 09f16e7e-17ce-4a8e-947d-08ddde1d47ee X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002529D.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4250 Content-Type: text/plain; charset="utf-8" Prior to the topology parsing rewrite and the switchover to the new parsing logic for AMD processors in commit c749ce393b8f ("x86/cpu: Use common topology code for AMD"), the "initial_apicid" on these platforms was: - First initialized to the LocalApicId from CPUID leaf 0x1 EBX[31:24]. - Then overwritten by the ExtendedLocalApicId in CPUID leaf 0xb EDX[31:0] on processors that supported topoext. With the new parsing flow introduced in commit f7fb3b2dd92c ("x86/cpu: Provide an AMD/HYGON specific topology parser"), parse_8000_001e() now unconditionally overwrites the "initial_apicid" already parsed during cpu_parse_topology_ext(). Although this has not been a problem on baremetal platforms, on virtualized AMD guests that feature more than 255 cores, QEMU 0's out the CPUID leaf 0x8000001e on CPUs with "CoreID" > 255 to prevent collision of these IDs in EBX[7:0] which can only represent a maximum of 255 cores [1]. This results in the following FW_BUG being logged when booting a guest with more than 255 cores: [Firmware Bug]: CPU 512: APIC ID mismatch. CPUID: 0x0000 APIC: 0x0200 Rely on the APICID parsed during cpu_parse_topology_ext() from CPUID leaf 0x80000026 or 0xb and only use the APICID from leaf 0x8000001e if cpu_parse_topology_ext() failed (has_topoext is false). On platforms that support the 0xb leaf (Zen2 or later, AMD guests on QEMU) or the extended leaf 0x80000026 (Zen4 or later), the "initial_apicid" is now set to the value parsed from EDX[31:0]. On older AMD/Hygon platforms that does not support the 0xb leaf but supports the TOPOEXT extension (Fam 0x15, 0x16, 0x17[Zen1], and Hygon), the current behavior is retained where "initial_apicid" is set using the 0x8000001e leaf. Link: https://github.com/qemu/qemu/commit/35ac5dfbcaa4b [1] Debugged-by: Naveen N Rao (AMD) Debugged-by: Sairaj Kodilkar Fixes: c749ce393b8f ("x86/cpu: Use common topology code for AMD") Tested-by: Naveen N Rao (AMD) Signed-off-by: K Prateek Nayak --- Changelog v2..v3: o No changes. --- arch/x86/kernel/cpu/topology_amd.c | 30 +++++++++++++++++++----------- 1 file changed, 19 insertions(+), 11 deletions(-) diff --git a/arch/x86/kernel/cpu/topology_amd.c b/arch/x86/kernel/cpu/topol= ogy_amd.c index bb00dc6433eb..ac0ba8495eec 100644 --- a/arch/x86/kernel/cpu/topology_amd.c +++ b/arch/x86/kernel/cpu/topology_amd.c @@ -81,20 +81,28 @@ static bool parse_8000_001e(struct topo_scan *tscan, bo= ol has_topoext) =20 cpuid_leaf(0x8000001e, &leaf); =20 - tscan->c->topo.initial_apicid =3D leaf.ext_apic_id; - - /* - * If leaf 0xb is available, then the domain shifts are set - * already and nothing to do here. Only valid for family >=3D 0x17. - */ - if (!has_topoext && tscan->c->x86 >=3D 0x17) { + if (!has_topoext) { /* - * Leaf 0x80000008 set the CORE domain shift already. - * Update the SMT domain, but do not propagate it. + * Prefer initial_apicid parsed from XTOPOLOGY leaf + * 0x8000026 or 0xb if available. Otherwise prefer the + * one from leaf 0x8000001e over 0x1. */ - unsigned int nthreads =3D leaf.core_nthreads + 1; + tscan->c->topo.initial_apicid =3D leaf.ext_apic_id; =20 - topology_update_dom(tscan, TOPO_SMT_DOMAIN, get_count_order(nthreads), n= threads); + /* + * If XTOPOLOGY leaf is available, then the domain shifts are set + * already and nothing to do here. Only valid for family >=3D 0x17. + */ + if (tscan->c->x86 >=3D 0x17) { + /* + * Leaf 0x80000008 set the CORE domain shift already. + * Update the SMT domain, but do not propagate it. + */ + unsigned int nthreads =3D leaf.core_nthreads + 1; + + topology_update_dom(tscan, TOPO_SMT_DOMAIN, + get_count_order(nthreads), nthreads); + } } =20 store_node(tscan, leaf.nnodes_per_socket + 1, leaf.node_id); --=20 2.34.1