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Mon, 18 Aug 2025 02:24:33 +0000 (GMT) From: Sangwook Shin To: krzk@kernel.org, alim.akhtar@samsung.com, wim@linux-watchdog.org, linux@roeck-us.net, semen.protsenko@linaro.org, dongil01.park@samsung.com, khwan.seo@samsung.com Cc: linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-watchdog@vger.kernel.org, linux-kernel@vger.kernel.org, Sangwook Shin Subject: [PATCH v6 3/5] watchdog: s3c2410_wdt: Increase max timeout value of watchdog Date: Mon, 18 Aug 2025 11:18:24 +0900 Message-Id: <20250818021826.623830-4-sw617.shin@samsung.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250818021826.623830-1-sw617.shin@samsung.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CMS-MailID: 20250818022433epcas2p1bf8e6a335be945822721b8db1e9571e9 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-Sendblock-Type: AUTO_CONFIDENTIAL CMS-TYPE: 102P cpgsPolicy: CPGSC10-234,N X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250818022433epcas2p1bf8e6a335be945822721b8db1e9571e9 References: <20250818021826.623830-1-sw617.shin@samsung.com> Increase max_timeout value from 55s to 3665038s (1018h 3min 58s) with 38400000 frequency system if the system has 32-bit WTCNT register. cat /sys/class/watchdog/watchdog0/max_timeout 3665038 [ 0.330082] s3c2410-wdt 10060000.watchdog_cl0: Heartbeat: count=3D109951= 1400000, timeout=3D3665038, freq=3D300000 [ 0.330087] s3c2410-wdt 10060000.watchdog_cl0: Heartbeat: timeout=3D3665= 038, divisor=3D256, count=3D1099511400000 (fffffc87) [ 0.330127] s3c2410-wdt 10060000.watchdog_cl0: starting watchdog timer [ 0.330134] s3c2410-wdt 10060000.watchdog_cl0: Starting watchdog: count= =3D0xfffffc87, wtcon=3D0001ff39 [ 0.330319] s3c2410-wdt 10060000.watchdog_cl0: watchdog active, reset en= abled, irq disabled If the system has a 32-bit WTCNT, add QUIRK_HAS_32BIT_CNT to its quirk flag= s, and it will operate with a 32-bit counter. If not, it will operate with a 1= 6-bit counter like in the previous version. Reviewed-by: Sam Protsenko Signed-off-by: Sangwook Shin Reviewed-by: Alim Akhtar Reviewed-by: Guenter Roeck --- drivers/watchdog/s3c2410_wdt.c | 26 +++++++++++++++++++------- 1 file changed, 19 insertions(+), 7 deletions(-) diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c index 1e8cf0299713..d983cbcb975c 100644 --- a/drivers/watchdog/s3c2410_wdt.c +++ b/drivers/watchdog/s3c2410_wdt.c @@ -34,7 +34,8 @@ #define S3C2410_WTCNT 0x08 #define S3C2410_WTCLRINT 0x0c =20 -#define S3C2410_WTCNT_MAXCNT 0xffff +#define S3C2410_WTCNT_MAXCNT_16 0xffff +#define S3C2410_WTCNT_MAXCNT_32 0xffffffff =20 #define S3C2410_WTCON_RSTEN BIT(0) #define S3C2410_WTCON_INTEN BIT(2) @@ -124,6 +125,10 @@ * %QUIRK_HAS_DBGACK_BIT: WTCON register has DBGACK_MASK bit. Setting the * DBGACK_MASK bit disables the watchdog outputs when the SoC is in debug = mode. * Debug mode is determined by the DBGACK CPU signal. + * + * %QUIRK_HAS_32BIT_CNT: WTDAT and WTCNT are 32-bit registers. With these + * 32-bit registers, larger values will be set, which means that larger ti= meouts + * value can be set. */ #define QUIRK_HAS_WTCLRINT_REG BIT(0) #define QUIRK_HAS_PMU_MASK_RESET BIT(1) @@ -131,6 +136,7 @@ #define QUIRK_HAS_PMU_AUTO_DISABLE BIT(3) #define QUIRK_HAS_PMU_CNT_EN BIT(4) #define QUIRK_HAS_DBGACK_BIT BIT(5) +#define QUIRK_HAS_32BIT_CNT BIT(6) =20 /* These quirks require that we have a PMU register map */ #define QUIRKS_HAVE_PMUREG \ @@ -199,6 +205,7 @@ struct s3c2410_wdt { struct notifier_block freq_transition; const struct s3c2410_wdt_variant *drv_data; struct regmap *pmureg; + u32 max_cnt; }; =20 static const struct s3c2410_wdt_variant drv_data_s3c2410 =3D { @@ -412,7 +419,7 @@ static inline unsigned int s3c2410wdt_max_timeout(struc= t s3c2410_wdt *wdt) { const unsigned long freq =3D s3c2410wdt_get_freq(wdt); const u64 n_max =3D (u64)(S3C2410_WTCON_PRESCALE_MAX + 1) * - S3C2410_WTCON_MAXDIV * S3C2410_WTCNT_MAXCNT; + S3C2410_WTCON_MAXDIV * wdt->max_cnt; u64 t_max =3D div64_ul(n_max, freq); =20 if (t_max > UINT_MAX) @@ -572,7 +579,7 @@ static int s3c2410wdt_set_heartbeat(struct watchdog_dev= ice *wdd, { struct s3c2410_wdt *wdt =3D watchdog_get_drvdata(wdd); unsigned long freq =3D s3c2410wdt_get_freq(wdt); - unsigned int count; + unsigned long count; unsigned int divisor =3D 1; unsigned long wtcon; =20 @@ -582,7 +589,7 @@ static int s3c2410wdt_set_heartbeat(struct watchdog_dev= ice *wdd, freq =3D DIV_ROUND_UP(freq, 128); count =3D timeout * freq; =20 - dev_dbg(wdt->dev, "Heartbeat: count=3D%d, timeout=3D%d, freq=3D%lu\n", + dev_dbg(wdt->dev, "Heartbeat: count=3D%lu, timeout=3D%d, freq=3D%lu\n", count, timeout, freq); =20 /* if the count is bigger than the watchdog register, @@ -590,8 +597,8 @@ static int s3c2410wdt_set_heartbeat(struct watchdog_dev= ice *wdd, actually make this value */ =20 - if (count >=3D 0x10000) { - divisor =3D DIV_ROUND_UP(count, 0xffff); + if (count > wdt->max_cnt) { + divisor =3D DIV_ROUND_UP(count, wdt->max_cnt); =20 if (divisor > S3C2410_WTCON_PRESCALE_MAX + 1) { dev_err(wdt->dev, "timeout %d too big\n", timeout); @@ -599,7 +606,7 @@ static int s3c2410wdt_set_heartbeat(struct watchdog_dev= ice *wdd, } } =20 - dev_dbg(wdt->dev, "Heartbeat: timeout=3D%d, divisor=3D%d, count=3D%d (%08= x)\n", + dev_dbg(wdt->dev, "Heartbeat: timeout=3D%d, divisor=3D%d, count=3D%lu (%0= 8lx)\n", timeout, divisor, count, DIV_ROUND_UP(count, divisor)); =20 count =3D DIV_ROUND_UP(count, divisor); @@ -807,6 +814,11 @@ static int s3c2410wdt_probe(struct platform_device *pd= ev) if (IS_ERR(wdt->src_clk)) return dev_err_probe(dev, PTR_ERR(wdt->src_clk), "failed to get source c= lock\n"); =20 + if (wdt->drv_data->quirks & QUIRK_HAS_32BIT_CNT) + wdt->max_cnt =3D S3C2410_WTCNT_MAXCNT_32; + else + wdt->max_cnt =3D S3C2410_WTCNT_MAXCNT_16; + wdt->wdt_device.min_timeout =3D 1; wdt->wdt_device.max_timeout =3D s3c2410wdt_max_timeout(wdt); =20 --=20 2.25.1