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The value 0x100 in the s3c2410wdt_set_heartbeat function represents S3C2410_WTCON_PRESCALE_MAX + 1, but it is hardcoded, making its meaning difficult to understand and reducing code readability. Reviewed-by: Sam Protsenko Reviewed-by: Alim Akhtar Signed-off-by: Sangwook Shin Reviewed-by: Guenter Roeck --- drivers/watchdog/s3c2410_wdt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c index 40901bdac426..95f7207e390a 100644 --- a/drivers/watchdog/s3c2410_wdt.c +++ b/drivers/watchdog/s3c2410_wdt.c @@ -587,7 +587,7 @@ static int s3c2410wdt_set_heartbeat(struct watchdog_dev= ice *wdd, if (count >=3D 0x10000) { divisor =3D DIV_ROUND_UP(count, 0xffff); =20 - if (divisor > 0x100) { + if (divisor > S3C2410_WTCON_PRESCALE_MAX + 1) { dev_err(wdt->dev, "timeout %d too big\n", timeout); return -EINVAL; } --=20 2.25.1 From nobody Sat Oct 4 11:13:46 2025 Received: from mailout1.samsung.com (mailout1.samsung.com [203.254.224.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 718122571A5 for ; Mon, 18 Aug 2025 02:24:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Mon, 18 Aug 2025 02:24:34 +0000 (GMT) Received: from epcas2p2.samsung.com (unknown [182.195.36.99]) by epsnrtp02.localdomain (Postfix) with ESMTP id 4c4xPG24nDz2SSKf; Mon, 18 Aug 2025 02:24:34 +0000 (GMT) Received: from epsmtip1.samsung.com (unknown [182.195.34.30]) by epcas2p3.samsung.com (KnoxPortal) with ESMTPA id 20250818022433epcas2p3fc48febfa6729645af6ebd088937c80c~cu0gxZS4m0148401484epcas2p3R; Mon, 18 Aug 2025 02:24:33 +0000 (GMT) Received: from localhost.localdomain (unknown [10.229.9.126]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20250818022433epsmtip134777d3422bc84da61719ae40059d335~cu0gsjRKQ2020320203epsmtip1O; Mon, 18 Aug 2025 02:24:33 +0000 (GMT) From: Sangwook Shin To: krzk@kernel.org, alim.akhtar@samsung.com, wim@linux-watchdog.org, linux@roeck-us.net, semen.protsenko@linaro.org, dongil01.park@samsung.com, khwan.seo@samsung.com Cc: linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-watchdog@vger.kernel.org, linux-kernel@vger.kernel.org, Sangwook Shin Subject: [PATCH v6 2/5] watchdog: s3c2410_wdt: Fix max_timeout being calculated larger Date: Mon, 18 Aug 2025 11:18:23 +0900 Message-Id: <20250818021826.623830-3-sw617.shin@samsung.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250818021826.623830-1-sw617.shin@samsung.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CMS-MailID: 20250818022433epcas2p3fc48febfa6729645af6ebd088937c80c X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-Sendblock-Type: AUTO_CONFIDENTIAL CMS-TYPE: 102P cpgsPolicy: CPGSC10-234,N X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250818022433epcas2p3fc48febfa6729645af6ebd088937c80c References: <20250818021826.623830-1-sw617.shin@samsung.com> Fix the issue of max_timeout being calculated larger than actual value. The calculation result of freq / (S3C2410_WTCON_PRESCALE_MAX + 1) / S3C2410_WTCON_MAXDIV is smaller than the actual value because the remainder is discarded during the calculation process. This leads to a larger calculated value for max_timeout compared to the actual settable value. To resolve this issue, the order of calculations in the computation process has been adjusted. Reviewed-by: Sam Protsenko Signed-off-by: Sangwook Shin Reviewed-by: Alim Akhtar Reviewed-by: Guenter Roeck --- drivers/watchdog/s3c2410_wdt.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c index 95f7207e390a..1e8cf0299713 100644 --- a/drivers/watchdog/s3c2410_wdt.c +++ b/drivers/watchdog/s3c2410_wdt.c @@ -27,6 +27,7 @@ #include #include #include +#include =20 #define S3C2410_WTCON 0x00 #define S3C2410_WTDAT 0x04 @@ -410,9 +411,14 @@ static inline unsigned long s3c2410wdt_get_freq(struct= s3c2410_wdt *wdt) static inline unsigned int s3c2410wdt_max_timeout(struct s3c2410_wdt *wdt) { const unsigned long freq =3D s3c2410wdt_get_freq(wdt); + const u64 n_max =3D (u64)(S3C2410_WTCON_PRESCALE_MAX + 1) * + S3C2410_WTCON_MAXDIV * S3C2410_WTCNT_MAXCNT; + u64 t_max =3D div64_ul(n_max, freq); =20 - return S3C2410_WTCNT_MAXCNT / (freq / (S3C2410_WTCON_PRESCALE_MAX + 1) - / S3C2410_WTCON_MAXDIV); + if (t_max > UINT_MAX) + t_max =3D UINT_MAX; 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Mon, 18 Aug 2025 02:24:33 +0000 (GMT) From: Sangwook Shin To: krzk@kernel.org, alim.akhtar@samsung.com, wim@linux-watchdog.org, linux@roeck-us.net, semen.protsenko@linaro.org, dongil01.park@samsung.com, khwan.seo@samsung.com Cc: linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-watchdog@vger.kernel.org, linux-kernel@vger.kernel.org, Sangwook Shin Subject: [PATCH v6 3/5] watchdog: s3c2410_wdt: Increase max timeout value of watchdog Date: Mon, 18 Aug 2025 11:18:24 +0900 Message-Id: <20250818021826.623830-4-sw617.shin@samsung.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250818021826.623830-1-sw617.shin@samsung.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CMS-MailID: 20250818022433epcas2p1bf8e6a335be945822721b8db1e9571e9 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-Sendblock-Type: AUTO_CONFIDENTIAL CMS-TYPE: 102P cpgsPolicy: CPGSC10-234,N X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250818022433epcas2p1bf8e6a335be945822721b8db1e9571e9 References: <20250818021826.623830-1-sw617.shin@samsung.com> Increase max_timeout value from 55s to 3665038s (1018h 3min 58s) with 38400000 frequency system if the system has 32-bit WTCNT register. cat /sys/class/watchdog/watchdog0/max_timeout 3665038 [ 0.330082] s3c2410-wdt 10060000.watchdog_cl0: Heartbeat: count=3D109951= 1400000, timeout=3D3665038, freq=3D300000 [ 0.330087] s3c2410-wdt 10060000.watchdog_cl0: Heartbeat: timeout=3D3665= 038, divisor=3D256, count=3D1099511400000 (fffffc87) [ 0.330127] s3c2410-wdt 10060000.watchdog_cl0: starting watchdog timer [ 0.330134] s3c2410-wdt 10060000.watchdog_cl0: Starting watchdog: count= =3D0xfffffc87, wtcon=3D0001ff39 [ 0.330319] s3c2410-wdt 10060000.watchdog_cl0: watchdog active, reset en= abled, irq disabled If the system has a 32-bit WTCNT, add QUIRK_HAS_32BIT_CNT to its quirk flag= s, and it will operate with a 32-bit counter. If not, it will operate with a 1= 6-bit counter like in the previous version. Reviewed-by: Sam Protsenko Signed-off-by: Sangwook Shin Reviewed-by: Alim Akhtar Reviewed-by: Guenter Roeck --- drivers/watchdog/s3c2410_wdt.c | 26 +++++++++++++++++++------- 1 file changed, 19 insertions(+), 7 deletions(-) diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c index 1e8cf0299713..d983cbcb975c 100644 --- a/drivers/watchdog/s3c2410_wdt.c +++ b/drivers/watchdog/s3c2410_wdt.c @@ -34,7 +34,8 @@ #define S3C2410_WTCNT 0x08 #define S3C2410_WTCLRINT 0x0c =20 -#define S3C2410_WTCNT_MAXCNT 0xffff +#define S3C2410_WTCNT_MAXCNT_16 0xffff +#define S3C2410_WTCNT_MAXCNT_32 0xffffffff =20 #define S3C2410_WTCON_RSTEN BIT(0) #define S3C2410_WTCON_INTEN BIT(2) @@ -124,6 +125,10 @@ * %QUIRK_HAS_DBGACK_BIT: WTCON register has DBGACK_MASK bit. Setting the * DBGACK_MASK bit disables the watchdog outputs when the SoC is in debug = mode. * Debug mode is determined by the DBGACK CPU signal. + * + * %QUIRK_HAS_32BIT_CNT: WTDAT and WTCNT are 32-bit registers. With these + * 32-bit registers, larger values will be set, which means that larger ti= meouts + * value can be set. */ #define QUIRK_HAS_WTCLRINT_REG BIT(0) #define QUIRK_HAS_PMU_MASK_RESET BIT(1) @@ -131,6 +136,7 @@ #define QUIRK_HAS_PMU_AUTO_DISABLE BIT(3) #define QUIRK_HAS_PMU_CNT_EN BIT(4) #define QUIRK_HAS_DBGACK_BIT BIT(5) +#define QUIRK_HAS_32BIT_CNT BIT(6) =20 /* These quirks require that we have a PMU register map */ #define QUIRKS_HAVE_PMUREG \ @@ -199,6 +205,7 @@ struct s3c2410_wdt { struct notifier_block freq_transition; const struct s3c2410_wdt_variant *drv_data; struct regmap *pmureg; + u32 max_cnt; }; =20 static const struct s3c2410_wdt_variant drv_data_s3c2410 =3D { @@ -412,7 +419,7 @@ static inline unsigned int s3c2410wdt_max_timeout(struc= t s3c2410_wdt *wdt) { const unsigned long freq =3D s3c2410wdt_get_freq(wdt); const u64 n_max =3D (u64)(S3C2410_WTCON_PRESCALE_MAX + 1) * - S3C2410_WTCON_MAXDIV * S3C2410_WTCNT_MAXCNT; + S3C2410_WTCON_MAXDIV * wdt->max_cnt; u64 t_max =3D div64_ul(n_max, freq); =20 if (t_max > UINT_MAX) @@ -572,7 +579,7 @@ static int s3c2410wdt_set_heartbeat(struct watchdog_dev= ice *wdd, { struct s3c2410_wdt *wdt =3D watchdog_get_drvdata(wdd); unsigned long freq =3D s3c2410wdt_get_freq(wdt); - unsigned int count; + unsigned long count; unsigned int divisor =3D 1; unsigned long wtcon; =20 @@ -582,7 +589,7 @@ static int s3c2410wdt_set_heartbeat(struct watchdog_dev= ice *wdd, freq =3D DIV_ROUND_UP(freq, 128); count =3D timeout * freq; =20 - dev_dbg(wdt->dev, "Heartbeat: count=3D%d, timeout=3D%d, freq=3D%lu\n", + dev_dbg(wdt->dev, "Heartbeat: count=3D%lu, timeout=3D%d, freq=3D%lu\n", count, timeout, freq); =20 /* if the count is bigger than the watchdog register, @@ -590,8 +597,8 @@ static int s3c2410wdt_set_heartbeat(struct watchdog_dev= ice *wdd, actually make this value */ =20 - if (count >=3D 0x10000) { - divisor =3D DIV_ROUND_UP(count, 0xffff); + if (count > wdt->max_cnt) { + divisor =3D DIV_ROUND_UP(count, wdt->max_cnt); =20 if (divisor > S3C2410_WTCON_PRESCALE_MAX + 1) { dev_err(wdt->dev, "timeout %d too big\n", timeout); @@ -599,7 +606,7 @@ static int s3c2410wdt_set_heartbeat(struct watchdog_dev= ice *wdd, } } =20 - dev_dbg(wdt->dev, "Heartbeat: timeout=3D%d, divisor=3D%d, count=3D%d (%08= x)\n", + dev_dbg(wdt->dev, "Heartbeat: timeout=3D%d, divisor=3D%d, count=3D%lu (%0= 8lx)\n", timeout, divisor, count, DIV_ROUND_UP(count, divisor)); =20 count =3D DIV_ROUND_UP(count, divisor); @@ -807,6 +814,11 @@ static int s3c2410wdt_probe(struct platform_device *pd= ev) if (IS_ERR(wdt->src_clk)) return dev_err_probe(dev, PTR_ERR(wdt->src_clk), "failed to get source c= lock\n"); =20 + if (wdt->drv_data->quirks & QUIRK_HAS_32BIT_CNT) + wdt->max_cnt =3D S3C2410_WTCNT_MAXCNT_32; + else + wdt->max_cnt =3D S3C2410_WTCNT_MAXCNT_16; + wdt->wdt_device.min_timeout =3D 1; wdt->wdt_device.max_timeout =3D s3c2410wdt_max_timeout(wdt); =20 --=20 2.25.1 From nobody Sat Oct 4 11:13:46 2025 Received: from mailout4.samsung.com (mailout4.samsung.com [203.254.224.34]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 836F02561AA for ; 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Mon, 18 Aug 2025 02:24:34 +0000 (GMT) Received: from epcas2p3.samsung.com (unknown [182.195.36.68]) by epsnrtp04.localdomain (Postfix) with ESMTP id 4c4xPG250vz6B9mG; Mon, 18 Aug 2025 02:24:34 +0000 (GMT) Received: from epsmtip1.samsung.com (unknown [182.195.34.30]) by epcas2p4.samsung.com (KnoxPortal) with ESMTPA id 20250818022433epcas2p4fec1cccd280fc73dccc5b00e2236f836~cu0g9KQ3e2945329453epcas2p4O; Mon, 18 Aug 2025 02:24:33 +0000 (GMT) Received: from localhost.localdomain (unknown [10.229.9.126]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20250818022433epsmtip1332c50c1db103d4bbdcee250138ca793~cu0g22E_C2171021710epsmtip1K; Mon, 18 Aug 2025 02:24:33 +0000 (GMT) From: Sangwook Shin To: krzk@kernel.org, alim.akhtar@samsung.com, wim@linux-watchdog.org, linux@roeck-us.net, semen.protsenko@linaro.org, dongil01.park@samsung.com, khwan.seo@samsung.com Cc: linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-watchdog@vger.kernel.org, linux-kernel@vger.kernel.org, Sangwook Shin Subject: [PATCH v6 4/5] watchdog: s3c2410_wdt: exynosautov920: Enable QUIRK_HAS_32BIT_CNT Date: Mon, 18 Aug 2025 11:18:25 +0900 Message-Id: <20250818021826.623830-5-sw617.shin@samsung.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250818021826.623830-1-sw617.shin@samsung.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CMS-MailID: 20250818022433epcas2p4fec1cccd280fc73dccc5b00e2236f836 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-Sendblock-Type: AUTO_CONFIDENTIAL CMS-TYPE: 102P cpgsPolicy: CPGSC10-234,N X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250818022433epcas2p4fec1cccd280fc73dccc5b00e2236f836 References: <20250818021826.623830-1-sw617.shin@samsung.com> Enable QUIRK_HAS_32BIT_CNT to ExynosAutov920 SoC which has 32-bit WTCNT. Reviewed-by: Sam Protsenko Signed-off-by: Sangwook Shin Reviewed-by: Alim Akhtar Reviewed-by: Guenter Roeck --- drivers/watchdog/s3c2410_wdt.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c index d983cbcb975c..915d3c88565a 100644 --- a/drivers/watchdog/s3c2410_wdt.c +++ b/drivers/watchdog/s3c2410_wdt.c @@ -357,7 +357,7 @@ static const struct s3c2410_wdt_variant drv_data_exynos= autov920_cl0 =3D { .cnt_en_bit =3D 8, .quirks =3D QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_PMU_MASK_RESET | QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_CNT_EN | - QUIRK_HAS_DBGACK_BIT, + QUIRK_HAS_DBGACK_BIT | QUIRK_HAS_32BIT_CNT, }; =20 static const struct s3c2410_wdt_variant drv_data_exynosautov920_cl1 =3D { @@ -370,7 +370,7 @@ static const struct s3c2410_wdt_variant drv_data_exynos= autov920_cl1 =3D { .cnt_en_bit =3D 8, .quirks =3D QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_PMU_MASK_RESET | QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_CNT_EN | - QUIRK_HAS_DBGACK_BIT, + QUIRK_HAS_DBGACK_BIT | QUIRK_HAS_32BIT_CNT, }; =20 static const struct of_device_id s3c2410_wdt_match[] =3D { --=20 2.25.1 From nobody Sat Oct 4 11:13:46 2025 Received: from mailout2.samsung.com (mailout2.samsung.com [203.254.224.25]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5745725394B for ; Mon, 18 Aug 2025 02:24:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=203.254.224.25 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755483880; cv=none; b=CfCL9FjvN9YA6bSTrywdNC+S3tcWMGiAh+8c9a7JoB6zLUAvmUPL5/yLO+MDmd7C8ZWigyedwWkoi/uUf23Ny8ZugdnNiDMpup5ZWji/yYejMzJ4DUOrZPo1jkA5yLPBQtvjE3RHRDjJ4JCH1nI2iTwVC751YuDudtYSNh9mdmk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755483880; c=relaxed/simple; bh=IjSu0FqxtK8qVNVlBAVyRBAm9ZI3BxjjnWb4CJZra1g=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:MIME-Version: Content-Type:References; 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Mon, 18 Aug 2025 02:24:33 +0000 (GMT) From: Sangwook Shin To: krzk@kernel.org, alim.akhtar@samsung.com, wim@linux-watchdog.org, linux@roeck-us.net, semen.protsenko@linaro.org, dongil01.park@samsung.com, khwan.seo@samsung.com Cc: linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-watchdog@vger.kernel.org, linux-kernel@vger.kernel.org, Sangwook Shin Subject: [PATCH v6 5/5] watchdog: s3c2410_wdt: exynosautov9: Enable supported features Date: Mon, 18 Aug 2025 11:18:26 +0900 Message-Id: <20250818021826.623830-6-sw617.shin@samsung.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250818021826.623830-1-sw617.shin@samsung.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CMS-MailID: 20250818022433epcas2p15ec2e45f26f6ff5fb69f0b1e377616f4 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-Sendblock-Type: AUTO_CONFIDENTIAL CMS-TYPE: 102P cpgsPolicy: CPGSC10-234,N X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250818022433epcas2p15ec2e45f26f6ff5fb69f0b1e377616f4 References: <20250818021826.623830-1-sw617.shin@samsung.com> Enable supported features for ExynosAutov9 SoC. - QUIRK_HAS_DBGACK_BIT - QUIRK_HAS_32BIT_CNT Reviewed-by: Sam Protsenko Signed-off-by: Sangwook Shin Reviewed-by: Alim Akhtar Reviewed-by: Guenter Roeck --- drivers/watchdog/s3c2410_wdt.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c index 915d3c88565a..b774477190b6 100644 --- a/drivers/watchdog/s3c2410_wdt.c +++ b/drivers/watchdog/s3c2410_wdt.c @@ -306,7 +306,8 @@ static const struct s3c2410_wdt_variant drv_data_exynos= autov9_cl0 =3D { .cnt_en_reg =3D EXYNOS850_CLUSTER0_NONCPU_OUT, .cnt_en_bit =3D 7, .quirks =3D QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_PMU_MASK_RESET | - QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_CNT_EN, + QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_CNT_EN | + QUIRK_HAS_DBGACK_BIT | QUIRK_HAS_32BIT_CNT, }; =20 static const struct s3c2410_wdt_variant drv_data_exynosautov9_cl1 =3D { @@ -318,7 +319,8 @@ static const struct s3c2410_wdt_variant drv_data_exynos= autov9_cl1 =3D { .cnt_en_reg =3D EXYNOSAUTOV9_CLUSTER1_NONCPU_OUT, .cnt_en_bit =3D 7, .quirks =3D QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_PMU_MASK_RESET | - QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_CNT_EN, + QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_CNT_EN | + QUIRK_HAS_DBGACK_BIT | QUIRK_HAS_32BIT_CNT, }; =20 static const struct s3c2410_wdt_variant drv_data_gs101_cl0 =3D { --=20 2.25.1