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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lei Wei , Suruchi Agarwal , Pavithra R , "Simon Horman" , Jonathan Corbet , Kees Cook , "Gustavo A. R. Silva" , "Philipp Zabel" CC: , , , , , , , , Luo Jie X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1755522889; l=15749; i=quic_luoj@quicinc.com; s=20250209; h=from:subject:message-id; bh=NthzY7UmfPbVUlNev74fcfHYMPzy1nxkOCl2iULOsq4=; b=n4NcnfO+dn5vu8Om3MUq5Bm5SksGMJ9m9IxmFtygQevckYW3T9MVJtmYH/xIWb5L9TOzzjeKT 1kqgCN7QEdZCoCi0W40Ww8mpQAUadDyKISm2o43oIGqMybQpcOBfUFO X-Developer-Key: i=quic_luoj@quicinc.com; a=ed25519; pk=pzwy8bU5tJZ5UKGTv28n+QOuktaWuriznGmriA9Qkfc= X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: O44LWBneQHvCsZx09zzYtaFVOaZlUMOC X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODE2MDAyMCBTYWx0ZWRfX7bUSfiE3dC77 s3ZZj4XfnD7jWx5I7z2OpuYM1RpBfrrKGiINcNr2+LXm3Q+DFAR/AHF+5AMccPKSFaTlXGbULx2 3wQkXcUQN1ELq3oy4uLKHEtFFnXafY+3y83o2iP7YX38qrKpySyvnSsJP21FIBzs3HQG5H7IzsS c0aRwPt5+jHQn2/u2b3dfK7dBJEbERSKAv6y3mLPciT1tHsILI5s5gbN92WLn6v5GWZsRLlw5CR yUzksnlVGrz9Mq3RctGq12QaN2Xwi0atGatn0NGt5/n4sFT+AQ5rLANWdGLIoMrYU/KGm+dub8J i+4icrxMMKxsbgqd4MNnGvgtnn9Z5vIfEPhXONfCvwk6IDvvYMPUdVT8savTFNT8kBiao+VX6kY 4PGbi0T+ X-Authority-Analysis: v=2.4 cv=a+Mw9VSF c=1 sm=1 tr=0 ts=68a32778 cx=c_pps a=JYp8KDb2vCoCEuGobkYCKw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=GEpy-HfZoHoA:10 a=IkcTkHD0fZMA:10 a=2OwXVqhp2XgA:10 a=COk6AnOGAAAA:8 a=bbYyvoBojASMYFRgmj8A:9 a=QEXdDO2ut3YA:10 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: O44LWBneQHvCsZx09zzYtaFVOaZlUMOC X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-18_05,2025-08-14_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 malwarescore=0 suspectscore=0 impostorscore=0 phishscore=0 adultscore=0 priorityscore=1501 clxscore=1015 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508160020 PPE service code is a special code (0-255) that is defined by PPE for PPE's packet processing stages, as per the network functions required for the packet. For packet being sent out by ARM cores on Ethernet ports, The service code 1 is used as the default service code. This service code is used to bypass most of packet processing stages of the PPE before the packet transmitted out PPE port, since the software network stack has already processed the packet. Signed-off-by: Luo Jie --- drivers/net/ethernet/qualcomm/ppe/ppe_config.c | 95 +++++++++++++++- drivers/net/ethernet/qualcomm/ppe/ppe_config.h | 145 +++++++++++++++++++++= ++++ drivers/net/ethernet/qualcomm/ppe/ppe_regs.h | 53 +++++++++ 3 files changed, 292 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/qualcomm/ppe/ppe_config.c b/drivers/net/e= thernet/qualcomm/ppe/ppe_config.c index 9037702460b5..39a01f25f5ef 100644 --- a/drivers/net/ethernet/qualcomm/ppe/ppe_config.c +++ b/drivers/net/ethernet/qualcomm/ppe/ppe_config.c @@ -8,6 +8,7 @@ */ =20 #include +#include #include #include #include @@ -1108,6 +1109,75 @@ int ppe_port_resource_get(struct ppe_device *ppe_dev= , int port, return 0; } =20 +/** + * ppe_sc_config_set - Set PPE service code configuration + * @ppe_dev: PPE device + * @sc: Service ID, 0-255 supported by PPE + * @cfg: Service code configuration + * + * PPE service code is used by the PPE during its packet processing stages, + * to perform or bypass certain selected packet operations on the packet. + * + * Return: 0 on success, negative error code on failure. + */ +int ppe_sc_config_set(struct ppe_device *ppe_dev, int sc, struct ppe_sc_cf= g cfg) +{ + u32 val, reg, servcode_val[2] =3D {}; + unsigned long bitmap_value; + int ret; + + val =3D FIELD_PREP(PPE_IN_L2_SERVICE_TBL_DST_PORT_ID_VALID, cfg.dest_port= _valid); + val |=3D FIELD_PREP(PPE_IN_L2_SERVICE_TBL_DST_PORT_ID, cfg.dest_port); + val |=3D FIELD_PREP(PPE_IN_L2_SERVICE_TBL_DST_DIRECTION, cfg.is_src); + + bitmap_value =3D bitmap_read(cfg.bitmaps.egress, 0, PPE_SC_BYPASS_EGRESS_= SIZE); + val |=3D FIELD_PREP(PPE_IN_L2_SERVICE_TBL_DST_BYPASS_BITMAP, bitmap_value= ); + val |=3D FIELD_PREP(PPE_IN_L2_SERVICE_TBL_RX_CNT_EN, + test_bit(PPE_SC_BYPASS_COUNTER_RX, cfg.bitmaps.counter)); + val |=3D FIELD_PREP(PPE_IN_L2_SERVICE_TBL_TX_CNT_EN, + test_bit(PPE_SC_BYPASS_COUNTER_TX, cfg.bitmaps.counter)); + reg =3D PPE_IN_L2_SERVICE_TBL_ADDR + PPE_IN_L2_SERVICE_TBL_INC * sc; + + ret =3D regmap_write(ppe_dev->regmap, reg, val); + if (ret) + return ret; + + bitmap_value =3D bitmap_read(cfg.bitmaps.ingress, 0, PPE_SC_BYPASS_INGRES= S_SIZE); + PPE_SERVICE_SET_BYPASS_BITMAP(servcode_val, bitmap_value); + PPE_SERVICE_SET_RX_CNT_EN(servcode_val, + test_bit(PPE_SC_BYPASS_COUNTER_RX_VLAN, cfg.bitmaps.counter)); + reg =3D PPE_SERVICE_TBL_ADDR + PPE_SERVICE_TBL_INC * sc; + + ret =3D regmap_bulk_write(ppe_dev->regmap, reg, + servcode_val, ARRAY_SIZE(servcode_val)); + if (ret) + return ret; + + reg =3D PPE_EG_SERVICE_TBL_ADDR + PPE_EG_SERVICE_TBL_INC * sc; + ret =3D regmap_bulk_read(ppe_dev->regmap, reg, + servcode_val, ARRAY_SIZE(servcode_val)); + if (ret) + return ret; + + PPE_EG_SERVICE_SET_NEXT_SERVCODE(servcode_val, cfg.next_service_code); + PPE_EG_SERVICE_SET_UPDATE_ACTION(servcode_val, cfg.eip_field_update_bitma= p); + PPE_EG_SERVICE_SET_HW_SERVICE(servcode_val, cfg.eip_hw_service); + PPE_EG_SERVICE_SET_OFFSET_SEL(servcode_val, cfg.eip_offset_sel); + PPE_EG_SERVICE_SET_TX_CNT_EN(servcode_val, + test_bit(PPE_SC_BYPASS_COUNTER_TX_VLAN, cfg.bitmaps.counter)); + + ret =3D regmap_bulk_write(ppe_dev->regmap, reg, + servcode_val, ARRAY_SIZE(servcode_val)); + if (ret) + return ret; + + bitmap_value =3D bitmap_read(cfg.bitmaps.tunnel, 0, PPE_SC_BYPASS_TUNNEL_= SIZE); + val =3D FIELD_PREP(PPE_TL_SERVICE_TBL_BYPASS_BITMAP, bitmap_value); + reg =3D PPE_TL_SERVICE_TBL_ADDR + PPE_TL_SERVICE_TBL_INC * sc; + + return regmap_write(ppe_dev->regmap, reg, val); +} + static int ppe_config_bm_threshold(struct ppe_device *ppe_dev, int bm_port= _id, const struct ppe_bm_port_config port_cfg) { @@ -1517,6 +1587,25 @@ static int ppe_queue_dest_init(struct ppe_device *pp= e_dev) return 0; } =20 +/* Initialize the service code 1 used by CPU port. */ +static int ppe_servcode_init(struct ppe_device *ppe_dev) +{ + struct ppe_sc_cfg sc_cfg =3D {}; + + bitmap_zero(sc_cfg.bitmaps.counter, PPE_SC_BYPASS_COUNTER_SIZE); + bitmap_zero(sc_cfg.bitmaps.tunnel, PPE_SC_BYPASS_TUNNEL_SIZE); + + bitmap_fill(sc_cfg.bitmaps.ingress, PPE_SC_BYPASS_INGRESS_SIZE); + clear_bit(PPE_SC_BYPASS_INGRESS_FAKE_MAC_HEADER, sc_cfg.bitmaps.ingress); + clear_bit(PPE_SC_BYPASS_INGRESS_SERVICE_CODE, sc_cfg.bitmaps.ingress); + clear_bit(PPE_SC_BYPASS_INGRESS_FAKE_L2_PROTO, sc_cfg.bitmaps.ingress); + + bitmap_fill(sc_cfg.bitmaps.egress, PPE_SC_BYPASS_EGRESS_SIZE); + clear_bit(PPE_SC_BYPASS_EGRESS_ACL_POST_ROUTING_CHECK, sc_cfg.bitmaps.egr= ess); + + return ppe_sc_config_set(ppe_dev, PPE_EDMA_SC_BYPASS_ID, sc_cfg); +} + int ppe_hw_config(struct ppe_device *ppe_dev) { int ret; @@ -1533,5 +1622,9 @@ int ppe_hw_config(struct ppe_device *ppe_dev) if (ret) return ret; =20 - return ppe_queue_dest_init(ppe_dev); + ret =3D ppe_queue_dest_init(ppe_dev); + if (ret) + return ret; + + return ppe_servcode_init(ppe_dev); } diff --git a/drivers/net/ethernet/qualcomm/ppe/ppe_config.h b/drivers/net/e= thernet/qualcomm/ppe/ppe_config.h index b4fd5f833bac..2b3f7e39cc7e 100644 --- a/drivers/net/ethernet/qualcomm/ppe/ppe_config.h +++ b/drivers/net/ethernet/qualcomm/ppe/ppe_config.h @@ -6,6 +6,8 @@ #ifndef __PPE_CONFIG_H__ #define __PPE_CONFIG_H__ =20 +#include + #include "ppe.h" =20 /* There are different table index ranges for configuring queue base ID of @@ -18,6 +20,9 @@ #define PPE_QUEUE_INTER_PRI_NUM 16 #define PPE_QUEUE_HASH_NUM 256 =20 +/* The service code is used by EDMA port to transmit packet to PPE. */ +#define PPE_EDMA_SC_BYPASS_ID 1 + /** * enum ppe_scheduler_frame_mode - PPE scheduler frame mode. * @PPE_SCH_WITH_IPG_PREAMBLE_FRAME_CRC: The scheduled frame includes IPG, @@ -90,6 +95,144 @@ struct ppe_queue_ucast_dest { int dest_port; }; =20 +/* Hardware bitmaps for bypassing features of the ingress packet. */ +enum ppe_sc_ingress_type { + PPE_SC_BYPASS_INGRESS_VLAN_TAG_FMT_CHECK =3D 0, + PPE_SC_BYPASS_INGRESS_VLAN_MEMBER_CHECK =3D 1, + PPE_SC_BYPASS_INGRESS_VLAN_TRANSLATE =3D 2, + PPE_SC_BYPASS_INGRESS_MY_MAC_CHECK =3D 3, + PPE_SC_BYPASS_INGRESS_DIP_LOOKUP =3D 4, + PPE_SC_BYPASS_INGRESS_FLOW_LOOKUP =3D 5, + PPE_SC_BYPASS_INGRESS_FLOW_ACTION =3D 6, + PPE_SC_BYPASS_INGRESS_ACL =3D 7, + PPE_SC_BYPASS_INGRESS_FAKE_MAC_HEADER =3D 8, + PPE_SC_BYPASS_INGRESS_SERVICE_CODE =3D 9, + PPE_SC_BYPASS_INGRESS_WRONG_PKT_FMT_L2 =3D 10, + PPE_SC_BYPASS_INGRESS_WRONG_PKT_FMT_L3_IPV4 =3D 11, + PPE_SC_BYPASS_INGRESS_WRONG_PKT_FMT_L3_IPV6 =3D 12, + PPE_SC_BYPASS_INGRESS_WRONG_PKT_FMT_L4 =3D 13, + PPE_SC_BYPASS_INGRESS_FLOW_SERVICE_CODE =3D 14, + PPE_SC_BYPASS_INGRESS_ACL_SERVICE_CODE =3D 15, + PPE_SC_BYPASS_INGRESS_FAKE_L2_PROTO =3D 16, + PPE_SC_BYPASS_INGRESS_PPPOE_TERMINATION =3D 17, + PPE_SC_BYPASS_INGRESS_DEFAULT_VLAN =3D 18, + PPE_SC_BYPASS_INGRESS_DEFAULT_PCP =3D 19, + PPE_SC_BYPASS_INGRESS_VSI_ASSIGN =3D 20, + /* Values 21-23 are not specified by hardware. */ + PPE_SC_BYPASS_INGRESS_VLAN_ASSIGN_FAIL =3D 24, + PPE_SC_BYPASS_INGRESS_SOURCE_GUARD =3D 25, + PPE_SC_BYPASS_INGRESS_MRU_MTU_CHECK =3D 26, + PPE_SC_BYPASS_INGRESS_FLOW_SRC_CHECK =3D 27, + PPE_SC_BYPASS_INGRESS_FLOW_QOS =3D 28, + /* This must be last as it determines the size of the BITMAP. */ + PPE_SC_BYPASS_INGRESS_SIZE, +}; + +/* Hardware bitmaps for bypassing features of the egress packet. */ +enum ppe_sc_egress_type { + PPE_SC_BYPASS_EGRESS_VLAN_MEMBER_CHECK =3D 0, + PPE_SC_BYPASS_EGRESS_VLAN_TRANSLATE =3D 1, + PPE_SC_BYPASS_EGRESS_VLAN_TAG_FMT_CTRL =3D 2, + PPE_SC_BYPASS_EGRESS_FDB_LEARN =3D 3, + PPE_SC_BYPASS_EGRESS_FDB_REFRESH =3D 4, + PPE_SC_BYPASS_EGRESS_L2_SOURCE_SECURITY =3D 5, + PPE_SC_BYPASS_EGRESS_MANAGEMENT_FWD =3D 6, + PPE_SC_BYPASS_EGRESS_BRIDGING_FWD =3D 7, + PPE_SC_BYPASS_EGRESS_IN_STP_FLTR =3D 8, + PPE_SC_BYPASS_EGRESS_EG_STP_FLTR =3D 9, + PPE_SC_BYPASS_EGRESS_SOURCE_FLTR =3D 10, + PPE_SC_BYPASS_EGRESS_POLICER =3D 11, + PPE_SC_BYPASS_EGRESS_L2_PKT_EDIT =3D 12, + PPE_SC_BYPASS_EGRESS_L3_PKT_EDIT =3D 13, + PPE_SC_BYPASS_EGRESS_ACL_POST_ROUTING_CHECK =3D 14, + PPE_SC_BYPASS_EGRESS_PORT_ISOLATION =3D 15, + PPE_SC_BYPASS_EGRESS_PRE_ACL_QOS =3D 16, + PPE_SC_BYPASS_EGRESS_POST_ACL_QOS =3D 17, + PPE_SC_BYPASS_EGRESS_DSCP_QOS =3D 18, + PPE_SC_BYPASS_EGRESS_PCP_QOS =3D 19, + PPE_SC_BYPASS_EGRESS_PREHEADER_QOS =3D 20, + PPE_SC_BYPASS_EGRESS_FAKE_MAC_DROP =3D 21, + PPE_SC_BYPASS_EGRESS_TUNL_CONTEXT =3D 22, + PPE_SC_BYPASS_EGRESS_FLOW_POLICER =3D 23, + /* This must be last as it determines the size of the BITMAP. */ + PPE_SC_BYPASS_EGRESS_SIZE, +}; + +/* Hardware bitmaps for bypassing counter of packet. */ +enum ppe_sc_counter_type { + PPE_SC_BYPASS_COUNTER_RX_VLAN =3D 0, + PPE_SC_BYPASS_COUNTER_RX =3D 1, + PPE_SC_BYPASS_COUNTER_TX_VLAN =3D 2, + PPE_SC_BYPASS_COUNTER_TX =3D 3, + /* This must be last as it determines the size of the BITMAP. */ + PPE_SC_BYPASS_COUNTER_SIZE, +}; + +/* Hardware bitmaps for bypassing features of tunnel packet. */ +enum ppe_sc_tunnel_type { + PPE_SC_BYPASS_TUNNEL_SERVICE_CODE =3D 0, + PPE_SC_BYPASS_TUNNEL_TUNNEL_HANDLE =3D 1, + PPE_SC_BYPASS_TUNNEL_L3_IF_CHECK =3D 2, + PPE_SC_BYPASS_TUNNEL_VLAN_CHECK =3D 3, + PPE_SC_BYPASS_TUNNEL_DMAC_CHECK =3D 4, + PPE_SC_BYPASS_TUNNEL_UDP_CSUM_0_CHECK =3D 5, + PPE_SC_BYPASS_TUNNEL_TBL_DE_ACCE_CHECK =3D 6, + PPE_SC_BYPASS_TUNNEL_PPPOE_MC_TERM_CHECK =3D 7, + PPE_SC_BYPASS_TUNNEL_TTL_EXCEED_CHECK =3D 8, + PPE_SC_BYPASS_TUNNEL_MAP_SRC_CHECK =3D 9, + PPE_SC_BYPASS_TUNNEL_MAP_DST_CHECK =3D 10, + PPE_SC_BYPASS_TUNNEL_LPM_DST_LOOKUP =3D 11, + PPE_SC_BYPASS_TUNNEL_LPM_LOOKUP =3D 12, + PPE_SC_BYPASS_TUNNEL_WRONG_PKT_FMT_L2 =3D 13, + PPE_SC_BYPASS_TUNNEL_WRONG_PKT_FMT_L3_IPV4 =3D 14, + PPE_SC_BYPASS_TUNNEL_WRONG_PKT_FMT_L3_IPV6 =3D 15, + PPE_SC_BYPASS_TUNNEL_WRONG_PKT_FMT_L4 =3D 16, + PPE_SC_BYPASS_TUNNEL_WRONG_PKT_FMT_TUNNEL =3D 17, + /* Values 18-19 are not specified by hardware. */ + PPE_SC_BYPASS_TUNNEL_PRE_IPO =3D 20, + /* This must be last as it determines the size of the BITMAP. */ + PPE_SC_BYPASS_TUNNEL_SIZE, +}; + +/** + * struct ppe_sc_bypass - PPE service bypass bitmaps + * @ingress: Bitmap of features that can be bypassed on the ingress packet. + * @egress: Bitmap of features that can be bypassed on the egress packet. + * @counter: Bitmap of features that can be bypassed on the counter type. + * @tunnel: Bitmap of features that can be bypassed on the tunnel packet. + */ +struct ppe_sc_bypass { + DECLARE_BITMAP(ingress, PPE_SC_BYPASS_INGRESS_SIZE); + DECLARE_BITMAP(egress, PPE_SC_BYPASS_EGRESS_SIZE); + DECLARE_BITMAP(counter, PPE_SC_BYPASS_COUNTER_SIZE); + DECLARE_BITMAP(tunnel, PPE_SC_BYPASS_TUNNEL_SIZE); +}; + +/** + * struct ppe_sc_cfg - PPE service code configuration. + * @dest_port_valid: Generate destination port or not. + * @dest_port: Destination port ID. + * @bitmaps: Bitmap of bypass features. + * @is_src: Destination port acts as source port, packet sent to CPU. + * @next_service_code: New service code generated. + * @eip_field_update_bitmap: Fields updated as actions taken for EIP. + * @eip_hw_service: Selected hardware functions for EIP. + * @eip_offset_sel: Packet offset selection, using packet's layer 4 offset + * or using packet's layer 3 offset for EIP. + * + * Service code is generated during the packet passing through PPE. + */ +struct ppe_sc_cfg { + bool dest_port_valid; + int dest_port; + struct ppe_sc_bypass bitmaps; + bool is_src; + int next_service_code; + int eip_field_update_bitmap; + int eip_hw_service; + int eip_offset_sel; +}; + int ppe_hw_config(struct ppe_device *ppe_dev); int ppe_queue_scheduler_set(struct ppe_device *ppe_dev, int node_id, bool flow_level, int port, @@ -109,4 +252,6 @@ int ppe_queue_ucast_offset_hash_set(struct ppe_device *= ppe_dev, int ppe_port_resource_get(struct ppe_device *ppe_dev, int port, enum ppe_resource_type type, int *res_start, int *res_end); +int ppe_sc_config_set(struct ppe_device *ppe_dev, int sc, + struct ppe_sc_cfg cfg); #endif diff --git a/drivers/net/ethernet/qualcomm/ppe/ppe_regs.h b/drivers/net/eth= ernet/qualcomm/ppe/ppe_regs.h index 3776e619e70f..4cb76313db87 100644 --- a/drivers/net/ethernet/qualcomm/ppe/ppe_regs.h +++ b/drivers/net/ethernet/qualcomm/ppe/ppe_regs.h @@ -25,10 +25,63 @@ #define PPE_BM_SCH_CFG_TBL_SECOND_PORT_VALID BIT(6) #define PPE_BM_SCH_CFG_TBL_SECOND_PORT GENMASK(11, 8) =20 +/* PPE service code configuration for the ingress direction functions, + * including bypass configuration for relevant PPE switch core functions + * such as flow entry lookup bypass. + */ +#define PPE_SERVICE_TBL_ADDR 0x15000 +#define PPE_SERVICE_TBL_ENTRIES 256 +#define PPE_SERVICE_TBL_INC 0x10 +#define PPE_SERVICE_W0_BYPASS_BITMAP GENMASK(31, 0) +#define PPE_SERVICE_W1_RX_CNT_EN BIT(0) + +#define PPE_SERVICE_SET_BYPASS_BITMAP(tbl_cfg, value) \ + FIELD_MODIFY(PPE_SERVICE_W0_BYPASS_BITMAP, tbl_cfg, value) +#define PPE_SERVICE_SET_RX_CNT_EN(tbl_cfg, value) \ + FIELD_MODIFY(PPE_SERVICE_W1_RX_CNT_EN, (tbl_cfg) + 0x1, value) + /* PPE queue counters enable/disable control. */ #define PPE_EG_BRIDGE_CONFIG_ADDR 0x20044 #define PPE_EG_BRIDGE_CONFIG_QUEUE_CNT_EN BIT(2) =20 +/* PPE service code configuration on the egress direction. */ +#define PPE_EG_SERVICE_TBL_ADDR 0x43000 +#define PPE_EG_SERVICE_TBL_ENTRIES 256 +#define PPE_EG_SERVICE_TBL_INC 0x10 +#define PPE_EG_SERVICE_W0_UPDATE_ACTION GENMASK(31, 0) +#define PPE_EG_SERVICE_W1_NEXT_SERVCODE GENMASK(7, 0) +#define PPE_EG_SERVICE_W1_HW_SERVICE GENMASK(13, 8) +#define PPE_EG_SERVICE_W1_OFFSET_SEL BIT(14) +#define PPE_EG_SERVICE_W1_TX_CNT_EN BIT(15) + +#define PPE_EG_SERVICE_SET_UPDATE_ACTION(tbl_cfg, value) \ + FIELD_MODIFY(PPE_EG_SERVICE_W0_UPDATE_ACTION, tbl_cfg, value) +#define PPE_EG_SERVICE_SET_NEXT_SERVCODE(tbl_cfg, value) \ + FIELD_MODIFY(PPE_EG_SERVICE_W1_NEXT_SERVCODE, (tbl_cfg) + 0x1, value) +#define PPE_EG_SERVICE_SET_HW_SERVICE(tbl_cfg, value) \ + FIELD_MODIFY(PPE_EG_SERVICE_W1_HW_SERVICE, (tbl_cfg) + 0x1, value) +#define PPE_EG_SERVICE_SET_OFFSET_SEL(tbl_cfg, value) \ + FIELD_MODIFY(PPE_EG_SERVICE_W1_OFFSET_SEL, (tbl_cfg) + 0x1, value) +#define PPE_EG_SERVICE_SET_TX_CNT_EN(tbl_cfg, value) \ + FIELD_MODIFY(PPE_EG_SERVICE_W1_TX_CNT_EN, (tbl_cfg) + 0x1, value) + +/* PPE service code configuration for destination port and counter. */ +#define PPE_IN_L2_SERVICE_TBL_ADDR 0x66000 +#define PPE_IN_L2_SERVICE_TBL_ENTRIES 256 +#define PPE_IN_L2_SERVICE_TBL_INC 0x10 +#define PPE_IN_L2_SERVICE_TBL_DST_PORT_ID_VALID BIT(0) +#define PPE_IN_L2_SERVICE_TBL_DST_PORT_ID GENMASK(4, 1) +#define PPE_IN_L2_SERVICE_TBL_DST_DIRECTION BIT(5) +#define PPE_IN_L2_SERVICE_TBL_DST_BYPASS_BITMAP GENMASK(29, 6) +#define PPE_IN_L2_SERVICE_TBL_RX_CNT_EN BIT(30) +#define PPE_IN_L2_SERVICE_TBL_TX_CNT_EN BIT(31) + +/* PPE service code configuration for the tunnel packet. */ +#define PPE_TL_SERVICE_TBL_ADDR 0x306000 +#define PPE_TL_SERVICE_TBL_ENTRIES 256 +#define PPE_TL_SERVICE_TBL_INC 4 +#define PPE_TL_SERVICE_TBL_BYPASS_BITMAP GENMASK(31, 0) + /* Port scheduler global config. */ #define PPE_PSCH_SCH_DEPTH_CFG_ADDR 0x400000 #define PPE_PSCH_SCH_DEPTH_CFG_INC 4 --=20 2.34.1