From nobody Sat Oct 4 09:42:08 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6C08332C33A for ; Mon, 18 Aug 2025 18:59:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755543570; cv=none; b=JayoRVHAa1/ir9G+MaLOU1BebwdnpM9JLtvLDKp4yYURQf88i/1QkWA+LGQSDtRcmpBiNNSrLVGVbEW0yl7ipIJdr7dSYuIoRdGJGi2HqATbLFjRfrKbF8+lLngcBX4nSKiAgyqA4QpsvF3Q/c7nEhcvT8B3oQsRKVsjzwiaKx8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755543570; c=relaxed/simple; bh=4wV56OSShoqT9TNr4Pc+fmDF3yV2U2XrBU0YxwKlMCo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=JtUkotMvM+TbY83GTmAMpcRke60im+NL20YI+VaxfYcJLa6u+x1pJs24JMoIL8WrCDqeaYfBWqLS/dcSA6R8t2PXiXVKSxT6UY6XxhE3fM+6Qs+BT4yyTGXO6nVhtuY6daEVS/XzNNP4S/iAXf4MAuBZ6Hma0VIjrbrvy2RA5P8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=gcBbHmFz; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="gcBbHmFz" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1755543566; bh=4wV56OSShoqT9TNr4Pc+fmDF3yV2U2XrBU0YxwKlMCo=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=gcBbHmFzJGn9PRkKtNQcRxHPPVAHV1j8o9xBpiHBn71jqFNbYk1DWDz+eAqMhN3Nv tsG2Sr5YL9thonVwjJt41u2KuZYaRfTyup0sV350bMRywtNh0UY35AqTmVhUACmQOC /jsZ0vmcIGXNr4Q6eEJ6H2C9HHLJQtCcg3knoYq/NOvB69Y8+bjk7zJzbFWjDA24yM aPqrmrGnjjQzqCaJsNUp/dJQiTLAGHs6XLvRZbTw7RattFglUb0fYDk6CP02Br3W+0 EtVpCXrejPkveUf9iDawh/UZky0pUlYEtbqPzqbSILrqm6EZPXqR/PZFZ9Xd/EbosT eQhaQA3tkZVvQ== Received: from localhost (unknown [82.79.138.60]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (prime256v1) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by bali.collaboradmins.com (Postfix) with UTF8SMTPSA id 6D62A17E090E; Mon, 18 Aug 2025 20:59:26 +0200 (CEST) From: Cristian Ciocaltea Date: Mon, 18 Aug 2025 21:59:08 +0300 Subject: [PATCH v3 08/14] phy: rockchip: samsung-hdptx: Enable lane output in common helper Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250818-phy-hdptx-frl-v3-8-c79997d8bb2b@collabora.com> References: <20250818-phy-hdptx-frl-v3-0-c79997d8bb2b@collabora.com> In-Reply-To: <20250818-phy-hdptx-frl-v3-0-c79997d8bb2b@collabora.com> To: Vinod Koul , Kishon Vijay Abraham I , Heiko Stuebner , Algea Cao , Dmitry Baryshkov Cc: kernel@collabora.com, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.14.2 In preparation to support FRL mode, move the PHY lane output enablement from the TMDS specific configuration to the common *_post_enable_lane() helper and make sure it gets turned off in *_phy_disable(). Signed-off-by: Cristian Ciocaltea --- drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/ph= y/rockchip/phy-rockchip-samsung-hdptx.c index f2202b1195e7f24c455acdfa9bf2482ddddd6866..3bb4ce993088b4a6c17a40ecb23= 5ce98dc0eb9da 100644 --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c @@ -830,6 +830,8 @@ static int rk_hdptx_post_enable_lane(struct rk_hdptx_ph= y *hdptx) HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN; regmap_write(hdptx->grf, GRF_HDPTX_CON0, val); =20 + regmap_write(hdptx->regmap, LNTOP_REG(0207), 0x0f); + ret =3D regmap_read_poll_timeout(hdptx->grf, GRF_HDPTX_STATUS, val, (val & HDPTX_O_PHY_RDY) && (val & HDPTX_O_PLL_LOCK_DONE), @@ -883,6 +885,7 @@ static void rk_hdptx_phy_disable(struct rk_hdptx_phy *h= dptx) usleep_range(20, 30); reset_control_deassert(hdptx->rsts[RST_APB].rstc); =20 + regmap_write(hdptx->regmap, LNTOP_REG(0207), 0x0); regmap_write(hdptx->regmap, LANE_REG(0300), 0x82); regmap_write(hdptx->regmap, SB_REG(010f), 0xc1); regmap_write(hdptx->regmap, SB_REG(0110), 0x1); @@ -1060,7 +1063,6 @@ static int rk_hdptx_tmds_ropll_mode_config(struct rk_= hdptx_phy *hdptx) } =20 regmap_write(hdptx->regmap, LNTOP_REG(0206), 0x07); - regmap_write(hdptx->regmap, LNTOP_REG(0207), 0x0f); =20 rk_hdptx_multi_reg_write(hdptx, rk_hdptx_common_lane_init_seq); rk_hdptx_multi_reg_write(hdptx, rk_hdptx_tmds_lane_init_seq); --=20 2.50.1