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Mon, 18 Aug 2025 20:59:25 +0200 (CEST) From: Cristian Ciocaltea Date: Mon, 18 Aug 2025 21:59:07 +0300 Subject: [PATCH v3 07/14] phy: rockchip: samsung-hdptx: Consistently use [rk_]hdptx_[tmds_] prefixes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250818-phy-hdptx-frl-v3-7-c79997d8bb2b@collabora.com> References: <20250818-phy-hdptx-frl-v3-0-c79997d8bb2b@collabora.com> In-Reply-To: <20250818-phy-hdptx-frl-v3-0-c79997d8bb2b@collabora.com> To: Vinod Koul , Kishon Vijay Abraham I , Heiko Stuebner , Algea Cao , Dmitry Baryshkov Cc: kernel@collabora.com, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.14.2 Fix the naming inconsistencies for some of the functions and global variables: * Add the missing 'rk_hdptx_' prefix to ropll_tmds_cfg variable * Replace '_ropll_tmds_' with '_tmds_ropll_' globally * Replace 'hdtpx' with 'hdptx' globally Signed-off-by: Cristian Ciocaltea --- drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 62 +++++++++++--------= ---- 1 file changed, 31 insertions(+), 31 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/ph= y/rockchip/phy-rockchip-samsung-hdptx.c index 495427fc44b385e23da02cd21eefdb137d8b5fdb..f2202b1195e7f24c455acdfa9bf= 2482ddddd6866 100644 --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c @@ -32,17 +32,17 @@ #define HDPTX_O_PHY_RDY BIT(1) #define HDPTX_O_SB_RDY BIT(0) =20 -#define HDTPX_REG(_n, _min, _max) \ +#define HDPTX_REG(_n, _min, _max) \ ( \ BUILD_BUG_ON_ZERO((0x##_n) < (0x##_min)) + \ BUILD_BUG_ON_ZERO((0x##_n) > (0x##_max)) + \ ((0x##_n) * 4) \ ) =20 -#define CMN_REG(n) HDTPX_REG(n, 0000, 00a7) -#define SB_REG(n) HDTPX_REG(n, 0100, 0129) -#define LNTOP_REG(n) HDTPX_REG(n, 0200, 0229) -#define LANE_REG(n) HDTPX_REG(n, 0300, 062d) +#define CMN_REG(n) HDPTX_REG(n, 0000, 00a7) +#define SB_REG(n) HDPTX_REG(n, 0100, 0129) +#define LNTOP_REG(n) HDPTX_REG(n, 0200, 0229) +#define LANE_REG(n) HDPTX_REG(n, 0300, 062d) =20 /* CMN_REG(0008) */ #define OVRD_LCPLL_EN_MASK BIT(7) @@ -411,7 +411,7 @@ struct rk_hdptx_phy { unsigned int lanes; }; =20 -static const struct ropll_config ropll_tmds_cfg[] =3D { +static const struct ropll_config rk_hdptx_tmds_ropll_cfg[] =3D { { 594000000ULL, 124, 124, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, { 371250000ULL, 155, 155, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, @@ -456,7 +456,7 @@ static const struct ropll_config ropll_tmds_cfg[] =3D { 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, }; =20 -static const struct reg_sequence rk_hdtpx_common_cmn_init_seq[] =3D { +static const struct reg_sequence rk_hdptx_common_cmn_init_seq[] =3D { REG_SEQ0(CMN_REG(0009), 0x0c), REG_SEQ0(CMN_REG(000a), 0x83), REG_SEQ0(CMN_REG(000b), 0x06), @@ -546,7 +546,7 @@ static const struct reg_sequence rk_hdtpx_common_cmn_in= it_seq[] =3D { REG_SEQ0(CMN_REG(009b), 0x10), }; =20 -static const struct reg_sequence rk_hdtpx_tmds_cmn_init_seq[] =3D { +static const struct reg_sequence rk_hdptx_tmds_cmn_init_seq[] =3D { REG_SEQ0(CMN_REG(0008), 0x00), REG_SEQ0(CMN_REG(0011), 0x01), REG_SEQ0(CMN_REG(0017), 0x20), @@ -588,14 +588,14 @@ static const struct reg_sequence rk_hdtpx_tmds_cmn_in= it_seq[] =3D { REG_SEQ0(CMN_REG(009b), 0x00), }; =20 -static const struct reg_sequence rk_hdtpx_common_sb_init_seq[] =3D { +static const struct reg_sequence rk_hdptx_common_sb_init_seq[] =3D { REG_SEQ0(SB_REG(0114), 0x00), REG_SEQ0(SB_REG(0115), 0x00), REG_SEQ0(SB_REG(0116), 0x00), REG_SEQ0(SB_REG(0117), 0x00), }; =20 -static const struct reg_sequence rk_hdtpx_tmds_lntop_highbr_seq[] =3D { +static const struct reg_sequence rk_hdptx_tmds_lntop_highbr_seq[] =3D { REG_SEQ0(LNTOP_REG(0201), 0x00), REG_SEQ0(LNTOP_REG(0202), 0x00), REG_SEQ0(LNTOP_REG(0203), 0x0f), @@ -603,7 +603,7 @@ static const struct reg_sequence rk_hdtpx_tmds_lntop_hi= ghbr_seq[] =3D { REG_SEQ0(LNTOP_REG(0205), 0xff), }; =20 -static const struct reg_sequence rk_hdtpx_tmds_lntop_lowbr_seq[] =3D { +static const struct reg_sequence rk_hdptx_tmds_lntop_lowbr_seq[] =3D { REG_SEQ0(LNTOP_REG(0201), 0x07), REG_SEQ0(LNTOP_REG(0202), 0xc1), REG_SEQ0(LNTOP_REG(0203), 0xf0), @@ -611,7 +611,7 @@ static const struct reg_sequence rk_hdtpx_tmds_lntop_lo= wbr_seq[] =3D { REG_SEQ0(LNTOP_REG(0205), 0x1f), }; =20 -static const struct reg_sequence rk_hdtpx_common_lane_init_seq[] =3D { +static const struct reg_sequence rk_hdptx_common_lane_init_seq[] =3D { REG_SEQ0(LANE_REG(0303), 0x0c), REG_SEQ0(LANE_REG(0307), 0x20), REG_SEQ0(LANE_REG(030a), 0x17), @@ -666,7 +666,7 @@ static const struct reg_sequence rk_hdtpx_common_lane_i= nit_seq[] =3D { REG_SEQ0(LANE_REG(0620), 0xa0), }; =20 -static const struct reg_sequence rk_hdtpx_tmds_lane_init_seq[] =3D { +static const struct reg_sequence rk_hdptx_tmds_lane_init_seq[] =3D { REG_SEQ0(LANE_REG(0312), 0x00), REG_SEQ0(LANE_REG(0412), 0x00), REG_SEQ0(LANE_REG(0512), 0x00), @@ -971,7 +971,7 @@ static bool rk_hdptx_phy_clk_pll_calc(unsigned long lon= g rate, return true; } =20 -static int rk_hdptx_ropll_tmds_cmn_config(struct rk_hdptx_phy *hdptx) +static int rk_hdptx_tmds_ropll_cmn_config(struct rk_hdptx_phy *hdptx) { const struct ropll_config *cfg =3D NULL; struct ropll_config rc =3D {0}; @@ -980,9 +980,9 @@ static int rk_hdptx_ropll_tmds_cmn_config(struct rk_hdp= tx_phy *hdptx) if (!hdptx->hdmi_cfg.tmds_char_rate) return 0; =20 - for (i =3D 0; i < ARRAY_SIZE(ropll_tmds_cfg); i++) - if (hdptx->hdmi_cfg.tmds_char_rate =3D=3D ropll_tmds_cfg[i].rate) { - cfg =3D &ropll_tmds_cfg[i]; + for (i =3D 0; i < ARRAY_SIZE(rk_hdptx_tmds_ropll_cfg); i++) + if (hdptx->hdmi_cfg.tmds_char_rate =3D=3D rk_hdptx_tmds_ropll_cfg[i].rat= e) { + cfg =3D &rk_hdptx_tmds_ropll_cfg[i]; break; } =20 @@ -1002,8 +1002,8 @@ static int rk_hdptx_ropll_tmds_cmn_config(struct rk_h= dptx_phy *hdptx) =20 rk_hdptx_pre_power_up(hdptx); =20 - rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_common_cmn_init_seq); - rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_tmds_cmn_init_seq); + rk_hdptx_multi_reg_write(hdptx, rk_hdptx_common_cmn_init_seq); + rk_hdptx_multi_reg_write(hdptx, rk_hdptx_tmds_cmn_init_seq); =20 regmap_write(hdptx->regmap, CMN_REG(0051), cfg->pms_mdiv); regmap_write(hdptx->regmap, CMN_REG(0055), cfg->pms_mdiv_afc); @@ -1045,25 +1045,25 @@ static int rk_hdptx_ropll_tmds_cmn_config(struct rk= _hdptx_phy *hdptx) return ret; } =20 -static int rk_hdptx_ropll_tmds_mode_config(struct rk_hdptx_phy *hdptx) +static int rk_hdptx_tmds_ropll_mode_config(struct rk_hdptx_phy *hdptx) { - rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_common_sb_init_seq); + rk_hdptx_multi_reg_write(hdptx, rk_hdptx_common_sb_init_seq); =20 regmap_write(hdptx->regmap, LNTOP_REG(0200), 0x06); =20 if (hdptx->hdmi_cfg.tmds_char_rate > HDMI14_MAX_RATE) { /* For 1/40 bitrate clk */ - rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_tmds_lntop_highbr_seq); + rk_hdptx_multi_reg_write(hdptx, rk_hdptx_tmds_lntop_highbr_seq); } else { /* For 1/10 bitrate clk */ - rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_tmds_lntop_lowbr_seq); + rk_hdptx_multi_reg_write(hdptx, rk_hdptx_tmds_lntop_lowbr_seq); } =20 regmap_write(hdptx->regmap, LNTOP_REG(0206), 0x07); regmap_write(hdptx->regmap, LNTOP_REG(0207), 0x0f); =20 - rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_common_lane_init_seq); - rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_tmds_lane_init_seq); + rk_hdptx_multi_reg_write(hdptx, rk_hdptx_common_lane_init_seq); + rk_hdptx_multi_reg_write(hdptx, rk_hdptx_tmds_lane_init_seq); =20 return rk_hdptx_post_enable_lane(hdptx); } @@ -1122,7 +1122,7 @@ static int rk_hdptx_phy_consumer_get(struct rk_hdptx_= phy *hdptx) if (mode =3D=3D PHY_MODE_DP) { rk_hdptx_dp_reset(hdptx); } else { - ret =3D rk_hdptx_ropll_tmds_cmn_config(hdptx); + ret =3D rk_hdptx_tmds_ropll_cmn_config(hdptx); if (ret) goto dec_usage; } @@ -1469,7 +1469,7 @@ static int rk_hdptx_phy_power_on(struct phy *phy) regmap_write(hdptx->grf, GRF_HDPTX_CON0, HDPTX_MODE_SEL << 16 | FIELD_PREP(HDPTX_MODE_SEL, 0x0)); =20 - ret =3D rk_hdptx_ropll_tmds_mode_config(hdptx); + ret =3D rk_hdptx_tmds_ropll_mode_config(hdptx); if (ret) rk_hdptx_phy_consumer_put(hdptx, true); } @@ -1492,11 +1492,11 @@ static int rk_hdptx_phy_verify_hdmi_config(struct r= k_hdptx_phy *hdptx, if (!hdmi->tmds_char_rate || hdmi->tmds_char_rate > HDMI20_MAX_RATE) return -EINVAL; =20 - for (i =3D 0; i < ARRAY_SIZE(ropll_tmds_cfg); i++) - if (hdmi->tmds_char_rate =3D=3D ropll_tmds_cfg[i].rate) + for (i =3D 0; i < ARRAY_SIZE(rk_hdptx_tmds_ropll_cfg); i++) + if (hdmi->tmds_char_rate =3D=3D rk_hdptx_tmds_ropll_cfg[i].rate) break; =20 - if (i =3D=3D ARRAY_SIZE(ropll_tmds_cfg) && + if (i =3D=3D ARRAY_SIZE(rk_hdptx_tmds_ropll_cfg) && !rk_hdptx_phy_clk_pll_calc(hdmi->tmds_char_rate, NULL)) return -EINVAL; =20 @@ -1921,7 +1921,7 @@ static int rk_hdptx_phy_clk_set_rate(struct clk_hw *h= w, unsigned long rate, * while the latter being executed only once, i.e. when clock remains * in the prepared state during rate changes. */ - return rk_hdptx_ropll_tmds_cmn_config(hdptx); + return rk_hdptx_tmds_ropll_cmn_config(hdptx); } =20 static const struct clk_ops hdptx_phy_clk_ops =3D { --=20 2.50.1