From nobody Sat Oct 4 09:40:48 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 72D6A274B50 for ; Mon, 18 Aug 2025 18:59:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755543565; cv=none; b=GsARGLREav3FxniMnPv1ZrqfGDKkhL6w40SoNDAuy1LGfmfK8A8Sy6xQW7CSKULa2z24un6abz3qZ2UMszR8IHoVWzDqn1qXQ+yL+l3I3CUyeufebwsqKFhu4Aqujqfi4w7qzzLkwoAP7VZQrrN/CfOptKD7RE64Ob/hPUF1KnA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755543565; c=relaxed/simple; bh=z2OM3+rx83A3V9ym7RSXQfddzzsMXYLBw5vA4FCqwJo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=YOq8rDp/1UwqOw0VV4ukDbOMdPT3vB6cw3DHjg7RT6rERBTDI8exdwrHJEk92ehuUfILZqyjmLugIepqyBZCtx2v0JHlJR8VCa/ZTLGdJVzi1F0x3BVfZtqYIzEIHHdlp1DdSNTStsKuySdghJzItvSqubOjlB8aJ+TA4hDAlpU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=af9MmNf8; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="af9MmNf8" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1755543561; bh=z2OM3+rx83A3V9ym7RSXQfddzzsMXYLBw5vA4FCqwJo=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=af9MmNf8KQjzKABMu+lGlhCMKVHVynoRq+6yr5SnXN0maz6/5YCoOxXGcSQj+P38k nnEGNGt8iLYNu6TacIIA8cWBq8NPoFKYkgoraHgFxgkVvCyPJeSjTkYjgVn0adRikJ 24PsqwDXzXN3EY42mL8R7tk/vRr4P7Lb2uIRCtODgsCCnC8oNHrnhASXwP7EU10oC9 MpiKmZsWpUBixkmvL1rX0VibFru6jaudhi5Zf2Nd2a6Iao0fc+CAWikdi3nQzhxelZ tpl2GxCO5LIOZFmAxHr1QRMCSEQ3ktNeV0mf/eZAB9gvJfOzKDrUvTOWum8snNcQNF 9VFrfu999qWYQ== Received: from localhost (unknown [82.79.138.60]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (prime256v1) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by bali.collaboradmins.com (Postfix) with UTF8SMTPSA id 7A12017E090E; Mon, 18 Aug 2025 20:59:21 +0200 (CEST) From: Cristian Ciocaltea Date: Mon, 18 Aug 2025 21:59:02 +0300 Subject: [PATCH v3 02/14] phy: rockchip: samsung-hdptx: Fix reported clock rate in high bpc mode Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250818-phy-hdptx-frl-v3-2-c79997d8bb2b@collabora.com> References: <20250818-phy-hdptx-frl-v3-0-c79997d8bb2b@collabora.com> In-Reply-To: <20250818-phy-hdptx-frl-v3-0-c79997d8bb2b@collabora.com> To: Vinod Koul , Kishon Vijay Abraham I , Heiko Stuebner , Algea Cao , Dmitry Baryshkov Cc: kernel@collabora.com, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, Andy Yan X-Mailer: b4 0.14.2 When making use of the clock provider functionality, the output clock does normally match the TMDS character rate, which is what the PHY PLL gets configured to. However, this is only applicable for default color depth of 8 bpc. For higher depths, the output clock is further divided by the hardware according to the formula: output_clock_rate =3D tmds_char_rate * 8 / bpc Since the existence of the clock divider wasn't taken into account when support for high bpc has been introduced, make the necessary adjustments to report the correct clock rate. Fixes: 9d0ec51d7c22 ("phy: rockchip: samsung-hdptx: Add high color depth ma= nagement") Reported-by: Andy Yan Signed-off-by: Cristian Ciocaltea --- drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/ph= y/rockchip/phy-rockchip-samsung-hdptx.c index 79db57ee90d1487b51f4ddadde870a275dd7b17b..8adf6e84fc0b762a7a604245960= 1c3271572de8e 100644 --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c @@ -1038,7 +1038,8 @@ static int rk_hdptx_ropll_tmds_cmn_config(struct rk_h= dptx_phy *hdptx) =20 ret =3D rk_hdptx_post_enable_pll(hdptx); if (!ret) - hdptx->hw_rate =3D hdptx->hdmi_cfg.tmds_char_rate; + hdptx->hw_rate =3D DIV_ROUND_CLOSEST_ULL(hdptx->hdmi_cfg.tmds_char_rate = * 8, + hdptx->hdmi_cfg.bpc); =20 return ret; } @@ -1896,19 +1897,20 @@ static long rk_hdptx_phy_clk_round_rate(struct clk_= hw *hw, unsigned long rate, * hence ensure rk_hdptx_phy_clk_set_rate() won't be invoked with * a different rate argument. */ - return hdptx->hdmi_cfg.tmds_char_rate; + return DIV_ROUND_CLOSEST_ULL(hdptx->hdmi_cfg.tmds_char_rate * 8, hdptx->h= dmi_cfg.bpc); } =20 static int rk_hdptx_phy_clk_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { struct rk_hdptx_phy *hdptx =3D to_rk_hdptx_phy(hw); + unsigned long long tmds_rate =3D DIV_ROUND_CLOSEST_ULL(rate * hdptx->hdmi= _cfg.bpc, 8); =20 /* Revert any unlikely TMDS char rate change since round_rate() */ - if (hdptx->hdmi_cfg.tmds_char_rate !=3D rate) { - dev_warn(hdptx->dev, "Reverting unexpected rate change from %lu to %llu\= n", - rate, hdptx->hdmi_cfg.tmds_char_rate); - hdptx->hdmi_cfg.tmds_char_rate =3D rate; + if (hdptx->hdmi_cfg.tmds_char_rate !=3D tmds_rate) { + dev_warn(hdptx->dev, "Reverting unexpected rate change from %llu to %llu= \n", + tmds_rate, hdptx->hdmi_cfg.tmds_char_rate); + hdptx->hdmi_cfg.tmds_char_rate =3D tmds_rate; } =20 /* --=20 2.50.1