From nobody Sat Oct 4 09:42:06 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CAC4D338F2F for ; Mon, 18 Aug 2025 18:59:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755543572; cv=none; b=XOokS5I/WgPlZcH1yGOrUEAhEa/gP1Vh1LnsUoow/DXOoRHM/fWWX4DuWNLzl5/MMNiysu1LUgMJAg1sDVkOUQoZDIU0SqTmkW1BTx81SeDajoGrIKp1c9rfawIt7J8QB5iceqTyLT4NWLzKT4J4/nKGKe7ezYGI5g02rAx1mZY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755543572; c=relaxed/simple; bh=jnnCmyETnWIGICs1yL1qijh+vsxC5P+LXQTyy/MIZRM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=AzpAPONKSEf01U46pGULMgwoXgBGrLXOFGXgIK6WMpCRzXAM5S/27S23a52Bda6W/vtZ/9DlhFsPVl0990WugQ7XpcLxzv+9v5kYk7vBfjCCQCXa+kR2pu07oLBgsK/1LF7LDqhShnJWmDkyGCAgEVhOsmdvdezLHK+SQoAtMNM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=OYiwSzFf; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="OYiwSzFf" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1755543569; bh=jnnCmyETnWIGICs1yL1qijh+vsxC5P+LXQTyy/MIZRM=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=OYiwSzFf0LneLP2rVQN+un1zBllUsll+DI9jFRrjLuRml0XVJojY1zCTVwXuLcW1Q ZG0c2bn92BTafQYj2xI1sQuyO/WaLAvccte2RfaDwW9pKMqQouXj9ZBh824ZDkNwUm OmpreJU+wdIGLzlBzBCl1fgxqbAGH2+OzgshWbMVlKSc4oWsDU2kX1juj4V3Fss6pp iiiWNs1mTs5e4dPXblIzpwdKOq4NwLqPlTbiAO0QsGCBS7pn55nWmYiuuiFeDf/qQv xum5lT/hjuYN+EsTYX1EhTC/Bep5hSdX/g5ly1GOlr/9KJxydgLYzgQMQQnDKxIY8t a7vyPhsxwTtvA== Received: from localhost (unknown [82.79.138.60]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (prime256v1) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by bali.collaboradmins.com (Postfix) with UTF8SMTPSA id E38D017E0154; Mon, 18 Aug 2025 20:59:28 +0200 (CEST) From: Cristian Ciocaltea Date: Mon, 18 Aug 2025 21:59:11 +0300 Subject: [PATCH v3 11/14] phy: rockchip: samsung-hdptx: Drop hw_rate driver data Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250818-phy-hdptx-frl-v3-11-c79997d8bb2b@collabora.com> References: <20250818-phy-hdptx-frl-v3-0-c79997d8bb2b@collabora.com> In-Reply-To: <20250818-phy-hdptx-frl-v3-0-c79997d8bb2b@collabora.com> To: Vinod Koul , Kishon Vijay Abraham I , Heiko Stuebner , Algea Cao , Dmitry Baryshkov Cc: kernel@collabora.com, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.14.2 The ->hw_rate member of struct rk_hdptx_phy was mainly used to keep track of the clock rate programmed in hardware and support implementing the ->recalc_rate() callback in hdptx_phy_clk_ops. Computing the clock rate from the actual PHY PLL configuration seems to work reliably, hence remove the now redundant struct member. Signed-off-by: Cristian Ciocaltea --- drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 13 ++----------- 1 file changed, 2 insertions(+), 11 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/ph= y/rockchip/phy-rockchip-samsung-hdptx.c index 6e2443f78968948b84e4261e33761fe0d189553b..4195387108d8786c2b7cabb6d2f= 3c07315fefd88 100644 --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c @@ -401,7 +401,6 @@ struct rk_hdptx_phy { =20 /* clk provider */ struct clk_hw hw; - unsigned long hw_rate; bool restrict_rate_change; =20 atomic_t usage_count; @@ -964,7 +963,7 @@ static int rk_hdptx_tmds_ropll_cmn_config(struct rk_hdp= tx_phy *hdptx) { const struct ropll_config *cfg =3D NULL; struct ropll_config rc =3D {0}; - int ret, i; + int i; =20 if (!hdptx->hdmi_cfg.tmds_char_rate) return 0; @@ -1026,12 +1025,7 @@ static int rk_hdptx_tmds_ropll_cmn_config(struct rk_= hdptx_phy *hdptx) regmap_update_bits(hdptx->regmap, CMN_REG(0086), PLL_PCG_CLK_EN_MASK, FIELD_PREP(PLL_PCG_CLK_EN_MASK, 0x1)); =20 - ret =3D rk_hdptx_post_enable_pll(hdptx); - if (!ret) - hdptx->hw_rate =3D DIV_ROUND_CLOSEST_ULL(hdptx->hdmi_cfg.tmds_char_rate = * 8, - hdptx->hdmi_cfg.bpc); - - return ret; + return rk_hdptx_post_enable_pll(hdptx); } =20 static int rk_hdptx_tmds_ropll_mode_config(struct rk_hdptx_phy *hdptx) @@ -1936,9 +1930,6 @@ static unsigned long rk_hdptx_phy_clk_recalc_rate(str= uct clk_hw *hw, u64 rate; int ret; =20 - if (hdptx->hw_rate) - return hdptx->hw_rate; - ret =3D regmap_read(hdptx->grf, GRF_HDPTX_CON0, &status); if (ret || !(status & HDPTX_I_PLL_EN)) return 0; --=20 2.50.1