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The location of this group of registers is indicated by the MISCOFF register. Each capability has a capability ID to determine which functionality is supported and each capability will point to the next capability supported. Add a basic function to read those capabilities offsets. Signed-off-by: Vivek Pernamitta Signed-off-by: Krishna Chaitanya Chundru --- This patch is required by MHI TSC time sync also, for that reason sending this seperately. Changes from v4: - Removed the le32_to_cpu conversions as these will be taken care by the readl API's (Mani) --- drivers/bus/mhi/common.h | 13 +++++++++++++ drivers/bus/mhi/host/init.c | 32 ++++++++++++++++++++++++++++++++ 2 files changed, 45 insertions(+) diff --git a/drivers/bus/mhi/common.h b/drivers/bus/mhi/common.h index dda340aaed95a5573a2ec776ca712e11a1ed0b52..58f27c6ba63e3e6fa28ca48d6d1= 065684ed6e1dd 100644 --- a/drivers/bus/mhi/common.h +++ b/drivers/bus/mhi/common.h @@ -16,6 +16,7 @@ #define MHICFG 0x10 #define CHDBOFF 0x18 #define ERDBOFF 0x20 +#define MISCOFF 0x24 #define BHIOFF 0x28 #define BHIEOFF 0x2c #define DEBUGOFF 0x30 @@ -113,6 +114,9 @@ #define MHISTATUS_MHISTATE_MASK GENMASK(15, 8) #define MHISTATUS_SYSERR_MASK BIT(2) #define MHISTATUS_READY_MASK BIT(0) +#define MISC_CAP_MASK GENMASK(31, 0) +#define CAP_CAPID_MASK GENMASK(31, 24) +#define CAP_NEXT_CAP_MASK GENMASK(23, 12) =20 /* Command Ring Element macros */ /* No operation command */ @@ -204,6 +208,15 @@ #define MHI_RSCTRE_DATA_DWORD1 cpu_to_le32(FIELD_PREP(GENMASK(23, 16), \ MHI_PKT_TYPE_COALESCING)) =20 +enum mhi_capability_type { + MHI_CAP_ID_INTX =3D 0x1, + MHI_CAP_ID_TIME_SYNC =3D 0x2, + MHI_CAP_ID_BW_SCALE =3D 0x3, + MHI_CAP_ID_TSC_TIME_SYNC =3D 0x4, + MHI_CAP_ID_MAX_TRB_LEN =3D 0x5, + MHI_CAP_ID_MAX, +}; + enum mhi_pkt_type { MHI_PKT_TYPE_INVALID =3D 0x0, MHI_PKT_TYPE_NOOP_CMD =3D 0x1, diff --git a/drivers/bus/mhi/host/init.c b/drivers/bus/mhi/host/init.c index 7f72aab38ce92fea9e875e65c69d9a4714ecbc13..b5f23336eb6afe249c07932bc41= 82fafdf1f2a19 100644 --- a/drivers/bus/mhi/host/init.c +++ b/drivers/bus/mhi/host/init.c @@ -467,6 +467,38 @@ static int mhi_init_dev_ctxt(struct mhi_controller *mh= i_cntrl) return ret; } =20 +static int mhi_find_capability(struct mhi_controller *mhi_cntrl, u32 capab= ility, u32 *offset) +{ + u32 val, cur_cap, next_offset; + int ret; + + /* Get the first supported capability offset */ + ret =3D mhi_read_reg_field(mhi_cntrl, mhi_cntrl->regs, MISCOFF, MISC_CAP_= MASK, offset); + if (ret) + return ret; + + do { + if (*offset >=3D mhi_cntrl->reg_len) + return -ENXIO; + + ret =3D mhi_read_reg(mhi_cntrl, mhi_cntrl->regs, *offset, &val); + if (ret) + return ret; + + cur_cap =3D FIELD_GET(CAP_CAPID_MASK, val); + next_offset =3D FIELD_GET(CAP_NEXT_CAP_MASK, val); + if (cur_cap >=3D MHI_CAP_ID_MAX) + return -ENXIO; + + if (cur_cap =3D=3D capability) + return 0; + + *offset =3D next_offset; + } while (next_offset); + + return -ENXIO; +} + int mhi_init_mmio(struct mhi_controller *mhi_cntrl) { u32 val; --- base-commit: c17b750b3ad9f45f2b6f7e6f7f4679844244f0b9 change-id: 20250818-mhi_cap-3b2bb05663f4 Best regards, --=20 Krishna Chaitanya Chundru