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QCS615 has a DP port, and DP support will be added in a later patch. Reviewed-by: Dmitry Baryshkov Signed-off-by: Li Liu Signed-off-by: Fange Zhang --- arch/arm64/boot/dts/qcom/sm6150.dtsi | 182 +++++++++++++++++++++++++++++++= +++- 1 file changed, 180 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm6150.dtsi b/arch/arm64/boot/dts/qco= m/sm6150.dtsi index 50cd9275e4028eb8f689eae215bf47a9e06d4cfb..8c60875b5953f031fac8557d047= d1adf3883db29 100644 --- a/arch/arm64/boot/dts/qcom/sm6150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6150.dtsi @@ -3,6 +3,7 @@ * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserve= d. */ =20 +#include #include #include #include @@ -3576,14 +3577,191 @@ camcc: clock-controller@ad00000 { #power-domain-cells =3D <1>; }; =20 + mdss: display-subsystem@ae00000 { + compatible =3D "qcom,sm6150-mdss"; + reg =3D <0x0 0x0ae00000 0x0 0x1000>; + reg-names =3D "mdss"; + + interconnects =3D <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "mdp0-mem", + "cpu-cfg"; + + power-domains =3D <&dispcc MDSS_CORE_GDSC>; + + clocks =3D <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + + interrupts =3D ; + interrupt-controller; + #interrupt-cells =3D <1>; + + iommus =3D <&apps_smmu 0x800 0x0>; + + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + status =3D "disabled"; + + mdss_mdp: display-controller@ae01000 { + compatible =3D "qcom,sm6150-dpu"; + reg =3D <0x0 0x0ae01000 0x0 0x8f000>, + <0x0 0x0aeb0000 0x0 0x2008>; + reg-names =3D "mdp", + "vbif"; + + clocks =3D <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names =3D "iface", + "bus", + "core", + "vsync"; + + operating-points-v2 =3D <&mdp_opp_table>; + power-domains =3D <&rpmhpd RPMHPD_CX>; + + interrupts-extended =3D <&mdss 0>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + dpu_intf0_out: endpoint { + }; + }; + + port@1 { + reg =3D <1>; + + dpu_intf1_out: endpoint { + remote-endpoint =3D <&mdss_dsi0_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-192000000 { + opp-hz =3D /bits/ 64 <192000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-256000000 { + opp-hz =3D /bits/ 64 <256000000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + + opp-307200000 { + opp-hz =3D /bits/ 64 <307200000>; + required-opps =3D <&rpmhpd_opp_nom>; + }; + }; + }; + + mdss_dsi0: dsi@ae94000 { + compatible =3D "qcom,sm6150-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg =3D <0x0 0x0ae94000 0x0 0x400>; + reg-names =3D "dsi_ctrl"; + + interrupts-extended =3D <&mdss 4>; + + clocks =3D <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names =3D "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks =3D <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents =3D <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; + + operating-points-v2 =3D <&dsi0_opp_table>; + power-domains =3D <&rpmhpd RPMHPD_CX>; + + phys =3D <&mdss_dsi0_phy>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + + dsi0_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-164000000 { + opp-hz =3D /bits/ 64 <164000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + }; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + mdss_dsi0_in: endpoint { + remote-endpoint =3D <&dpu_intf1_out>; + }; + }; + + port@1 { + reg =3D <1>; + + mdss_dsi0_out: endpoint { + }; + }; + }; + }; + + mdss_dsi0_phy: phy@ae94400 { + compatible =3D "qcom,sm6150-dsi-phy-14nm"; + reg =3D <0x0 0x0ae94400 0x0 0x100>, + <0x0 0x0ae94500 0x0 0x300>, + <0x0 0x0ae94800 0x0 0x124>; + reg-names =3D "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells =3D <1>; + #phy-cells =3D <0>; + + clocks =3D <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "iface", + "ref"; + + status =3D "disabled"; + }; + }; + dispcc: clock-controller@af00000 { compatible =3D "qcom,qcs615-dispcc"; reg =3D <0 0x0af00000 0 0x20000>; =20 clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, - <0>, - <0>, + <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, <0>, <0>, <0>; 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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2446ca9cffdsm67505765ad.5.2025.08.17.21.39.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Aug 2025 21:40:00 -0700 (PDT) From: Fange Zhang Date: Mon, 18 Aug 2025 12:39:21 +0800 Subject: [PATCH v6 2/2] arm64: dts: qcom: Add display support for QCS615 RIDE board Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250818-add-display-support-for-qcs615-platform-v6-2-62aad5138a78@oss.qualcomm.com> References: <20250818-add-display-support-for-qcs615-platform-v6-0-62aad5138a78@oss.qualcomm.com> In-Reply-To: <20250818-add-display-support-for-qcs615-platform-v6-0-62aad5138a78@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Li Liu , Fange Zhang , dmitry.baryshkov@oss.qualcomm.com, tingwei.zhang@oss.qualcomm.com, xiangxu.yin@oss.qualcomm.com X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1755491988; l=2780; i=fange.zhang@oss.qualcomm.com; s=20250714; h=from:subject:message-id; bh=Uhf3pCMvh2O5TroEbSoOdeJOJk/Am8Y7U0jj7j2dFhM=; b=GuhRimwzw/dI5bIhQZRw/gvFbHbSz9WhzsZicnCG5AjH16nX1PZdF4+DNSStskrwBL/U2ORiW nTNwy3l4HuTCmuhDCZi/0tZC2MXAhUcwd6l6cO4U4MlM71nhxmvJz/d X-Developer-Key: i=fange.zhang@oss.qualcomm.com; a=ed25519; pk=tn190A7bjF3/EyH7AYy/eNzPoS9lwXGznYamlMv6TE0= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODE2MDAzMyBTYWx0ZWRfX4e6YJiROT580 33qSpA06ZG5jxYd9Fwe9WcRLNTIEeo+Wda2FHUGsNBihEAxQjTiWEGGvP/ExNCEGltOfsSrLQ0M RlJzJ6881m3DQ7fA2Zij5LwKrVVAHHQH4Pgm+b1Hrd6FECFj/BWke1NaxUCcXxXWTp/OlKrXWp5 wifkYzx4JRD60zqBB5eW2KhyHKsHzTOjOdNRcJH73+s8H2NKm/qUpgG4449AW/0lyf4jlT7JSTo rr/C7/MqsbiZRtBwm3mvcrLCtEA/uTHPGlipglbBw+xfAhdb6b+pMNNdYuBLIHtwQL3aEVtEO1T x8RyCBIiJZPqK145UOX+Je9IeELanZpjNupuHJtuT0tPX7iYeW35NDrJITRAY5bgj3ZMp6nh8nk ebD42Xmo X-Authority-Analysis: v=2.4 cv=c4mrQQ9l c=1 sm=1 tr=0 ts=68a2aea2 cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=2OwXVqhp2XgA:10 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=cjmIRqugeGUkMfCPaF0A:9 a=QEXdDO2ut3YA:10 a=1OuFwYUASf3TG4hYMiVC:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: N321B2yq2W9mkxBg36Pr01UVOIhI7byQ X-Proofpoint-ORIG-GUID: N321B2yq2W9mkxBg36Pr01UVOIhI7byQ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-18_02,2025-08-14_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 spamscore=0 priorityscore=1501 adultscore=0 impostorscore=0 bulkscore=0 phishscore=0 malwarescore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508160033 From: Li Liu Add display MDSS and DSI configuration for QCS615 RIDE board. QCS615 has a DP port, and DP support will be added in a later patch. Reviewed-by: Dmitry Baryshkov Signed-off-by: Li Liu Signed-off-by: Fange Zhang --- arch/arm64/boot/dts/qcom/qcs615-ride.dts | 90 ++++++++++++++++++++++++++++= ++++ 1 file changed, 90 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts= /qcom/qcs615-ride.dts index 59582d3dc4c49828ef4a0d22a1cbaba715c7ce8c..39c757b66f47579d9bc7cc5c4d7= 03f7af4434df4 100644 --- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts @@ -39,6 +39,18 @@ xo_board_clk: xo-board-clk { }; }; =20 + dp-dsi0-connector { + compatible =3D "dp-connector"; + label =3D "DSI0"; + type =3D "mini"; + + port { + dp_dsi0_connector_in: endpoint { + remote-endpoint =3D <&dsi2dp_bridge_out>; + }; + }; + }; + vreg_conn_1p8: regulator-conn-1p8 { compatible =3D "regulator-fixed"; regulator-name =3D "vreg_conn_1p8"; @@ -294,6 +306,84 @@ &gcc { <&sleep_clk>; }; =20 +&i2c2 { + clock-frequency =3D <400000>; + status =3D "okay"; + + io_expander: gpio@3e { + compatible =3D "semtech,sx1509q"; + reg =3D <0x3e>; + interrupts-extended =3D <&tlmm 58 IRQ_TYPE_EDGE_FALLING>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + semtech,probe-reset; + }; + + i2c-mux@77 { + compatible =3D "nxp,pca9542"; + reg =3D <0x77>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + i2c@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + bridge@58 { + compatible =3D "analogix,anx7625"; + reg =3D <0x58>; + interrupts-extended =3D <&io_expander 0 IRQ_TYPE_EDGE_FALLING>; + enable-gpios =3D <&tlmm 4 GPIO_ACTIVE_HIGH>; + reset-gpios =3D <&tlmm 5 GPIO_ACTIVE_HIGH>; + wakeup-source; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + dsi2dp_bridge_in: endpoint { + remote-endpoint =3D <&mdss_dsi0_out>; + }; + }; + + port@1 { + reg =3D <1>; + + dsi2dp_bridge_out: endpoint { + remote-endpoint =3D <&dp_dsi0_connector_in>; + }; + }; + }; + }; + }; + }; +}; + +&mdss { + status =3D "okay"; +}; + +&mdss_dsi0 { + vdda-supply =3D <&vreg_l11a>; + status =3D "okay"; +}; + +&mdss_dsi0_out { + remote-endpoint =3D <&dsi2dp_bridge_in>; + data-lanes =3D <0 1 2 3>; +}; + +&mdss_dsi0_phy { + vdds-supply =3D <&vreg_l5a>; + status =3D "okay"; +}; + &pcie { perst-gpios =3D <&tlmm 101 GPIO_ACTIVE_LOW>; wake-gpios =3D <&tlmm 100 GPIO_ACTIVE_HIGH>; --=20 2.34.1