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[31.53.6.191]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-45a1c6cfed5sm129938485e9.7.2025.08.17.07.30.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Aug 2025 07:30:27 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Geert Uytterhoeven , Linus Walleij Cc: Biju Das , Lad Prabhakar , linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Biju Das Subject: [PATCH v2 2/2] pinctrl: renesas: rzg2l: Drop the unnecessary pin configurations Date: Sun, 17 Aug 2025 15:30:20 +0100 Message-ID: <20250817143024.165471-3-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250817143024.165471-1-biju.das.jz@bp.renesas.com> References: <20250817143024.165471-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das There is no need to reconfigure the pin if the pin's configuration values are same as the reset values. E.g.: PS0 pin configuration for NMI function is PMC =3D 1 and PFC =3D 0 and is same as that of reset values. Currently t= he code is first setting it to GPIO HI-Z state and then again reconfiguring to NMI function leading to spurious IRQ. Drop the unnecessary pin configurations from the driver. Signed-off-by: Biju Das --- v1->v2: * Updated commit header and description. * Added check in rzg2l_pinctrl_set_pfc_mode() to avoid unnecessary configuration * Updated rzg2l_pinctrl_pm_setup_pfc() to make changes minimal. --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 22 ++++++++++++++++------ 1 file changed, 16 insertions(+), 6 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/rene= sas/pinctrl-rzg2l.c index 2b5d16594bb7..8422a5429ca3 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -539,7 +539,11 @@ static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pi= nctrl *pctrl, u8 pin, u8 off, u8 func) { unsigned long flags; - u32 reg; + u32 reg, pfc; + + pfc =3D readl(pctrl->base + PFC(off)); + if (((pfc >> (pin * 4)) & PFC_MASK) =3D=3D func) + return; =20 spin_lock_irqsave(&pctrl->lock, flags); =20 @@ -555,9 +559,8 @@ static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pin= ctrl *pctrl, writeb(reg & ~BIT(pin), pctrl->base + PMC(off)); =20 /* Select Pin function mode with PFC register */ - reg =3D readl(pctrl->base + PFC(off)); - reg &=3D ~(PFC_MASK << (pin * 4)); - writel(reg | (func << (pin * 4)), pctrl->base + PFC(off)); + pfc &=3D ~(PFC_MASK << (pin * 4)); + writel(pfc | (func << (pin * 4)), pctrl->base + PFC(off)); =20 /* Switch to Peripheral pin function with PMC register */ reg =3D readb(pctrl->base + PMC(off)); @@ -3103,11 +3106,18 @@ static void rzg2l_pinctrl_pm_setup_pfc(struct rzg2l= _pinctrl *pctrl) pm =3D readw(pctrl->base + PM(off)); for_each_set_bit(pin, &pinmap, max_pin) { struct rzg2l_pinctrl_reg_cache *cache =3D pctrl->cache; + u32 pfc_val, pfc_mask; =20 /* Nothing to do if PFC was not configured before. */ if (!(cache->pmc[port] & BIT(pin))) continue; =20 + pfc_val =3D readl(pctrl->base + PFC(off)); + pfc_mask =3D PFC_MASK << (pin * 4); + /* Nothing to do if reset value of the pin is same as cached value */ + if ((cache->pfc[port] & pfc_mask) =3D=3D (pfc_val & pfc_mask)) + continue; + /* Set pin to 'Non-use (Hi-Z input protection)' */ pm &=3D ~(PM_MASK << (pin * 2)); writew(pm, pctrl->base + PM(off)); @@ -3117,8 +3127,8 @@ static void rzg2l_pinctrl_pm_setup_pfc(struct rzg2l_p= inctrl *pctrl) writeb(pmc, pctrl->base + PMC(off)); =20 /* Select Pin function mode. */ - pfc &=3D ~(PFC_MASK << (pin * 4)); - pfc |=3D (cache->pfc[port] & (PFC_MASK << (pin * 4))); + pfc &=3D ~pfc_mask; + pfc |=3D (cache->pfc[port] & pfc_mask); writel(pfc, pctrl->base + PFC(off)); =20 /* Switch to Peripheral pin function. */ --=20 2.43.0