From nobody Sat Oct 4 12:49:02 2025 Received: from mail-pf1-f177.google.com (mail-pf1-f177.google.com [209.85.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 03A6C288516 for ; Sun, 17 Aug 2025 12:34:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.177 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755434049; cv=none; b=TgUIr92GGuofLKkKjYz8mu+jFy4ALAK6lmgJi0Ti7keQ0kWts5ggExCI6L6k7Py3coPzVvkLxmq/wEdpzMBj7pW+5QkGAWZBjdcsahlT/Dx8vSliQWVpaM4JS7l/3w6TdL01lC79v72C8LqOFdjv2kp3SzsWzH9tTc/h9QpQ7p0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755434049; c=relaxed/simple; bh=hVMdhYbIXLIIT6+8btqojCllM2RBg3WEv0m0tN5ZgeU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=t9cSaK8SdgWBnCB2VEtkhNJGgxjGtvYQPsXPZGulKzT6XWTxzbHpcDdC/po470LWVT/Hui7ZQkov0dqpIz48uB1MzhwvXKaZlW11QmGRIPVtlJrKbzwtUi2gzbRQo0xN1peFMH054n0aRy1F3yV8l9yqXqRtIwRR4h5vYhRReCQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com; spf=pass smtp.mailfrom=ventanamicro.com; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b=iUaaxycO; arc=none smtp.client-ip=209.85.210.177 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b="iUaaxycO" Received: by mail-pf1-f177.google.com with SMTP id d2e1a72fcca58-76e2eb20a64so3632198b3a.3 for ; Sun, 17 Aug 2025 05:34:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1755434046; x=1756038846; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=1X6mHsVn0Xnkju9YueBNfmXGkOzlQDsEJD2zMFOchw0=; b=iUaaxycO7XbEhXlz3KXlj5rVDGbAg65hv43HduPZFjS8YsJfZgQyEtKFmTj4fJ7T5V ic18GUHVoicFZdm3gNYop4mXJQcrXlVZP/pclaEzvwnZilxhPCURr89eRdt3wv2fvxpz TRPadDUdY/74spuWcyWCO02Ywd3fqMi0xrESFi/0aDzlqD3gQh+dHK24RJjcaM06CvDh MozDXwoIiwjJ0ALuVUu3PkOK0uODr10hQ7OQPz7xT4bGBl5fVgcQP9WUnYSr/as7VEwF jTpyUIx35nP57u81NmLFMpkPpb3FvpT3JMmUYtxHxswg8YNUokdksOZH1sR3trUfPeTf X+Bg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1755434046; x=1756038846; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1X6mHsVn0Xnkju9YueBNfmXGkOzlQDsEJD2zMFOchw0=; b=TDNvVwQoXkHuxVJIBDUi7s0+EsLzhMsCAL6jl+GY49wy2iNigP6Swk8S3AaxVMUITs ynUM55sMOV82STm5XAi8YBiPaW9i+pJtnAueSCW2+POjyc5BgreOWPn5I7Lrkz3/Ezzw o1IOIdcFxeiuTp3+rLB6LTq1ZXGhE7IXdO22DqhIUyOOlgzvwHPEv/JU/C4PROGTE1pH 9fOgK6D6vON2Z7/atA+RUMP6Ua46Zv/K65EBeg53DMp5+JPit76JFXJKAIsp575gk+ed C67YZxwShQHlO5OUyeFyM9NxocWQQI0z91m5Is/3G5wNoA1oUz1JsHCIx9O5dQdVcSqk 5Mqg== X-Forwarded-Encrypted: i=1; AJvYcCVf1n0HTfv1F3EGwAST+B+MTWXC432PRI4hDilCbtmsgrhtiRrLtgPlTldm9eteYcg0CdyNNuFpgOEYWGA=@vger.kernel.org X-Gm-Message-State: AOJu0Yx7bDbTI6KPLSdT3mP4FtlNpEGzGXa8quPuZz9l1KuYtVudXUkx waIO8/94Od8VZZ2djQU5KBgGa1nLzGvnDpKFkF/JG6/cMUMz9hdkxmiuHEkcG48ksHk= X-Gm-Gg: ASbGnctxFVAxMHn2fXWjK3bc4mdgko5A+JyKWAGzwtzcAg1XvsX2U0sIyrohyOaX5zd HLto6wvZwUVaweA7CqoRlnSGp11JEGq6LKCmGcv4AKEJZW+GJf2EadSf6YmTfejxSwJ2oEF1ByI EeetDHhikqakuF3aRP50gYt3oP9u/XgWJvRCTXfsCqNIH+CvjqpuwN1vc+CYUizPbZDx4hNfsw1 vTPoaMplf09b8FiZrzeMbeXIlexMNUjE/3JeW2KtyXpK/oRvHH6K+zvVqt4PxrPf9nAuW4AU4Xf hnJjZKyIFabSpVxAtUEHkNhlx9oCSK6eIoE2P7YGapZ81XW6D3usroi0WTzLLNsOJTFGGQ/Ms5y mCTBrVMus4plkTziYBkzzpzKDP/e6P+eKISdk5IJf6po9fs5tgu9pb7c= X-Google-Smtp-Source: AGHT+IEtC55e88m1o+TkYXc5HIsqgrGIksroTJA/ryQI57h4rVtpqXgcH5RlB6DdCPCfpIn1BlcsZQ== X-Received: by 2002:a05:6a20:244b:b0:240:8d5:6271 with SMTP id adf61e73a8af0-240d2f28027mr11452970637.39.1755434046019; Sun, 17 Aug 2025 05:34:06 -0700 (PDT) Received: from localhost.localdomain ([122.171.23.202]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3232b291449sm4480912a91.0.2025.08.17.05.34.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Aug 2025 05:34:05 -0700 (PDT) From: Anup Patel To: Atish Patra Cc: Palmer Dabbelt , Paul Walmsley , Alexandre Ghiti , Andrew Jones , Anup Patel , Paolo Bonzini , Shuah Khan , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, Anup Patel Subject: [PATCH v2 5/6] RISC-V: KVM: Implement ONE_REG interface for SBI FWFT state Date: Sun, 17 Aug 2025 18:03:23 +0530 Message-ID: <20250817123324.239423-6-apatel@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250817123324.239423-1-apatel@ventanamicro.com> References: <20250817123324.239423-1-apatel@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The KVM user-space needs a way to save/restore the state of SBI FWFT features so implement SBI extension ONE_REG callbacks. Signed-off-by: Anup Patel --- arch/riscv/include/uapi/asm/kvm.h | 14 +++ arch/riscv/kvm/vcpu_sbi_fwft.c | 168 +++++++++++++++++++++++++++--- 2 files changed, 170 insertions(+), 12 deletions(-) diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/as= m/kvm.h index a5ca0f4ce2d3..fc5624e89c7b 100644 --- a/arch/riscv/include/uapi/asm/kvm.h +++ b/arch/riscv/include/uapi/asm/kvm.h @@ -215,6 +215,17 @@ struct kvm_riscv_sbi_sta { unsigned long shmem_hi; }; =20 +struct kvm_riscv_sbi_fwft_feature { + unsigned long flags; + unsigned long value; +}; + +/* SBI FWFT extension registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */ +struct kvm_riscv_sbi_fwft { + struct kvm_riscv_sbi_fwft_feature misaligned_deleg; + struct kvm_riscv_sbi_fwft_feature pointer_masking; +}; + /* Possible states for kvm_riscv_timer */ #define KVM_RISCV_TIMER_STATE_OFF 0 #define KVM_RISCV_TIMER_STATE_ON 1 @@ -298,6 +309,9 @@ struct kvm_riscv_sbi_sta { #define KVM_REG_RISCV_SBI_STA (0x0 << KVM_REG_RISCV_SUBTYPE_SHIFT) #define KVM_REG_RISCV_SBI_STA_REG(name) \ (offsetof(struct kvm_riscv_sbi_sta, name) / sizeof(unsigned long)) +#define KVM_REG_RISCV_SBI_FWFT (0x1 << KVM_REG_RISCV_SUBTYPE_SHIFT) +#define KVM_REG_RISCV_SBI_FWFT_REG(name) \ + (offsetof(struct kvm_riscv_sbi_fwft, name) / sizeof(unsigned long)) =20 /* Device Control API: RISC-V AIA */ #define KVM_DEV_RISCV_APLIC_ALIGN 0x1000 diff --git a/arch/riscv/kvm/vcpu_sbi_fwft.c b/arch/riscv/kvm/vcpu_sbi_fwft.c index 5a3bad0f9330..6499a669f9d0 100644 --- a/arch/riscv/kvm/vcpu_sbi_fwft.c +++ b/arch/riscv/kvm/vcpu_sbi_fwft.c @@ -22,6 +22,11 @@ struct kvm_sbi_fwft_feature { */ enum sbi_fwft_feature_t id; =20 + /** + * @flags_reg_num: ONE_REG index of the feature flag + */ + unsigned long flags_reg_num; + /** * @supported: Check if the feature is supported on the vcpu * @@ -44,7 +49,8 @@ struct kvm_sbi_fwft_feature { * * This callback is mandatory */ - long (*set)(struct kvm_vcpu *vcpu, struct kvm_sbi_fwft_config *conf, unsi= gned long value); + long (*set)(struct kvm_vcpu *vcpu, struct kvm_sbi_fwft_config *conf, + bool one_reg_access, unsigned long value); =20 /** * @get: Get the feature current value @@ -53,7 +59,8 @@ struct kvm_sbi_fwft_feature { * * This callback is mandatory */ - long (*get)(struct kvm_vcpu *vcpu, struct kvm_sbi_fwft_config *conf, unsi= gned long *value); + long (*get)(struct kvm_vcpu *vcpu, struct kvm_sbi_fwft_config *conf, + bool one_reg_access, unsigned long *value); }; =20 static const enum sbi_fwft_feature_t kvm_fwft_defined_features[] =3D { @@ -91,16 +98,18 @@ static void kvm_sbi_fwft_reset_misaligned_delegation(st= ruct kvm_vcpu *vcpu) =20 static long kvm_sbi_fwft_set_misaligned_delegation(struct kvm_vcpu *vcpu, struct kvm_sbi_fwft_config *conf, - unsigned long value) + bool one_reg_access, unsigned long value) { struct kvm_vcpu_config *cfg =3D &vcpu->arch.cfg; =20 if (value =3D=3D 1) { cfg->hedeleg |=3D MIS_DELEG; - csr_set(CSR_HEDELEG, MIS_DELEG); + if (!one_reg_access) + csr_set(CSR_HEDELEG, MIS_DELEG); } else if (value =3D=3D 0) { cfg->hedeleg &=3D ~MIS_DELEG; - csr_clear(CSR_HEDELEG, MIS_DELEG); + if (!one_reg_access) + csr_clear(CSR_HEDELEG, MIS_DELEG); } else { return SBI_ERR_INVALID_PARAM; } @@ -110,10 +119,11 @@ static long kvm_sbi_fwft_set_misaligned_delegation(st= ruct kvm_vcpu *vcpu, =20 static long kvm_sbi_fwft_get_misaligned_delegation(struct kvm_vcpu *vcpu, struct kvm_sbi_fwft_config *conf, - unsigned long *value) + bool one_reg_access, unsigned long *value) { - *value =3D (csr_read(CSR_HEDELEG) & MIS_DELEG) =3D=3D MIS_DELEG; + struct kvm_vcpu_config *cfg =3D &vcpu->arch.cfg; =20 + *value =3D (cfg->hedeleg & MIS_DELEG) =3D=3D MIS_DELEG; return SBI_SUCCESS; } =20 @@ -145,7 +155,7 @@ static void kvm_sbi_fwft_reset_pointer_masking_pmlen(st= ruct kvm_vcpu *vcpu) =20 static long kvm_sbi_fwft_set_pointer_masking_pmlen(struct kvm_vcpu *vcpu, struct kvm_sbi_fwft_config *conf, - unsigned long value) + bool one_reg_access, unsigned long value) { struct kvm_sbi_fwft *fwft =3D vcpu_to_fwft(vcpu); unsigned long pmm; @@ -167,14 +177,15 @@ static long kvm_sbi_fwft_set_pointer_masking_pmlen(st= ruct kvm_vcpu *vcpu, * update here so that VCPU see's pointer masking mode change * immediately. */ - csr_write(CSR_HENVCFG, vcpu->arch.cfg.henvcfg); + if (!one_reg_access) + csr_write(CSR_HENVCFG, vcpu->arch.cfg.henvcfg); =20 return SBI_SUCCESS; } =20 static long kvm_sbi_fwft_get_pointer_masking_pmlen(struct kvm_vcpu *vcpu, struct kvm_sbi_fwft_config *conf, - unsigned long *value) + bool one_reg_access, unsigned long *value) { switch (vcpu->arch.cfg.henvcfg & ENVCFG_PMM) { case ENVCFG_PMM_PMLEN_0: @@ -198,6 +209,8 @@ static long kvm_sbi_fwft_get_pointer_masking_pmlen(stru= ct kvm_vcpu *vcpu, static const struct kvm_sbi_fwft_feature features[] =3D { { .id =3D SBI_FWFT_MISALIGNED_EXC_DELEG, + .flags_reg_num =3D offsetof(struct kvm_riscv_sbi_fwft, misaligned_deleg.= flags) / + sizeof(unsigned long), .supported =3D kvm_sbi_fwft_misaligned_delegation_supported, .reset =3D kvm_sbi_fwft_reset_misaligned_delegation, .set =3D kvm_sbi_fwft_set_misaligned_delegation, @@ -206,6 +219,8 @@ static const struct kvm_sbi_fwft_feature features[] =3D= { #ifndef CONFIG_32BIT { .id =3D SBI_FWFT_POINTER_MASKING_PMLEN, + .flags_reg_num =3D offsetof(struct kvm_riscv_sbi_fwft, pointer_masking.f= lags) / + sizeof(unsigned long), .supported =3D kvm_sbi_fwft_pointer_masking_pmlen_supported, .reset =3D kvm_sbi_fwft_reset_pointer_masking_pmlen, .set =3D kvm_sbi_fwft_set_pointer_masking_pmlen, @@ -214,6 +229,21 @@ static const struct kvm_sbi_fwft_feature features[] = =3D { #endif }; =20 +static const struct kvm_sbi_fwft_feature *kvm_sbi_fwft_regnum_to_feature(u= nsigned long reg_num) +{ + const struct kvm_sbi_fwft_feature *feature; + int i; + + for (i =3D 0; i < ARRAY_SIZE(features); i++) { + feature =3D &features[i]; + if (feature->flags_reg_num =3D=3D reg_num || + (feature->flags_reg_num + 1) =3D=3D reg_num) + return feature; + } + + return NULL; +} + static struct kvm_sbi_fwft_config * kvm_sbi_fwft_get_config(struct kvm_vcpu *vcpu, enum sbi_fwft_feature_t fea= ture) { @@ -267,7 +297,7 @@ static int kvm_sbi_fwft_set(struct kvm_vcpu *vcpu, u32 = feature, =20 conf->flags =3D flags; =20 - return conf->feature->set(vcpu, conf, value); + return conf->feature->set(vcpu, conf, false, value); } =20 static int kvm_sbi_fwft_get(struct kvm_vcpu *vcpu, unsigned long feature, @@ -280,7 +310,7 @@ static int kvm_sbi_fwft_get(struct kvm_vcpu *vcpu, unsi= gned long feature, if (ret) return ret; =20 - return conf->feature->get(vcpu, conf, value); + return conf->feature->get(vcpu, conf, false, value); } =20 static int kvm_sbi_ext_fwft_handler(struct kvm_vcpu *vcpu, struct kvm_run = *run, @@ -354,6 +384,115 @@ static void kvm_sbi_ext_fwft_reset(struct kvm_vcpu *v= cpu) } } =20 +static unsigned long kvm_sbi_ext_fwft_get_reg_count(struct kvm_vcpu *vcpu) +{ + unsigned long max_reg_count =3D sizeof(struct kvm_riscv_sbi_fwft) / sizeo= f(unsigned long); + const struct kvm_sbi_fwft_feature *feature; + struct kvm_sbi_fwft_config *conf; + unsigned long reg, ret =3D 0; + + for (reg =3D 0; reg < max_reg_count; reg++) { + feature =3D kvm_sbi_fwft_regnum_to_feature(reg); + if (!feature) + continue; + + conf =3D kvm_sbi_fwft_get_config(vcpu, feature->id); + if (!conf || !conf->supported) + continue; + + ret++; + } + + return ret; +} + +static int kvm_sbi_ext_fwft_get_reg_id(struct kvm_vcpu *vcpu, int index, u= 64 *reg_id) +{ + int reg, max_reg_count =3D sizeof(struct kvm_riscv_sbi_fwft) / sizeof(uns= igned long); + const struct kvm_sbi_fwft_feature *feature; + struct kvm_sbi_fwft_config *conf; + int idx =3D 0; + + for (reg =3D 0; reg < max_reg_count; reg++) { + feature =3D kvm_sbi_fwft_regnum_to_feature(reg); + if (!feature) + continue; + + conf =3D kvm_sbi_fwft_get_config(vcpu, feature->id); + if (!conf || !conf->supported) + continue; + + if (index =3D=3D idx) { + *reg_id =3D KVM_REG_RISCV | + (IS_ENABLED(CONFIG_32BIT) ? + KVM_REG_SIZE_U32 : KVM_REG_SIZE_U64) | + KVM_REG_RISCV_SBI_STATE | + KVM_REG_RISCV_SBI_FWFT | reg; + return 0; + } + + idx++; + } + + return -ENOENT; +} + +static int kvm_sbi_ext_fwft_get_reg(struct kvm_vcpu *vcpu, unsigned long r= eg_num, + unsigned long reg_size, void *reg_val) +{ + const struct kvm_sbi_fwft_feature *feature; + struct kvm_sbi_fwft_config *conf; + unsigned long *value; + int ret =3D 0; + + if (reg_size !=3D sizeof(unsigned long)) + return -EINVAL; + value =3D reg_val; + + feature =3D kvm_sbi_fwft_regnum_to_feature(reg_num); + if (!feature) + return -ENOENT; + + conf =3D kvm_sbi_fwft_get_config(vcpu, feature->id); + if (!conf || !conf->supported) + return -ENOENT; + + if (feature->flags_reg_num =3D=3D reg_num) + *value =3D conf->flags; + else + ret =3D conf->feature->get(vcpu, conf, true, value); + + return sbi_err_map_linux_errno(ret); +} + +static int kvm_sbi_ext_fwft_set_reg(struct kvm_vcpu *vcpu, unsigned long r= eg_num, + unsigned long reg_size, const void *reg_val) +{ + const struct kvm_sbi_fwft_feature *feature; + struct kvm_sbi_fwft_config *conf; + unsigned long value; + int ret =3D 0; + + if (reg_size !=3D sizeof(unsigned long)) + return -EINVAL; + value =3D *(const unsigned long *)reg_val; + + feature =3D kvm_sbi_fwft_regnum_to_feature(reg_num); + if (!feature) + return -ENOENT; + + conf =3D kvm_sbi_fwft_get_config(vcpu, feature->id); + if (!conf || !conf->supported) + return -ENOENT; + + if (feature->flags_reg_num =3D=3D reg_num) + conf->flags =3D value & SBI_FWFT_SET_FLAG_LOCK; + else + ret =3D conf->feature->set(vcpu, conf, true, value); + + return sbi_err_map_linux_errno(ret); +} + const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_fwft =3D { .extid_start =3D SBI_EXT_FWFT, .extid_end =3D SBI_EXT_FWFT, @@ -361,4 +500,9 @@ const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_fwft = =3D { .init =3D kvm_sbi_ext_fwft_init, .deinit =3D kvm_sbi_ext_fwft_deinit, .reset =3D kvm_sbi_ext_fwft_reset, + .state_reg_subtype =3D KVM_REG_RISCV_SBI_FWFT, + .get_state_reg_count =3D kvm_sbi_ext_fwft_get_reg_count, + .get_state_reg_id =3D kvm_sbi_ext_fwft_get_reg_id, + .get_state_reg =3D kvm_sbi_ext_fwft_get_reg, + .set_state_reg =3D kvm_sbi_ext_fwft_set_reg, }; --=20 2.43.0