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Sun, 17 Aug 2025 05:33:45 -0700 (PDT) From: Anup Patel To: Atish Patra Cc: Palmer Dabbelt , Paul Walmsley , Alexandre Ghiti , Andrew Jones , Anup Patel , Paolo Bonzini , Shuah Khan , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, Anup Patel Subject: [PATCH v2 1/6] RISC-V: KVM: Set initial value of hedeleg in kvm_arch_vcpu_create() Date: Sun, 17 Aug 2025 18:03:19 +0530 Message-ID: <20250817123324.239423-2-apatel@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250817123324.239423-1-apatel@ventanamicro.com> References: <20250817123324.239423-1-apatel@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The hedeleg may be updated by ONE_REG interface before the VCPU is run at least once hence set the initial value of hedeleg in kvm_arch_vcpu_create() instead of kvm_riscv_vcpu_setup_config(). Signed-off-by: Anup Patel Reviewed-by: Andrew Jones --- arch/riscv/kvm/vcpu.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index f001e56403f9..86025f68c374 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -133,6 +133,8 @@ int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu) =20 /* Mark this VCPU never ran */ vcpu->arch.ran_atleast_once =3D false; + + vcpu->arch.cfg.hedeleg =3D KVM_HEDELEG_DEFAULT; vcpu->arch.mmu_page_cache.gfp_zero =3D __GFP_ZERO; bitmap_zero(vcpu->arch.isa, RISCV_ISA_EXT_MAX); =20 @@ -570,7 +572,6 @@ static void kvm_riscv_vcpu_setup_config(struct kvm_vcpu= *vcpu) cfg->hstateen0 |=3D SMSTATEEN0_SSTATEEN0; } =20 - cfg->hedeleg =3D KVM_HEDELEG_DEFAULT; if (vcpu->guest_debug) cfg->hedeleg &=3D ~BIT(EXC_BREAKPOINT); } --=20 2.43.0 From nobody Sat Oct 4 11:13:52 2025 Received: from mail-pj1-f44.google.com (mail-pj1-f44.google.com [209.85.216.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 99D044C79 for ; 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Sun, 17 Aug 2025 05:33:50 -0700 (PDT) Received: from localhost.localdomain ([122.171.23.202]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3232b291449sm4480912a91.0.2025.08.17.05.33.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Aug 2025 05:33:50 -0700 (PDT) From: Anup Patel To: Atish Patra Cc: Palmer Dabbelt , Paul Walmsley , Alexandre Ghiti , Andrew Jones , Anup Patel , Paolo Bonzini , Shuah Khan , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, Anup Patel Subject: [PATCH v2 2/6] RISC-V: KVM: Introduce feature specific reset for SBI FWFT Date: Sun, 17 Aug 2025 18:03:20 +0530 Message-ID: <20250817123324.239423-3-apatel@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250817123324.239423-1-apatel@ventanamicro.com> References: <20250817123324.239423-1-apatel@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The SBI FWFT feature values must be reset upon VCPU reset so introduce feature specific reset callback for this purpose. Signed-off-by: Anup Patel Reviewed-by: Andrew Jones --- arch/riscv/kvm/vcpu_sbi_fwft.c | 30 ++++++++++++++++++++++++++++-- 1 file changed, 28 insertions(+), 2 deletions(-) diff --git a/arch/riscv/kvm/vcpu_sbi_fwft.c b/arch/riscv/kvm/vcpu_sbi_fwft.c index 164a01288b0a..5a3bad0f9330 100644 --- a/arch/riscv/kvm/vcpu_sbi_fwft.c +++ b/arch/riscv/kvm/vcpu_sbi_fwft.c @@ -30,6 +30,13 @@ struct kvm_sbi_fwft_feature { */ bool (*supported)(struct kvm_vcpu *vcpu); =20 + /** + * @reset: Reset the feature value irrespective whether feature is suppor= ted or not + * + * This callback is mandatory + */ + void (*reset)(struct kvm_vcpu *vcpu); + /** * @set: Set the feature value * @@ -75,6 +82,13 @@ static bool kvm_sbi_fwft_misaligned_delegation_supported= (struct kvm_vcpu *vcpu) return misaligned_traps_can_delegate(); } =20 +static void kvm_sbi_fwft_reset_misaligned_delegation(struct kvm_vcpu *vcpu) +{ + struct kvm_vcpu_config *cfg =3D &vcpu->arch.cfg; + + cfg->hedeleg &=3D ~MIS_DELEG; +} + static long kvm_sbi_fwft_set_misaligned_delegation(struct kvm_vcpu *vcpu, struct kvm_sbi_fwft_config *conf, unsigned long value) @@ -124,6 +138,11 @@ static bool kvm_sbi_fwft_pointer_masking_pmlen_support= ed(struct kvm_vcpu *vcpu) return fwft->have_vs_pmlen_7 || fwft->have_vs_pmlen_16; } =20 +static void kvm_sbi_fwft_reset_pointer_masking_pmlen(struct kvm_vcpu *vcpu) +{ + vcpu->arch.cfg.henvcfg &=3D ~ENVCFG_PMM; +} + static long kvm_sbi_fwft_set_pointer_masking_pmlen(struct kvm_vcpu *vcpu, struct kvm_sbi_fwft_config *conf, unsigned long value) @@ -180,6 +199,7 @@ static const struct kvm_sbi_fwft_feature features[] =3D= { { .id =3D SBI_FWFT_MISALIGNED_EXC_DELEG, .supported =3D kvm_sbi_fwft_misaligned_delegation_supported, + .reset =3D kvm_sbi_fwft_reset_misaligned_delegation, .set =3D kvm_sbi_fwft_set_misaligned_delegation, .get =3D kvm_sbi_fwft_get_misaligned_delegation, }, @@ -187,6 +207,7 @@ static const struct kvm_sbi_fwft_feature features[] =3D= { { .id =3D SBI_FWFT_POINTER_MASKING_PMLEN, .supported =3D kvm_sbi_fwft_pointer_masking_pmlen_supported, + .reset =3D kvm_sbi_fwft_reset_pointer_masking_pmlen, .set =3D kvm_sbi_fwft_set_pointer_masking_pmlen, .get =3D kvm_sbi_fwft_get_pointer_masking_pmlen, }, @@ -321,11 +342,16 @@ static void kvm_sbi_ext_fwft_deinit(struct kvm_vcpu *= vcpu) =20 static void kvm_sbi_ext_fwft_reset(struct kvm_vcpu *vcpu) { - int i; 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Sun, 17 Aug 2025 05:33:55 -0700 (PDT) Received: from localhost.localdomain ([122.171.23.202]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3232b291449sm4480912a91.0.2025.08.17.05.33.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Aug 2025 05:33:55 -0700 (PDT) From: Anup Patel To: Atish Patra Cc: Palmer Dabbelt , Paul Walmsley , Alexandre Ghiti , Andrew Jones , Anup Patel , Paolo Bonzini , Shuah Khan , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, Anup Patel Subject: [PATCH v2 3/6] RISC-V: KVM: Introduce optional ONE_REG callbacks for SBI extensions Date: Sun, 17 Aug 2025 18:03:21 +0530 Message-ID: <20250817123324.239423-4-apatel@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250817123324.239423-1-apatel@ventanamicro.com> References: <20250817123324.239423-1-apatel@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" SBI extensions can have per-VCPU state which needs to be saved/restored through ONE_REG interface for Guest/VM migration. Introduce optional ONE_REG callbacks for SBI extensions so that ONE_REG implementation for an SBI extenion is part of the extension sources. Signed-off-by: Anup Patel Reviewed-by: Andrew Jones --- arch/riscv/include/asm/kvm_vcpu_sbi.h | 20 ++-- arch/riscv/kvm/vcpu_onereg.c | 31 +----- arch/riscv/kvm/vcpu_sbi.c | 145 ++++++++++++++++++++++---- arch/riscv/kvm/vcpu_sbi_sta.c | 63 +++++++---- 4 files changed, 176 insertions(+), 83 deletions(-) diff --git a/arch/riscv/include/asm/kvm_vcpu_sbi.h b/arch/riscv/include/asm= /kvm_vcpu_sbi.h index 766031e80960..8970cc7530c4 100644 --- a/arch/riscv/include/asm/kvm_vcpu_sbi.h +++ b/arch/riscv/include/asm/kvm_vcpu_sbi.h @@ -59,6 +59,14 @@ struct kvm_vcpu_sbi_extension { void (*deinit)(struct kvm_vcpu *vcpu); =20 void (*reset)(struct kvm_vcpu *vcpu); + + unsigned long state_reg_subtype; + unsigned long (*get_state_reg_count)(struct kvm_vcpu *vcpu); + int (*get_state_reg_id)(struct kvm_vcpu *vcpu, int index, u64 *reg_id); + int (*get_state_reg)(struct kvm_vcpu *vcpu, unsigned long reg_num, + unsigned long reg_size, void *reg_val); + int (*set_state_reg)(struct kvm_vcpu *vcpu, unsigned long reg_num, + unsigned long reg_size, const void *reg_val); }; =20 void kvm_riscv_vcpu_sbi_forward(struct kvm_vcpu *vcpu, struct kvm_run *run= ); @@ -73,10 +81,9 @@ int kvm_riscv_vcpu_set_reg_sbi_ext(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg); int kvm_riscv_vcpu_get_reg_sbi_ext(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg); -int kvm_riscv_vcpu_set_reg_sbi(struct kvm_vcpu *vcpu, - const struct kvm_one_reg *reg); -int kvm_riscv_vcpu_get_reg_sbi(struct kvm_vcpu *vcpu, - const struct kvm_one_reg *reg); +int kvm_riscv_vcpu_reg_indices_sbi(struct kvm_vcpu *vcpu, u64 __user *uind= ices); +int kvm_riscv_vcpu_set_reg_sbi(struct kvm_vcpu *vcpu, const struct kvm_one= _reg *reg); +int kvm_riscv_vcpu_get_reg_sbi(struct kvm_vcpu *vcpu, const struct kvm_one= _reg *reg); const struct kvm_vcpu_sbi_extension *kvm_vcpu_sbi_find_ext( struct kvm_vcpu *vcpu, unsigned long extid); bool riscv_vcpu_supports_sbi_ext(struct kvm_vcpu *vcpu, int idx); @@ -85,11 +92,6 @@ void kvm_riscv_vcpu_sbi_init(struct kvm_vcpu *vcpu); void kvm_riscv_vcpu_sbi_deinit(struct kvm_vcpu *vcpu); void kvm_riscv_vcpu_sbi_reset(struct kvm_vcpu *vcpu); =20 -int kvm_riscv_vcpu_get_reg_sbi_sta(struct kvm_vcpu *vcpu, unsigned long re= g_num, - unsigned long *reg_val); -int kvm_riscv_vcpu_set_reg_sbi_sta(struct kvm_vcpu *vcpu, unsigned long re= g_num, - unsigned long reg_val); - #ifdef CONFIG_RISCV_SBI_V01 extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_v01; #endif diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c index b77748a56a59..5843b0519224 100644 --- a/arch/riscv/kvm/vcpu_onereg.c +++ b/arch/riscv/kvm/vcpu_onereg.c @@ -1090,36 +1090,9 @@ static unsigned long num_sbi_ext_regs(struct kvm_vcp= u *vcpu) return copy_sbi_ext_reg_indices(vcpu, NULL); } =20 -static int copy_sbi_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindice= s) -{ - struct kvm_vcpu_sbi_context *scontext =3D &vcpu->arch.sbi_context; - int total =3D 0; - - if (scontext->ext_status[KVM_RISCV_SBI_EXT_STA] =3D=3D KVM_RISCV_SBI_EXT_= STATUS_ENABLED) { - u64 size =3D IS_ENABLED(CONFIG_32BIT) ? KVM_REG_SIZE_U32 : KVM_REG_SIZE_= U64; - int n =3D sizeof(struct kvm_riscv_sbi_sta) / sizeof(unsigned long); - - for (int i =3D 0; i < n; i++) { - u64 reg =3D KVM_REG_RISCV | size | - KVM_REG_RISCV_SBI_STATE | - KVM_REG_RISCV_SBI_STA | i; - - if (uindices) { - if (put_user(reg, uindices)) - return -EFAULT; - uindices++; - } - } - - total +=3D n; - } - - return total; -} - static inline unsigned long num_sbi_regs(struct kvm_vcpu *vcpu) { - return copy_sbi_reg_indices(vcpu, NULL); + return kvm_riscv_vcpu_reg_indices_sbi(vcpu, NULL); } =20 static inline unsigned long num_vector_regs(const struct kvm_vcpu *vcpu) @@ -1247,7 +1220,7 @@ int kvm_riscv_vcpu_copy_reg_indices(struct kvm_vcpu *= vcpu, return ret; uindices +=3D ret; =20 - ret =3D copy_sbi_reg_indices(vcpu, uindices); + ret =3D kvm_riscv_vcpu_reg_indices_sbi(vcpu, uindices); if (ret < 0) return ret; uindices +=3D ret; diff --git a/arch/riscv/kvm/vcpu_sbi.c b/arch/riscv/kvm/vcpu_sbi.c index 01a93f4fdb16..04903e5012d6 100644 --- a/arch/riscv/kvm/vcpu_sbi.c +++ b/arch/riscv/kvm/vcpu_sbi.c @@ -364,64 +364,163 @@ int kvm_riscv_vcpu_get_reg_sbi_ext(struct kvm_vcpu *= vcpu, return 0; } =20 -int kvm_riscv_vcpu_set_reg_sbi(struct kvm_vcpu *vcpu, - const struct kvm_one_reg *reg) +int kvm_riscv_vcpu_reg_indices_sbi(struct kvm_vcpu *vcpu, u64 __user *uind= ices) +{ + struct kvm_vcpu_sbi_context *scontext =3D &vcpu->arch.sbi_context; + const struct kvm_riscv_sbi_extension_entry *entry; + const struct kvm_vcpu_sbi_extension *ext; + unsigned long state_reg_count; + int i, j, rc, count =3D 0; + u64 reg; + + for (i =3D 0; i < ARRAY_SIZE(sbi_ext); i++) { + entry =3D &sbi_ext[i]; + ext =3D entry->ext_ptr; + + if (!ext->get_state_reg_count || + scontext->ext_status[entry->ext_idx] !=3D KVM_RISCV_SBI_EXT_STATUS_E= NABLED) + continue; + + state_reg_count =3D ext->get_state_reg_count(vcpu); + if (!uindices) + goto skip_put_user; + + for (j =3D 0; j < state_reg_count; j++) { + if (ext->get_state_reg_id) { + rc =3D ext->get_state_reg_id(vcpu, j, ®); + if (rc) + return rc; + } else { + reg =3D KVM_REG_RISCV | + (IS_ENABLED(CONFIG_32BIT) ? + KVM_REG_SIZE_U32 : KVM_REG_SIZE_U64) | + KVM_REG_RISCV_SBI_STATE | + ext->state_reg_subtype | j; + } + + if (put_user(reg, uindices)) + return -EFAULT; + uindices++; + } + +skip_put_user: + count +=3D state_reg_count; + } + + return count; +} + +static const struct kvm_vcpu_sbi_extension *kvm_vcpu_sbi_find_ext_withstat= e(struct kvm_vcpu *vcpu, + unsigned long subtype) +{ + struct kvm_vcpu_sbi_context *scontext =3D &vcpu->arch.sbi_context; + const struct kvm_riscv_sbi_extension_entry *entry; + const struct kvm_vcpu_sbi_extension *ext; + int i; + + for (i =3D 0; i < ARRAY_SIZE(sbi_ext); i++) { + entry =3D &sbi_ext[i]; + ext =3D entry->ext_ptr; + + if (ext->get_state_reg_count && + ext->state_reg_subtype =3D=3D subtype && + scontext->ext_status[entry->ext_idx] =3D=3D KVM_RISCV_SBI_EXT_STATUS= _ENABLED) + return ext; + } + + return NULL; +} + +int kvm_riscv_vcpu_set_reg_sbi(struct kvm_vcpu *vcpu, const struct kvm_one= _reg *reg) { unsigned long __user *uaddr =3D (unsigned long __user *)(unsigned long)reg->addr; unsigned long reg_num =3D reg->id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK | KVM_REG_RISCV_SBI_STATE); - unsigned long reg_subtype, reg_val; - - if (KVM_REG_SIZE(reg->id) !=3D sizeof(unsigned long)) + const struct kvm_vcpu_sbi_extension *ext; + unsigned long reg_subtype; + void *reg_val; + u64 data64; + u32 data32; + u16 data16; + u8 data8; + + switch (KVM_REG_SIZE(reg->id)) { + case 1: + reg_val =3D &data8; + break; + case 2: + reg_val =3D &data16; + break; + case 4: + reg_val =3D &data32; + break; + case 8: + reg_val =3D &data64; + break; + default: return -EINVAL; + } =20 - if (copy_from_user(®_val, uaddr, KVM_REG_SIZE(reg->id))) + if (copy_from_user(reg_val, uaddr, KVM_REG_SIZE(reg->id))) return -EFAULT; =20 reg_subtype =3D reg_num & KVM_REG_RISCV_SUBTYPE_MASK; reg_num &=3D ~KVM_REG_RISCV_SUBTYPE_MASK; =20 - switch (reg_subtype) { - case KVM_REG_RISCV_SBI_STA: - return kvm_riscv_vcpu_set_reg_sbi_sta(vcpu, reg_num, reg_val); - default: + ext =3D kvm_vcpu_sbi_find_ext_withstate(vcpu, reg_subtype); + if (!ext || !ext->set_state_reg) return -EINVAL; - } =20 - return 0; + return ext->set_state_reg(vcpu, reg_num, KVM_REG_SIZE(reg->id), reg_val); } =20 -int kvm_riscv_vcpu_get_reg_sbi(struct kvm_vcpu *vcpu, - const struct kvm_one_reg *reg) +int kvm_riscv_vcpu_get_reg_sbi(struct kvm_vcpu *vcpu, const struct kvm_one= _reg *reg) { unsigned long __user *uaddr =3D (unsigned long __user *)(unsigned long)reg->addr; unsigned long reg_num =3D reg->id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK | KVM_REG_RISCV_SBI_STATE); - unsigned long reg_subtype, reg_val; + const struct kvm_vcpu_sbi_extension *ext; + unsigned long reg_subtype; + void *reg_val; + u64 data64; + u32 data32; + u16 data16; + u8 data8; int ret; =20 - if (KVM_REG_SIZE(reg->id) !=3D sizeof(unsigned long)) + switch (KVM_REG_SIZE(reg->id)) { + case 1: + reg_val =3D &data8; + break; + case 2: + reg_val =3D &data16; + break; + case 4: + reg_val =3D &data32; + break; + case 8: + reg_val =3D &data64; + break; + default: return -EINVAL; + } =20 reg_subtype =3D reg_num & KVM_REG_RISCV_SUBTYPE_MASK; reg_num &=3D ~KVM_REG_RISCV_SUBTYPE_MASK; =20 - switch (reg_subtype) { - case KVM_REG_RISCV_SBI_STA: - ret =3D kvm_riscv_vcpu_get_reg_sbi_sta(vcpu, reg_num, ®_val); - break; - default: + ext =3D kvm_vcpu_sbi_find_ext_withstate(vcpu, reg_subtype); + if (!ext || !ext->get_state_reg) return -EINVAL; - } =20 + ret =3D ext->get_state_reg(vcpu, reg_num, KVM_REG_SIZE(reg->id), reg_val); if (ret) return ret; =20 - if (copy_to_user(uaddr, ®_val, KVM_REG_SIZE(reg->id))) + if (copy_to_user(uaddr, reg_val, KVM_REG_SIZE(reg->id))) return -EFAULT; =20 return 0; diff --git a/arch/riscv/kvm/vcpu_sbi_sta.c b/arch/riscv/kvm/vcpu_sbi_sta.c index cc6cb7c8f0e4..68486f90a61e 100644 --- a/arch/riscv/kvm/vcpu_sbi_sta.c +++ b/arch/riscv/kvm/vcpu_sbi_sta.c @@ -151,63 +151,82 @@ static unsigned long kvm_sbi_ext_sta_probe(struct kvm= _vcpu *vcpu) return !!sched_info_on(); } =20 -const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_sta =3D { - .extid_start =3D SBI_EXT_STA, - .extid_end =3D SBI_EXT_STA, - .handler =3D kvm_sbi_ext_sta_handler, - .probe =3D kvm_sbi_ext_sta_probe, - .reset =3D kvm_riscv_vcpu_sbi_sta_reset, -}; +static unsigned long kvm_sbi_ext_sta_get_state_reg_count(struct kvm_vcpu *= vcpu) +{ + return sizeof(struct kvm_riscv_sbi_sta) / sizeof(unsigned long); +} =20 -int kvm_riscv_vcpu_get_reg_sbi_sta(struct kvm_vcpu *vcpu, - unsigned long reg_num, - unsigned long *reg_val) +static int kvm_sbi_ext_sta_get_reg(struct kvm_vcpu *vcpu, unsigned long re= g_num, + unsigned long reg_size, void *reg_val) { + unsigned long *value; + + if (reg_size !=3D sizeof(unsigned long)) + return -EINVAL; + value =3D reg_val; + switch (reg_num) { case KVM_REG_RISCV_SBI_STA_REG(shmem_lo): - *reg_val =3D (unsigned long)vcpu->arch.sta.shmem; + *value =3D (unsigned long)vcpu->arch.sta.shmem; break; case KVM_REG_RISCV_SBI_STA_REG(shmem_hi): if (IS_ENABLED(CONFIG_32BIT)) - *reg_val =3D upper_32_bits(vcpu->arch.sta.shmem); + *value =3D upper_32_bits(vcpu->arch.sta.shmem); else - *reg_val =3D 0; + *value =3D 0; break; default: - return -EINVAL; + return -ENOENT; } =20 return 0; } =20 -int kvm_riscv_vcpu_set_reg_sbi_sta(struct kvm_vcpu *vcpu, - unsigned long reg_num, - unsigned long reg_val) +static int kvm_sbi_ext_sta_set_reg(struct kvm_vcpu *vcpu, unsigned long re= g_num, + unsigned long reg_size, const void *reg_val) { + unsigned long value; + + if (reg_size !=3D sizeof(unsigned long)) + return -EINVAL; + value =3D *(const unsigned long *)reg_val; + switch (reg_num) { case KVM_REG_RISCV_SBI_STA_REG(shmem_lo): if (IS_ENABLED(CONFIG_32BIT)) { gpa_t hi =3D upper_32_bits(vcpu->arch.sta.shmem); =20 - vcpu->arch.sta.shmem =3D reg_val; + vcpu->arch.sta.shmem =3D value; vcpu->arch.sta.shmem |=3D hi << 32; } else { - vcpu->arch.sta.shmem =3D reg_val; + vcpu->arch.sta.shmem =3D value; } break; case KVM_REG_RISCV_SBI_STA_REG(shmem_hi): if (IS_ENABLED(CONFIG_32BIT)) { gpa_t lo =3D lower_32_bits(vcpu->arch.sta.shmem); =20 - vcpu->arch.sta.shmem =3D ((gpa_t)reg_val << 32); + vcpu->arch.sta.shmem =3D ((gpa_t)value << 32); vcpu->arch.sta.shmem |=3D lo; - } else if (reg_val !=3D 0) { + } else if (value !=3D 0) { return -EINVAL; } break; default: - return -EINVAL; + return -ENOENT; } =20 return 0; } + +const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_sta =3D { + .extid_start =3D SBI_EXT_STA, + .extid_end =3D SBI_EXT_STA, + .handler =3D kvm_sbi_ext_sta_handler, + .probe =3D kvm_sbi_ext_sta_probe, + .reset =3D kvm_riscv_vcpu_sbi_sta_reset, + .state_reg_subtype =3D KVM_REG_RISCV_SBI_STA, + .get_state_reg_count =3D kvm_sbi_ext_sta_get_state_reg_count, + .get_state_reg =3D kvm_sbi_ext_sta_get_reg, + .set_state_reg =3D kvm_sbi_ext_sta_set_reg, +}; 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Sun, 17 Aug 2025 05:34:00 -0700 (PDT) From: Anup Patel To: Atish Patra Cc: Palmer Dabbelt , Paul Walmsley , Alexandre Ghiti , Andrew Jones , Anup Patel , Paolo Bonzini , Shuah Khan , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, Anup Patel Subject: [PATCH v2 4/6] RISC-V: KVM: Move copy_sbi_ext_reg_indices() to SBI implementation Date: Sun, 17 Aug 2025 18:03:22 +0530 Message-ID: <20250817123324.239423-5-apatel@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250817123324.239423-1-apatel@ventanamicro.com> References: <20250817123324.239423-1-apatel@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The ONE_REG handling of SBI extension enable/disable registers and SBI extension state registers is already under SBI implementation. On similar lines, let's move copy_sbi_ext_reg_indices() under SBI implementation. Signed-off-by: Anup Patel Reviewed-by: Andrew Jones --- arch/riscv/include/asm/kvm_vcpu_sbi.h | 2 +- arch/riscv/kvm/vcpu_onereg.c | 29 ++------------------------- arch/riscv/kvm/vcpu_sbi.c | 27 ++++++++++++++++++++++++- 3 files changed, 29 insertions(+), 29 deletions(-) diff --git a/arch/riscv/include/asm/kvm_vcpu_sbi.h b/arch/riscv/include/asm= /kvm_vcpu_sbi.h index 8970cc7530c4..d75ca45c0152 100644 --- a/arch/riscv/include/asm/kvm_vcpu_sbi.h +++ b/arch/riscv/include/asm/kvm_vcpu_sbi.h @@ -77,6 +77,7 @@ void kvm_riscv_vcpu_sbi_request_reset(struct kvm_vcpu *vc= pu, unsigned long pc, unsigned long a1); void kvm_riscv_vcpu_sbi_load_reset_state(struct kvm_vcpu *vcpu); int kvm_riscv_vcpu_sbi_return(struct kvm_vcpu *vcpu, struct kvm_run *run); +int kvm_riscv_vcpu_reg_indices_sbi_ext(struct kvm_vcpu *vcpu, u64 __user *= uindices); int kvm_riscv_vcpu_set_reg_sbi_ext(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg); int kvm_riscv_vcpu_get_reg_sbi_ext(struct kvm_vcpu *vcpu, @@ -86,7 +87,6 @@ int kvm_riscv_vcpu_set_reg_sbi(struct kvm_vcpu *vcpu, con= st struct kvm_one_reg * int kvm_riscv_vcpu_get_reg_sbi(struct kvm_vcpu *vcpu, const struct kvm_one= _reg *reg); const struct kvm_vcpu_sbi_extension *kvm_vcpu_sbi_find_ext( struct kvm_vcpu *vcpu, unsigned long extid); -bool riscv_vcpu_supports_sbi_ext(struct kvm_vcpu *vcpu, int idx); int kvm_riscv_vcpu_sbi_ecall(struct kvm_vcpu *vcpu, struct kvm_run *run); void kvm_riscv_vcpu_sbi_init(struct kvm_vcpu *vcpu); void kvm_riscv_vcpu_sbi_deinit(struct kvm_vcpu *vcpu); diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c index 5843b0519224..0894ab517525 100644 --- a/arch/riscv/kvm/vcpu_onereg.c +++ b/arch/riscv/kvm/vcpu_onereg.c @@ -1060,34 +1060,9 @@ static inline unsigned long num_isa_ext_regs(const s= truct kvm_vcpu *vcpu) return copy_isa_ext_reg_indices(vcpu, NULL); } =20 -static int copy_sbi_ext_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uin= dices) -{ - unsigned int n =3D 0; - - for (int i =3D 0; i < KVM_RISCV_SBI_EXT_MAX; i++) { - u64 size =3D IS_ENABLED(CONFIG_32BIT) ? - KVM_REG_SIZE_U32 : KVM_REG_SIZE_U64; - u64 reg =3D KVM_REG_RISCV | size | KVM_REG_RISCV_SBI_EXT | - KVM_REG_RISCV_SBI_SINGLE | i; - - if (!riscv_vcpu_supports_sbi_ext(vcpu, i)) - continue; - - if (uindices) { - if (put_user(reg, uindices)) - return -EFAULT; - uindices++; - } - - n++; - } - - return n; -} - static unsigned long num_sbi_ext_regs(struct kvm_vcpu *vcpu) { - return copy_sbi_ext_reg_indices(vcpu, NULL); + return kvm_riscv_vcpu_reg_indices_sbi_ext(vcpu, NULL); } =20 static inline unsigned long num_sbi_regs(struct kvm_vcpu *vcpu) @@ -1215,7 +1190,7 @@ int kvm_riscv_vcpu_copy_reg_indices(struct kvm_vcpu *= vcpu, return ret; uindices +=3D ret; =20 - ret =3D copy_sbi_ext_reg_indices(vcpu, uindices); + ret =3D kvm_riscv_vcpu_reg_indices_sbi_ext(vcpu, uindices); if (ret < 0) return ret; uindices +=3D ret; diff --git a/arch/riscv/kvm/vcpu_sbi.c b/arch/riscv/kvm/vcpu_sbi.c index 04903e5012d6..1b13623380e1 100644 --- a/arch/riscv/kvm/vcpu_sbi.c +++ b/arch/riscv/kvm/vcpu_sbi.c @@ -110,7 +110,7 @@ riscv_vcpu_get_sbi_ext(struct kvm_vcpu *vcpu, unsigned = long idx) return sext; } =20 -bool riscv_vcpu_supports_sbi_ext(struct kvm_vcpu *vcpu, int idx) +static bool riscv_vcpu_supports_sbi_ext(struct kvm_vcpu *vcpu, int idx) { struct kvm_vcpu_sbi_context *scontext =3D &vcpu->arch.sbi_context; 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Sun, 17 Aug 2025 05:34:06 -0700 (PDT) Received: from localhost.localdomain ([122.171.23.202]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3232b291449sm4480912a91.0.2025.08.17.05.34.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Aug 2025 05:34:05 -0700 (PDT) From: Anup Patel To: Atish Patra Cc: Palmer Dabbelt , Paul Walmsley , Alexandre Ghiti , Andrew Jones , Anup Patel , Paolo Bonzini , Shuah Khan , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, Anup Patel Subject: [PATCH v2 5/6] RISC-V: KVM: Implement ONE_REG interface for SBI FWFT state Date: Sun, 17 Aug 2025 18:03:23 +0530 Message-ID: <20250817123324.239423-6-apatel@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250817123324.239423-1-apatel@ventanamicro.com> References: <20250817123324.239423-1-apatel@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The KVM user-space needs a way to save/restore the state of SBI FWFT features so implement SBI extension ONE_REG callbacks. Signed-off-by: Anup Patel --- arch/riscv/include/uapi/asm/kvm.h | 14 +++ arch/riscv/kvm/vcpu_sbi_fwft.c | 168 +++++++++++++++++++++++++++--- 2 files changed, 170 insertions(+), 12 deletions(-) diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/as= m/kvm.h index a5ca0f4ce2d3..fc5624e89c7b 100644 --- a/arch/riscv/include/uapi/asm/kvm.h +++ b/arch/riscv/include/uapi/asm/kvm.h @@ -215,6 +215,17 @@ struct kvm_riscv_sbi_sta { unsigned long shmem_hi; }; =20 +struct kvm_riscv_sbi_fwft_feature { + unsigned long flags; + unsigned long value; +}; + +/* SBI FWFT extension registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */ +struct kvm_riscv_sbi_fwft { + struct kvm_riscv_sbi_fwft_feature misaligned_deleg; + struct kvm_riscv_sbi_fwft_feature pointer_masking; +}; + /* Possible states for kvm_riscv_timer */ #define KVM_RISCV_TIMER_STATE_OFF 0 #define KVM_RISCV_TIMER_STATE_ON 1 @@ -298,6 +309,9 @@ struct kvm_riscv_sbi_sta { #define KVM_REG_RISCV_SBI_STA (0x0 << KVM_REG_RISCV_SUBTYPE_SHIFT) #define KVM_REG_RISCV_SBI_STA_REG(name) \ (offsetof(struct kvm_riscv_sbi_sta, name) / sizeof(unsigned long)) +#define KVM_REG_RISCV_SBI_FWFT (0x1 << KVM_REG_RISCV_SUBTYPE_SHIFT) +#define KVM_REG_RISCV_SBI_FWFT_REG(name) \ + (offsetof(struct kvm_riscv_sbi_fwft, name) / sizeof(unsigned long)) =20 /* Device Control API: RISC-V AIA */ #define KVM_DEV_RISCV_APLIC_ALIGN 0x1000 diff --git a/arch/riscv/kvm/vcpu_sbi_fwft.c b/arch/riscv/kvm/vcpu_sbi_fwft.c index 5a3bad0f9330..6499a669f9d0 100644 --- a/arch/riscv/kvm/vcpu_sbi_fwft.c +++ b/arch/riscv/kvm/vcpu_sbi_fwft.c @@ -22,6 +22,11 @@ struct kvm_sbi_fwft_feature { */ enum sbi_fwft_feature_t id; =20 + /** + * @flags_reg_num: ONE_REG index of the feature flag + */ + unsigned long flags_reg_num; + /** * @supported: Check if the feature is supported on the vcpu * @@ -44,7 +49,8 @@ struct kvm_sbi_fwft_feature { * * This callback is mandatory */ - long (*set)(struct kvm_vcpu *vcpu, struct kvm_sbi_fwft_config *conf, unsi= gned long value); + long (*set)(struct kvm_vcpu *vcpu, struct kvm_sbi_fwft_config *conf, + bool one_reg_access, unsigned long value); =20 /** * @get: Get the feature current value @@ -53,7 +59,8 @@ struct kvm_sbi_fwft_feature { * * This callback is mandatory */ - long (*get)(struct kvm_vcpu *vcpu, struct kvm_sbi_fwft_config *conf, unsi= gned long *value); + long (*get)(struct kvm_vcpu *vcpu, struct kvm_sbi_fwft_config *conf, + bool one_reg_access, unsigned long *value); }; =20 static const enum sbi_fwft_feature_t kvm_fwft_defined_features[] =3D { @@ -91,16 +98,18 @@ static void kvm_sbi_fwft_reset_misaligned_delegation(st= ruct kvm_vcpu *vcpu) =20 static long kvm_sbi_fwft_set_misaligned_delegation(struct kvm_vcpu *vcpu, struct kvm_sbi_fwft_config *conf, - unsigned long value) + bool one_reg_access, unsigned long value) { struct kvm_vcpu_config *cfg =3D &vcpu->arch.cfg; =20 if (value =3D=3D 1) { cfg->hedeleg |=3D MIS_DELEG; - csr_set(CSR_HEDELEG, MIS_DELEG); + if (!one_reg_access) + csr_set(CSR_HEDELEG, MIS_DELEG); } else if (value =3D=3D 0) { cfg->hedeleg &=3D ~MIS_DELEG; - csr_clear(CSR_HEDELEG, MIS_DELEG); + if (!one_reg_access) + csr_clear(CSR_HEDELEG, MIS_DELEG); } else { return SBI_ERR_INVALID_PARAM; } @@ -110,10 +119,11 @@ static long kvm_sbi_fwft_set_misaligned_delegation(st= ruct kvm_vcpu *vcpu, =20 static long kvm_sbi_fwft_get_misaligned_delegation(struct kvm_vcpu *vcpu, struct kvm_sbi_fwft_config *conf, - unsigned long *value) + bool one_reg_access, unsigned long *value) { - *value =3D (csr_read(CSR_HEDELEG) & MIS_DELEG) =3D=3D MIS_DELEG; + struct kvm_vcpu_config *cfg =3D &vcpu->arch.cfg; =20 + *value =3D (cfg->hedeleg & MIS_DELEG) =3D=3D MIS_DELEG; return SBI_SUCCESS; } =20 @@ -145,7 +155,7 @@ static void kvm_sbi_fwft_reset_pointer_masking_pmlen(st= ruct kvm_vcpu *vcpu) =20 static long kvm_sbi_fwft_set_pointer_masking_pmlen(struct kvm_vcpu *vcpu, struct kvm_sbi_fwft_config *conf, - unsigned long value) + bool one_reg_access, unsigned long value) { struct kvm_sbi_fwft *fwft =3D vcpu_to_fwft(vcpu); unsigned long pmm; @@ -167,14 +177,15 @@ static long kvm_sbi_fwft_set_pointer_masking_pmlen(st= ruct kvm_vcpu *vcpu, * update here so that VCPU see's pointer masking mode change * immediately. */ - csr_write(CSR_HENVCFG, vcpu->arch.cfg.henvcfg); + if (!one_reg_access) + csr_write(CSR_HENVCFG, vcpu->arch.cfg.henvcfg); =20 return SBI_SUCCESS; } =20 static long kvm_sbi_fwft_get_pointer_masking_pmlen(struct kvm_vcpu *vcpu, struct kvm_sbi_fwft_config *conf, - unsigned long *value) + bool one_reg_access, unsigned long *value) { switch (vcpu->arch.cfg.henvcfg & ENVCFG_PMM) { case ENVCFG_PMM_PMLEN_0: @@ -198,6 +209,8 @@ static long kvm_sbi_fwft_get_pointer_masking_pmlen(stru= ct kvm_vcpu *vcpu, static const struct kvm_sbi_fwft_feature features[] =3D { { .id =3D SBI_FWFT_MISALIGNED_EXC_DELEG, + .flags_reg_num =3D offsetof(struct kvm_riscv_sbi_fwft, misaligned_deleg.= flags) / + sizeof(unsigned long), .supported =3D kvm_sbi_fwft_misaligned_delegation_supported, .reset =3D kvm_sbi_fwft_reset_misaligned_delegation, .set =3D kvm_sbi_fwft_set_misaligned_delegation, @@ -206,6 +219,8 @@ static const struct kvm_sbi_fwft_feature features[] =3D= { #ifndef CONFIG_32BIT { .id =3D SBI_FWFT_POINTER_MASKING_PMLEN, + .flags_reg_num =3D offsetof(struct kvm_riscv_sbi_fwft, pointer_masking.f= lags) / + sizeof(unsigned long), .supported =3D kvm_sbi_fwft_pointer_masking_pmlen_supported, .reset =3D kvm_sbi_fwft_reset_pointer_masking_pmlen, .set =3D kvm_sbi_fwft_set_pointer_masking_pmlen, @@ -214,6 +229,21 @@ static const struct kvm_sbi_fwft_feature features[] = =3D { #endif }; =20 +static const struct kvm_sbi_fwft_feature *kvm_sbi_fwft_regnum_to_feature(u= nsigned long reg_num) +{ + const struct kvm_sbi_fwft_feature *feature; + int i; + + for (i =3D 0; i < ARRAY_SIZE(features); i++) { + feature =3D &features[i]; + if (feature->flags_reg_num =3D=3D reg_num || + (feature->flags_reg_num + 1) =3D=3D reg_num) + return feature; + } + + return NULL; +} + static struct kvm_sbi_fwft_config * kvm_sbi_fwft_get_config(struct kvm_vcpu *vcpu, enum sbi_fwft_feature_t fea= ture) { @@ -267,7 +297,7 @@ static int kvm_sbi_fwft_set(struct kvm_vcpu *vcpu, u32 = feature, =20 conf->flags =3D flags; =20 - return conf->feature->set(vcpu, conf, value); + return conf->feature->set(vcpu, conf, false, value); } =20 static int kvm_sbi_fwft_get(struct kvm_vcpu *vcpu, unsigned long feature, @@ -280,7 +310,7 @@ static int kvm_sbi_fwft_get(struct kvm_vcpu *vcpu, unsi= gned long feature, if (ret) return ret; =20 - return conf->feature->get(vcpu, conf, value); + return conf->feature->get(vcpu, conf, false, value); } =20 static int kvm_sbi_ext_fwft_handler(struct kvm_vcpu *vcpu, struct kvm_run = *run, @@ -354,6 +384,115 @@ static void kvm_sbi_ext_fwft_reset(struct kvm_vcpu *v= cpu) } } =20 +static unsigned long kvm_sbi_ext_fwft_get_reg_count(struct kvm_vcpu *vcpu) +{ + unsigned long max_reg_count =3D sizeof(struct kvm_riscv_sbi_fwft) / sizeo= f(unsigned long); + const struct kvm_sbi_fwft_feature *feature; + struct kvm_sbi_fwft_config *conf; + unsigned long reg, ret =3D 0; + + for (reg =3D 0; reg < max_reg_count; reg++) { + feature =3D kvm_sbi_fwft_regnum_to_feature(reg); + if (!feature) + continue; + + conf =3D kvm_sbi_fwft_get_config(vcpu, feature->id); + if (!conf || !conf->supported) + continue; + + ret++; + } + + return ret; +} + +static int kvm_sbi_ext_fwft_get_reg_id(struct kvm_vcpu *vcpu, int index, u= 64 *reg_id) +{ + int reg, max_reg_count =3D sizeof(struct kvm_riscv_sbi_fwft) / sizeof(uns= igned long); + const struct kvm_sbi_fwft_feature *feature; + struct kvm_sbi_fwft_config *conf; + int idx =3D 0; + + for (reg =3D 0; reg < max_reg_count; reg++) { + feature =3D kvm_sbi_fwft_regnum_to_feature(reg); + if (!feature) + continue; + + conf =3D kvm_sbi_fwft_get_config(vcpu, feature->id); + if (!conf || !conf->supported) + continue; + + if (index =3D=3D idx) { + *reg_id =3D KVM_REG_RISCV | + (IS_ENABLED(CONFIG_32BIT) ? + KVM_REG_SIZE_U32 : KVM_REG_SIZE_U64) | + KVM_REG_RISCV_SBI_STATE | + KVM_REG_RISCV_SBI_FWFT | reg; + return 0; + } + + idx++; + } + + return -ENOENT; +} + +static int kvm_sbi_ext_fwft_get_reg(struct kvm_vcpu *vcpu, unsigned long r= eg_num, + unsigned long reg_size, void *reg_val) +{ + const struct kvm_sbi_fwft_feature *feature; + struct kvm_sbi_fwft_config *conf; + unsigned long *value; + int ret =3D 0; + + if (reg_size !=3D sizeof(unsigned long)) + return -EINVAL; + value =3D reg_val; + + feature =3D kvm_sbi_fwft_regnum_to_feature(reg_num); + if (!feature) + return -ENOENT; + + conf =3D kvm_sbi_fwft_get_config(vcpu, feature->id); + if (!conf || !conf->supported) + return -ENOENT; + + if (feature->flags_reg_num =3D=3D reg_num) + *value =3D conf->flags; + else + ret =3D conf->feature->get(vcpu, conf, true, value); + + return sbi_err_map_linux_errno(ret); +} + +static int kvm_sbi_ext_fwft_set_reg(struct kvm_vcpu *vcpu, unsigned long r= eg_num, + unsigned long reg_size, const void *reg_val) +{ + const struct kvm_sbi_fwft_feature *feature; + struct kvm_sbi_fwft_config *conf; + unsigned long value; + int ret =3D 0; + + if (reg_size !=3D sizeof(unsigned long)) + return -EINVAL; + value =3D *(const unsigned long *)reg_val; + + feature =3D kvm_sbi_fwft_regnum_to_feature(reg_num); + if (!feature) + return -ENOENT; + + conf =3D kvm_sbi_fwft_get_config(vcpu, feature->id); + if (!conf || !conf->supported) + return -ENOENT; + + if (feature->flags_reg_num =3D=3D reg_num) + conf->flags =3D value & SBI_FWFT_SET_FLAG_LOCK; + else + ret =3D conf->feature->set(vcpu, conf, true, value); + + return sbi_err_map_linux_errno(ret); +} + const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_fwft =3D { .extid_start =3D SBI_EXT_FWFT, .extid_end =3D SBI_EXT_FWFT, @@ -361,4 +500,9 @@ const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_fwft = =3D { .init =3D kvm_sbi_ext_fwft_init, .deinit =3D kvm_sbi_ext_fwft_deinit, .reset =3D kvm_sbi_ext_fwft_reset, + .state_reg_subtype =3D KVM_REG_RISCV_SBI_FWFT, + .get_state_reg_count =3D kvm_sbi_ext_fwft_get_reg_count, + .get_state_reg_id =3D kvm_sbi_ext_fwft_get_reg_id, + .get_state_reg =3D kvm_sbi_ext_fwft_get_reg, + .set_state_reg =3D kvm_sbi_ext_fwft_set_reg, }; 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Sun, 17 Aug 2025 05:34:10 -0700 (PDT) From: Anup Patel To: Atish Patra Cc: Palmer Dabbelt , Paul Walmsley , Alexandre Ghiti , Andrew Jones , Anup Patel , Paolo Bonzini , Shuah Khan , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, Anup Patel Subject: [PATCH v2 6/6] KVM: riscv: selftests: Add SBI FWFT to get-reg-list test Date: Sun, 17 Aug 2025 18:03:24 +0530 Message-ID: <20250817123324.239423-7-apatel@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250817123324.239423-1-apatel@ventanamicro.com> References: <20250817123324.239423-1-apatel@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" KVM RISC-V now supports SBI FWFT, so add it to the get-reg-list test. Signed-off-by: Anup Patel --- .../selftests/kvm/riscv/get-reg-list.c | 28 +++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c b/tools/testi= ng/selftests/kvm/riscv/get-reg-list.c index a0b7dabb5040..1bc84f09b4ee 100644 --- a/tools/testing/selftests/kvm/riscv/get-reg-list.c +++ b/tools/testing/selftests/kvm/riscv/get-reg-list.c @@ -128,6 +128,7 @@ bool filter_reg(__u64 reg) case KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT= _DBCN: case KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT= _SUSP: case KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT= _STA: + case KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT= _FWFT: case KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT= _EXPERIMENTAL: case KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT= _VENDOR: return true; @@ -627,6 +628,7 @@ static const char *sbi_ext_single_id_to_str(__u64 reg_o= ff) KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_DBCN), KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_SUSP), KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_STA), + KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_FWFT), KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_EXPERIMENTAL), KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_VENDOR), }; @@ -683,6 +685,17 @@ static const char *sbi_sta_id_to_str(__u64 reg_off) return strdup_printf("KVM_REG_RISCV_SBI_STA | %lld /* UNKNOWN */", reg_of= f); } =20 +static const char *sbi_fwft_id_to_str(__u64 reg_off) +{ + switch (reg_off) { + case 0: return "KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(misal= igned_deleg.flags)"; + case 1: return "KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(misal= igned_deleg.value)"; + case 2: return "KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(point= er_masking.flags)"; + case 3: return "KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(point= er_masking.value)"; + } + return strdup_printf("KVM_REG_RISCV_SBI_STA | %lld /* UNKNOWN */", reg_of= f); +} + static const char *sbi_id_to_str(const char *prefix, __u64 id) { __u64 reg_off =3D id & ~(REG_MASK | KVM_REG_RISCV_SBI_STATE); @@ -695,6 +708,8 @@ static const char *sbi_id_to_str(const char *prefix, __= u64 id) switch (reg_subtype) { case KVM_REG_RISCV_SBI_STA: return sbi_sta_id_to_str(reg_off); + case KVM_REG_RISCV_SBI_FWFT: + return sbi_fwft_id_to_str(reg_off); } =20 return strdup_printf("%lld | %lld /* UNKNOWN */", reg_subtype, reg_off); @@ -859,6 +874,14 @@ static __u64 sbi_sta_regs[] =3D { KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RI= SCV_SBI_STA | KVM_REG_RISCV_SBI_STA_REG(shmem_hi), }; =20 +static __u64 sbi_fwft_regs[] =3D { + KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISC= V_SBI_SINGLE | KVM_RISCV_SBI_EXT_FWFT, + KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RI= SCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(misaligned_deleg.flags), + KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RI= SCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(misaligned_deleg.value), + KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RI= SCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(pointer_masking.flags), + KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RI= SCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(pointer_masking.value), +}; + static __u64 zicbom_regs[] =3D { KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV= _CONFIG_REG(zicbom_block_size), KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_REG_RISC= V_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICBOM, @@ -1010,6 +1033,9 @@ static __u64 vector_regs[] =3D { #define SUBLIST_SBI_STA \ {"sbi-sta", .feature_type =3D VCPU_FEATURE_SBI_EXT, .feature =3D KVM_RISC= V_SBI_EXT_STA, \ .regs =3D sbi_sta_regs, .regs_n =3D ARRAY_SIZE(sbi_sta_regs),} +#define SUBLIST_SBI_FWFT \ + {"sbi-fwft", .feature_type =3D VCPU_FEATURE_SBI_EXT, .feature =3D KVM_RIS= CV_SBI_EXT_FWFT, \ + .regs =3D sbi_fwft_regs, .regs_n =3D ARRAY_SIZE(sbi_fwft_regs),} #define SUBLIST_ZICBOM \ {"zicbom", .feature =3D KVM_RISCV_ISA_EXT_ZICBOM, .regs =3D zicbom_regs, = .regs_n =3D ARRAY_SIZE(zicbom_regs),} #define SUBLIST_ZICBOZ \ @@ -1092,6 +1118,7 @@ KVM_SBI_EXT_SUBLIST_CONFIG(sta, STA); KVM_SBI_EXT_SIMPLE_CONFIG(pmu, PMU); KVM_SBI_EXT_SIMPLE_CONFIG(dbcn, DBCN); KVM_SBI_EXT_SIMPLE_CONFIG(susp, SUSP); +KVM_SBI_EXT_SUBLIST_CONFIG(fwft, FWFT); =20 KVM_ISA_EXT_SUBLIST_CONFIG(aia, AIA); KVM_ISA_EXT_SUBLIST_CONFIG(fp_f, FP_F); @@ -1167,6 +1194,7 @@ struct vcpu_reg_list *vcpu_configs[] =3D { &config_sbi_pmu, &config_sbi_dbcn, &config_sbi_susp, + &config_sbi_fwft, &config_aia, &config_fp_f, &config_fp_d, --=20 2.43.0