From nobody Sat Oct 4 14:13:11 2025 Received: from szxga04-in.huawei.com (szxga04-in.huawei.com [45.249.212.190]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F26D3291C22; Sat, 16 Aug 2025 10:28:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.190 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755340122; cv=none; b=YHkabPKOjzW4PJmjYK7XWaKvgWKQUWYX60Wcyo51YhsbPb3K2VLKjRyJahRea3VPVsjNhkzci2qSLUEALL25FQhg3HXdUV0CSJLlqIRCVMRDMqRPlRPEa6s9PMQnOlQmt11g2dUhbDE3VLIq8H+3NOpnGFu787F12BGMJ6Zg97c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755340122; c=relaxed/simple; bh=6OLBgmRUR9ef2I5Ll4tjclR1x12JVbuA0qXBgvqkx28=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=e/Wfbu8yAd7rutzn86emAU9fg9nvDhPeXiWVptyf0QE099iXfbzBJQpS524EXxlh4ioWaikwgvvv+u2fYoqcqxp6YzE6c1kpj1uZdG0g3LMzR5PpaYm+y7QWQsZiHEcKDtRLUBKIYcH+r9EWuimxGG4DaymNx1JiCobpAs6GJmY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; arc=none smtp.client-ip=45.249.212.190 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.19.88.214]) by szxga04-in.huawei.com (SkyGuard) with ESMTP id 4c3w7g6LxCz2Cfw6; Sat, 16 Aug 2025 18:24:15 +0800 (CST) Received: from dggemv712-chm.china.huawei.com (unknown [10.1.198.32]) by mail.maildlp.com (Postfix) with ESMTPS id D82031A016C; Sat, 16 Aug 2025 18:28:36 +0800 (CST) Received: from kwepemq200001.china.huawei.com (7.202.195.16) by dggemv712-chm.china.huawei.com (10.1.198.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Sat, 16 Aug 2025 18:28:36 +0800 Received: from localhost.huawei.com (10.90.31.46) by kwepemq200001.china.huawei.com (7.202.195.16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Sat, 16 Aug 2025 18:28:35 +0800 From: Chenghai Huang To: , CC: , , , , , , , Subject: [PATCH 2/6] crypto: hisilicon/zip - remove unnecessary validation for high-performance mode configurations Date: Sat, 16 Aug 2025 18:28:30 +0800 Message-ID: <20250816102834.828655-3-huangchenghai2@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20250816102834.828655-1-huangchenghai2@huawei.com> References: <20250816102834.828655-1-huangchenghai2@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: kwepems500002.china.huawei.com (7.221.188.17) To kwepemq200001.china.huawei.com (7.202.195.16) Content-Type: text/plain; charset="utf-8" When configuring the high-performance mode register, there is no need to verify whether the register has been successfully enabled, as there is no possibility of a write failure for this register. Fixes: a9864bae1806 ("crypto: hisilicon/zip - add zip comp high perf mode c= onfiguration") Signed-off-by: Chenghai Huang --- drivers/crypto/hisilicon/zip/zip_main.c | 16 +++------------- 1 file changed, 3 insertions(+), 13 deletions(-) diff --git a/drivers/crypto/hisilicon/zip/zip_main.c b/drivers/crypto/hisil= icon/zip/zip_main.c index 96687c78a8dc..744f5a0197c3 100644 --- a/drivers/crypto/hisilicon/zip/zip_main.c +++ b/drivers/crypto/hisilicon/zip/zip_main.c @@ -448,10 +448,9 @@ bool hisi_zip_alg_support(struct hisi_qm *qm, u32 alg) return false; } =20 -static int hisi_zip_set_high_perf(struct hisi_qm *qm) +static void hisi_zip_set_high_perf(struct hisi_qm *qm) { u32 val; - int ret; =20 val =3D readl_relaxed(qm->io_base + HZIP_HIGH_PERF_OFFSET); if (perf_mode =3D=3D HZIP_HIGH_COMP_PERF) @@ -461,13 +460,6 @@ static int hisi_zip_set_high_perf(struct hisi_qm *qm) =20 /* Set perf mode */ writel(val, qm->io_base + HZIP_HIGH_PERF_OFFSET); - ret =3D readl_relaxed_poll_timeout(qm->io_base + HZIP_HIGH_PERF_OFFSET, - val, val =3D=3D perf_mode, HZIP_DELAY_1_US, - HZIP_POLL_TIMEOUT_US); - if (ret) - pci_err(qm->pdev, "failed to set perf mode\n"); - - return ret; } =20 static void hisi_zip_open_sva_prefetch(struct hisi_qm *qm) @@ -581,6 +573,8 @@ static int hisi_zip_set_user_domain_and_cache(struct hi= si_qm *qm) CQC_CACHE_WB_ENABLE | FIELD_PREP(SQC_CACHE_WB_THRD, 1) | FIELD_PREP(CQC_CACHE_WB_THRD, 1), base + QM_CACHE_CTL); =20 + hisi_zip_set_high_perf(qm); + hisi_zip_enable_clock_gate(qm); =20 return hisi_dae_set_user_domain(qm); @@ -1252,10 +1246,6 @@ static int hisi_zip_pf_probe_init(struct hisi_zip *h= isi_zip) if (ret) return ret; =20 - ret =3D hisi_zip_set_high_perf(qm); - if (ret) - return ret; - hisi_qm_dev_err_init(qm); hisi_zip_debug_regs_clear(qm); =20 --=20 2.33.0