From nobody Sat Oct 4 12:46:56 2025 Received: from szxga05-in.huawei.com (szxga05-in.huawei.com [45.249.212.191]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4CBA5299A83; Sat, 16 Aug 2025 10:28:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.191 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755340126; cv=none; b=ag0R19NCYUi/9frJAFNnmM2rIVzgeCwhBnbncEUnRSolj2byhOitwjvxXa7WpBWQbuFDpLEOexgH6pHXj+gDdfgqDw8BvLuZ4ING0Wtj/wg2B0htvZD1et/1HprWWtcYU6SdU0OOg/ztHdxw7r64tp1PuRV1zjhQiM8D3b9lK7I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755340126; c=relaxed/simple; bh=jxcxCv+UtSpKj1BcxQWYKJ6rQt9/PuHHt0gIdTKocwU=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=jZYIhYSlAsQYdDYAUeCUX6vYfF6GnxCZ61qeWA9Zv1oCAzE3ZeC3USQHhAJvUtiONp9jmzNAny11kgGNarxwzo1jWrIacmdo2ifAd2IZ5SEIXM0aQgw1F+OUu1oFyTsZB75AJRa4RGWnPRHBWlfvkn8rtAAPPobL7fnQTmD+aJI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; arc=none smtp.client-ip=45.249.212.191 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.19.163.17]) by szxga05-in.huawei.com (SkyGuard) with ESMTP id 4c3w9X5x1Pz2Dc0v; Sat, 16 Aug 2025 18:25:52 +0800 (CST) Received: from dggemv706-chm.china.huawei.com (unknown [10.3.19.33]) by mail.maildlp.com (Postfix) with ESMTPS id 6B37A1A0188; Sat, 16 Aug 2025 18:28:36 +0800 (CST) Received: from kwepemq200001.china.huawei.com (7.202.195.16) by dggemv706-chm.china.huawei.com (10.3.19.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Sat, 16 Aug 2025 18:28:36 +0800 Received: from localhost.huawei.com (10.90.31.46) by kwepemq200001.china.huawei.com (7.202.195.16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Sat, 16 Aug 2025 18:28:35 +0800 From: Chenghai Huang To: , CC: , , , , , , , Subject: [PATCH 1/6] crypto: hisilicon - re-enable address prefetch after device resuming Date: Sat, 16 Aug 2025 18:28:29 +0800 Message-ID: <20250816102834.828655-2-huangchenghai2@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20250816102834.828655-1-huangchenghai2@huawei.com> References: <20250816102834.828655-1-huangchenghai2@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: kwepems500002.china.huawei.com (7.221.188.17) To kwepemq200001.china.huawei.com (7.202.195.16) Content-Type: text/plain; charset="utf-8" When the device resumes from a suspended state, it will revert to its initial state and requires re-enabling. Currently, the address prefetch function is not re-enabled after device resuming. Move the address prefetch enable to the initialization process. In this way, the address prefetch can be enabled when the device resumes by calling the initialization process. Fixes: 607c191b371d ("crypto: hisilicon - support runtime PM for accelerato= r device") Signed-off-by: Chenghai Huang --- drivers/crypto/hisilicon/hpre/hpre_main.c | 86 +++++++++++------------ drivers/crypto/hisilicon/qm.c | 3 - drivers/crypto/hisilicon/sec2/sec_main.c | 80 ++++++++++----------- drivers/crypto/hisilicon/zip/zip_main.c | 2 +- 4 files changed, 84 insertions(+), 87 deletions(-) diff --git a/drivers/crypto/hisilicon/hpre/hpre_main.c b/drivers/crypto/his= ilicon/hpre/hpre_main.c index f5b47e5ff48a..dbe8f62f556b 100644 --- a/drivers/crypto/hisilicon/hpre/hpre_main.c +++ b/drivers/crypto/hisilicon/hpre/hpre_main.c @@ -466,6 +466,47 @@ struct hisi_qp *hpre_create_qp(u8 type) return NULL; } =20 +static void hpre_close_sva_prefetch(struct hisi_qm *qm) +{ + u32 val; + int ret; + + if (!test_bit(QM_SUPPORT_SVA_PREFETCH, &qm->caps)) + return; + + val =3D readl_relaxed(qm->io_base + HPRE_PREFETCH_CFG); + val |=3D HPRE_PREFETCH_DISABLE; + writel(val, qm->io_base + HPRE_PREFETCH_CFG); + + ret =3D readl_relaxed_poll_timeout(qm->io_base + HPRE_SVA_PREFTCH_DFX, + val, !(val & HPRE_SVA_DISABLE_READY), + HPRE_REG_RD_INTVRL_US, + HPRE_REG_RD_TMOUT_US); + if (ret) + pci_err(qm->pdev, "failed to close sva prefetch\n"); +} + +static void hpre_open_sva_prefetch(struct hisi_qm *qm) +{ + u32 val; + int ret; + + if (!test_bit(QM_SUPPORT_SVA_PREFETCH, &qm->caps)) + return; + + /* Enable prefetch */ + val =3D readl_relaxed(qm->io_base + HPRE_PREFETCH_CFG); + val &=3D HPRE_PREFETCH_ENABLE; + writel(val, qm->io_base + HPRE_PREFETCH_CFG); + + ret =3D readl_relaxed_poll_timeout(qm->io_base + HPRE_PREFETCH_CFG, + val, !(val & HPRE_PREFETCH_DISABLE), + HPRE_REG_RD_INTVRL_US, + HPRE_REG_RD_TMOUT_US); + if (ret) + pci_err(qm->pdev, "failed to open sva prefetch\n"); +} + static void hpre_config_pasid(struct hisi_qm *qm) { u32 val1, val2; @@ -484,6 +525,8 @@ static void hpre_config_pasid(struct hisi_qm *qm) } writel_relaxed(val1, qm->io_base + HPRE_DATA_RUSER_CFG); writel_relaxed(val2, qm->io_base + HPRE_DATA_WUSER_CFG); + + hpre_open_sva_prefetch(qm); } =20 static int hpre_cfg_by_dsm(struct hisi_qm *qm) @@ -563,47 +606,6 @@ static void disable_flr_of_bme(struct hisi_qm *qm) writel(PEH_AXUSER_CFG_ENABLE, qm->io_base + QM_PEH_AXUSER_CFG_ENABLE); } =20 -static void hpre_open_sva_prefetch(struct hisi_qm *qm) -{ - u32 val; - int ret; - - if (!test_bit(QM_SUPPORT_SVA_PREFETCH, &qm->caps)) - return; - - /* Enable prefetch */ - val =3D readl_relaxed(qm->io_base + HPRE_PREFETCH_CFG); - val &=3D HPRE_PREFETCH_ENABLE; - writel(val, qm->io_base + HPRE_PREFETCH_CFG); - - ret =3D readl_relaxed_poll_timeout(qm->io_base + HPRE_PREFETCH_CFG, - val, !(val & HPRE_PREFETCH_DISABLE), - HPRE_REG_RD_INTVRL_US, - HPRE_REG_RD_TMOUT_US); - if (ret) - pci_err(qm->pdev, "failed to open sva prefetch\n"); -} - -static void hpre_close_sva_prefetch(struct hisi_qm *qm) -{ - u32 val; - int ret; - - if (!test_bit(QM_SUPPORT_SVA_PREFETCH, &qm->caps)) - return; - - val =3D readl_relaxed(qm->io_base + HPRE_PREFETCH_CFG); - val |=3D HPRE_PREFETCH_DISABLE; - writel(val, qm->io_base + HPRE_PREFETCH_CFG); - - ret =3D readl_relaxed_poll_timeout(qm->io_base + HPRE_SVA_PREFTCH_DFX, - val, !(val & HPRE_SVA_DISABLE_READY), - HPRE_REG_RD_INTVRL_US, - HPRE_REG_RD_TMOUT_US); - if (ret) - pci_err(qm->pdev, "failed to close sva prefetch\n"); -} - static void hpre_enable_clock_gate(struct hisi_qm *qm) { unsigned long offset; @@ -1450,8 +1452,6 @@ static int hpre_pf_probe_init(struct hpre *hpre) if (ret) return ret; =20 - hpre_open_sva_prefetch(qm); - hisi_qm_dev_err_init(qm); ret =3D hpre_show_last_regs_init(qm); if (ret) diff --git a/drivers/crypto/hisilicon/qm.c b/drivers/crypto/hisilicon/qm.c index 2e4ee7ecfdfb..a5cc0ccd94f1 100644 --- a/drivers/crypto/hisilicon/qm.c +++ b/drivers/crypto/hisilicon/qm.c @@ -4447,9 +4447,6 @@ static void qm_restart_prepare(struct hisi_qm *qm) { u32 value; =20 - if (qm->err_ini->open_sva_prefetch) - qm->err_ini->open_sva_prefetch(qm); - if (qm->ver >=3D QM_HW_V3) return; =20 diff --git a/drivers/crypto/hisilicon/sec2/sec_main.c b/drivers/crypto/hisi= licon/sec2/sec_main.c index 72cf48d1f3ab..ddb20f380b54 100644 --- a/drivers/crypto/hisilicon/sec2/sec_main.c +++ b/drivers/crypto/hisilicon/sec2/sec_main.c @@ -464,6 +464,45 @@ static void sec_set_endian(struct hisi_qm *qm) writel_relaxed(reg, qm->io_base + SEC_CONTROL_REG); } =20 +static void sec_close_sva_prefetch(struct hisi_qm *qm) +{ + u32 val; + int ret; + + if (!test_bit(QM_SUPPORT_SVA_PREFETCH, &qm->caps)) + return; + + val =3D readl_relaxed(qm->io_base + SEC_PREFETCH_CFG); + val |=3D SEC_PREFETCH_DISABLE; + writel(val, qm->io_base + SEC_PREFETCH_CFG); + + ret =3D readl_relaxed_poll_timeout(qm->io_base + SEC_SVA_TRANS, + val, !(val & SEC_SVA_DISABLE_READY), + SEC_DELAY_10_US, SEC_POLL_TIMEOUT_US); + if (ret) + pci_err(qm->pdev, "failed to close sva prefetch\n"); +} + +static void sec_open_sva_prefetch(struct hisi_qm *qm) +{ + u32 val; + int ret; + + if (!test_bit(QM_SUPPORT_SVA_PREFETCH, &qm->caps)) + return; + + /* Enable prefetch */ + val =3D readl_relaxed(qm->io_base + SEC_PREFETCH_CFG); + val &=3D SEC_PREFETCH_ENABLE; + writel(val, qm->io_base + SEC_PREFETCH_CFG); + + ret =3D readl_relaxed_poll_timeout(qm->io_base + SEC_PREFETCH_CFG, + val, !(val & SEC_PREFETCH_DISABLE), + SEC_DELAY_10_US, SEC_POLL_TIMEOUT_US); + if (ret) + pci_err(qm->pdev, "failed to open sva prefetch\n"); +} + static void sec_engine_sva_config(struct hisi_qm *qm) { u32 reg; @@ -497,45 +536,7 @@ static void sec_engine_sva_config(struct hisi_qm *qm) writel_relaxed(reg, qm->io_base + SEC_INTERFACE_USER_CTRL1_REG); } -} - -static void sec_open_sva_prefetch(struct hisi_qm *qm) -{ - u32 val; - int ret; - - if (!test_bit(QM_SUPPORT_SVA_PREFETCH, &qm->caps)) - return; - - /* Enable prefetch */ - val =3D readl_relaxed(qm->io_base + SEC_PREFETCH_CFG); - val &=3D SEC_PREFETCH_ENABLE; - writel(val, qm->io_base + SEC_PREFETCH_CFG); - - ret =3D readl_relaxed_poll_timeout(qm->io_base + SEC_PREFETCH_CFG, - val, !(val & SEC_PREFETCH_DISABLE), - SEC_DELAY_10_US, SEC_POLL_TIMEOUT_US); - if (ret) - pci_err(qm->pdev, "failed to open sva prefetch\n"); -} - -static void sec_close_sva_prefetch(struct hisi_qm *qm) -{ - u32 val; - int ret; - - if (!test_bit(QM_SUPPORT_SVA_PREFETCH, &qm->caps)) - return; - - val =3D readl_relaxed(qm->io_base + SEC_PREFETCH_CFG); - val |=3D SEC_PREFETCH_DISABLE; - writel(val, qm->io_base + SEC_PREFETCH_CFG); - - ret =3D readl_relaxed_poll_timeout(qm->io_base + SEC_SVA_TRANS, - val, !(val & SEC_SVA_DISABLE_READY), - SEC_DELAY_10_US, SEC_POLL_TIMEOUT_US); - if (ret) - pci_err(qm->pdev, "failed to close sva prefetch\n"); + sec_open_sva_prefetch(qm); } =20 static void sec_enable_clock_gate(struct hisi_qm *qm) @@ -1152,7 +1153,6 @@ static int sec_pf_probe_init(struct sec_dev *sec) if (ret) return ret; =20 - sec_open_sva_prefetch(qm); hisi_qm_dev_err_init(qm); sec_debug_regs_clear(qm); ret =3D sec_show_last_regs_init(qm); diff --git a/drivers/crypto/hisilicon/zip/zip_main.c b/drivers/crypto/hisil= icon/zip/zip_main.c index d8ba23b7cc7d..96687c78a8dc 100644 --- a/drivers/crypto/hisilicon/zip/zip_main.c +++ b/drivers/crypto/hisilicon/zip/zip_main.c @@ -565,6 +565,7 @@ static int hisi_zip_set_user_domain_and_cache(struct hi= si_qm *qm) writel(AXUSER_BASE, base + HZIP_DATA_WUSER_32_63); writel(AXUSER_BASE, base + HZIP_SGL_RUSER_32_63); } + hisi_zip_open_sva_prefetch(qm); =20 /* let's open all compression/decompression cores */ =20 @@ -1255,7 +1256,6 @@ static int hisi_zip_pf_probe_init(struct hisi_zip *hi= si_zip) if (ret) return ret; =20 - hisi_zip_open_sva_prefetch(qm); hisi_qm_dev_err_init(qm); hisi_zip_debug_regs_clear(qm); =20 --=20 2.33.0 From nobody Sat Oct 4 12:46:56 2025 Received: from szxga04-in.huawei.com (szxga04-in.huawei.com [45.249.212.190]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F26D3291C22; Sat, 16 Aug 2025 10:28:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.190 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755340122; cv=none; b=YHkabPKOjzW4PJmjYK7XWaKvgWKQUWYX60Wcyo51YhsbPb3K2VLKjRyJahRea3VPVsjNhkzci2qSLUEALL25FQhg3HXdUV0CSJLlqIRCVMRDMqRPlRPEa6s9PMQnOlQmt11g2dUhbDE3VLIq8H+3NOpnGFu787F12BGMJ6Zg97c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755340122; c=relaxed/simple; bh=6OLBgmRUR9ef2I5Ll4tjclR1x12JVbuA0qXBgvqkx28=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; 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Sat, 16 Aug 2025 18:28:36 +0800 Received: from localhost.huawei.com (10.90.31.46) by kwepemq200001.china.huawei.com (7.202.195.16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Sat, 16 Aug 2025 18:28:35 +0800 From: Chenghai Huang To: , CC: , , , , , , , Subject: [PATCH 2/6] crypto: hisilicon/zip - remove unnecessary validation for high-performance mode configurations Date: Sat, 16 Aug 2025 18:28:30 +0800 Message-ID: <20250816102834.828655-3-huangchenghai2@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20250816102834.828655-1-huangchenghai2@huawei.com> References: <20250816102834.828655-1-huangchenghai2@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: kwepems500002.china.huawei.com (7.221.188.17) To kwepemq200001.china.huawei.com (7.202.195.16) Content-Type: text/plain; charset="utf-8" When configuring the high-performance mode register, there is no need to verify whether the register has been successfully enabled, as there is no possibility of a write failure for this register. Fixes: a9864bae1806 ("crypto: hisilicon/zip - add zip comp high perf mode c= onfiguration") Signed-off-by: Chenghai Huang --- drivers/crypto/hisilicon/zip/zip_main.c | 16 +++------------- 1 file changed, 3 insertions(+), 13 deletions(-) diff --git a/drivers/crypto/hisilicon/zip/zip_main.c b/drivers/crypto/hisil= icon/zip/zip_main.c index 96687c78a8dc..744f5a0197c3 100644 --- a/drivers/crypto/hisilicon/zip/zip_main.c +++ b/drivers/crypto/hisilicon/zip/zip_main.c @@ -448,10 +448,9 @@ bool hisi_zip_alg_support(struct hisi_qm *qm, u32 alg) return false; } =20 -static int hisi_zip_set_high_perf(struct hisi_qm *qm) +static void hisi_zip_set_high_perf(struct hisi_qm *qm) { u32 val; - int ret; =20 val =3D readl_relaxed(qm->io_base + HZIP_HIGH_PERF_OFFSET); if (perf_mode =3D=3D HZIP_HIGH_COMP_PERF) @@ -461,13 +460,6 @@ static int hisi_zip_set_high_perf(struct hisi_qm *qm) =20 /* Set perf mode */ writel(val, qm->io_base + HZIP_HIGH_PERF_OFFSET); - ret =3D readl_relaxed_poll_timeout(qm->io_base + HZIP_HIGH_PERF_OFFSET, - val, val =3D=3D perf_mode, HZIP_DELAY_1_US, - HZIP_POLL_TIMEOUT_US); - if (ret) - pci_err(qm->pdev, "failed to set perf mode\n"); - - return ret; } =20 static void hisi_zip_open_sva_prefetch(struct hisi_qm *qm) @@ -581,6 +573,8 @@ static int hisi_zip_set_user_domain_and_cache(struct hi= si_qm *qm) CQC_CACHE_WB_ENABLE | FIELD_PREP(SQC_CACHE_WB_THRD, 1) | FIELD_PREP(CQC_CACHE_WB_THRD, 1), base + QM_CACHE_CTL); =20 + hisi_zip_set_high_perf(qm); + hisi_zip_enable_clock_gate(qm); =20 return hisi_dae_set_user_domain(qm); @@ -1252,10 +1246,6 @@ static int hisi_zip_pf_probe_init(struct hisi_zip *h= isi_zip) if (ret) return ret; =20 - ret =3D hisi_zip_set_high_perf(qm); - if (ret) - return ret; - hisi_qm_dev_err_init(qm); hisi_zip_debug_regs_clear(qm); =20 --=20 2.33.0 From nobody Sat Oct 4 12:46:56 2025 Received: from szxga04-in.huawei.com (szxga04-in.huawei.com [45.249.212.190]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 93CB2291C2D; Sat, 16 Aug 2025 10:28:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.190 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755340123; cv=none; b=IULZpWRATuH29Qcp8k4XYebkmhY2D9RGeYcP7gZRE92F43vGYg9q8uk2stv/9wqE94bqryKlSBKHzeQJd8cQXTdQJe9Aywq/6LEQz4Y2TLI3bkd5qUGglN6QiDI4kezPCvgThdQcG8CQ/KBehwBtAOfCbiWjTCD6M+2L8zzxjho= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755340123; c=relaxed/simple; bh=1ATT0x7wW4/tRbhjzxR/5NfvE7Ees3+a5k9rw9gXpAg=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=eBq6ScsX+BbB6CFWYWoXp5vOzdPmF9gES8lkPzB0SeqXVI2ooXhXz+QmhO6Z8ds9TvQ2xIeBtmUXBQZJmsYqvshB6cGSQ3amu/6uV9Lz0RCAbvC2ymHqhiYdXD7r/LriKXIQZp+m3j78P/CKgbD51XftVZp0OPBmbpgae1OT5bQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; arc=none smtp.client-ip=45.249.212.190 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.19.88.163]) by szxga04-in.huawei.com (SkyGuard) with ESMTP id 4c3w9Y1d24z2VRG4; Sat, 16 Aug 2025 18:25:53 +0800 (CST) Received: from dggemv705-chm.china.huawei.com (unknown [10.3.19.32]) by mail.maildlp.com (Postfix) with ESMTPS id 46CF518005F; Sat, 16 Aug 2025 18:28:37 +0800 (CST) Received: from kwepemq200001.china.huawei.com (7.202.195.16) by dggemv705-chm.china.huawei.com (10.3.19.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Sat, 16 Aug 2025 18:28:37 +0800 Received: from localhost.huawei.com (10.90.31.46) by kwepemq200001.china.huawei.com (7.202.195.16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Sat, 16 Aug 2025 18:28:36 +0800 From: Chenghai Huang To: , CC: , , , , , , , Subject: [PATCH 3/6] crypto: hisilicon - check the sva module status while enabling or disabling address prefetch Date: Sat, 16 Aug 2025 18:28:31 +0800 Message-ID: <20250816102834.828655-4-huangchenghai2@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20250816102834.828655-1-huangchenghai2@huawei.com> References: <20250816102834.828655-1-huangchenghai2@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: kwepems500002.china.huawei.com (7.221.188.17) To kwepemq200001.china.huawei.com (7.202.195.16) Content-Type: text/plain; charset="utf-8" From: Weili Qian After enabling address prefetch, check the sva module status. If all previous prefetch requests from the sva module are not completed, then disable the address prefetch to ensure normal execution of new task operations. After disabling address prefetch, check if all requests from the sva module have been completed. Fixes: a5c164b195a8 ("crypto: hisilicon/qm - support address prefetching") Signed-off-by: Weili Qian Signed-off-by: Chenghai Huang --- drivers/crypto/hisilicon/hpre/hpre_main.c | 43 +++++++++++- drivers/crypto/hisilicon/sec2/sec_main.c | 48 +++++++++++++- drivers/crypto/hisilicon/zip/zip_main.c | 79 +++++++++++++++++++---- 3 files changed, 154 insertions(+), 16 deletions(-) diff --git a/drivers/crypto/hisilicon/hpre/hpre_main.c b/drivers/crypto/his= ilicon/hpre/hpre_main.c index dbe8f62f556b..e91d03e767da 100644 --- a/drivers/crypto/hisilicon/hpre/hpre_main.c +++ b/drivers/crypto/hisilicon/hpre/hpre_main.c @@ -78,6 +78,11 @@ #define HPRE_PREFETCH_ENABLE (~(BIT(0) | BIT(30))) #define HPRE_PREFETCH_DISABLE BIT(30) #define HPRE_SVA_DISABLE_READY (BIT(4) | BIT(8)) +#define HPRE_SVA_PREFTCH_DFX4 0x301144 +#define HPRE_WAIT_SVA_READY 500000 +#define HPRE_READ_SVA_STATUS_TIMES 3 +#define HPRE_WAIT_US_MIN 10 +#define HPRE_WAIT_US_MAX 20 =20 /* clock gate */ #define HPRE_CLKGATE_CTL 0x301a10 @@ -466,6 +471,33 @@ struct hisi_qp *hpre_create_qp(u8 type) return NULL; } =20 +static int hpre_wait_sva_ready(struct hisi_qm *qm) +{ + u32 val, try_times =3D 0; + u8 count =3D 0; + + /* + * Read the register value every 10-20us. If the value is 0 for three + * consecutive times, the SVA module is ready. + */ + do { + val =3D readl(qm->io_base + HPRE_SVA_PREFTCH_DFX4); + if (val) + count =3D 0; + else if (++count =3D=3D HPRE_READ_SVA_STATUS_TIMES) + break; + + usleep_range(HPRE_WAIT_US_MIN, HPRE_WAIT_US_MAX); + } while (++try_times < HPRE_WAIT_SVA_READY); + + if (try_times =3D=3D HPRE_WAIT_SVA_READY) { + pci_err(qm->pdev, "failed to wait sva prefetch ready\n"); + return -ETIMEDOUT; + } + + return 0; +} + static void hpre_close_sva_prefetch(struct hisi_qm *qm) { u32 val; @@ -484,6 +516,8 @@ static void hpre_close_sva_prefetch(struct hisi_qm *qm) HPRE_REG_RD_TMOUT_US); if (ret) pci_err(qm->pdev, "failed to close sva prefetch\n"); + + (void)hpre_wait_sva_ready(qm); } =20 static void hpre_open_sva_prefetch(struct hisi_qm *qm) @@ -503,8 +537,15 @@ static void hpre_open_sva_prefetch(struct hisi_qm *qm) val, !(val & HPRE_PREFETCH_DISABLE), HPRE_REG_RD_INTVRL_US, HPRE_REG_RD_TMOUT_US); - if (ret) + if (ret) { pci_err(qm->pdev, "failed to open sva prefetch\n"); + hpre_close_sva_prefetch(qm); + return; + } + + ret =3D hpre_wait_sva_ready(qm); + if (ret) + hpre_close_sva_prefetch(qm); } =20 static void hpre_config_pasid(struct hisi_qm *qm) diff --git a/drivers/crypto/hisilicon/sec2/sec_main.c b/drivers/crypto/hisi= licon/sec2/sec_main.c index ddb20f380b54..348f1f52956d 100644 --- a/drivers/crypto/hisilicon/sec2/sec_main.c +++ b/drivers/crypto/hisilicon/sec2/sec_main.c @@ -93,6 +93,16 @@ #define SEC_PREFETCH_ENABLE (~(BIT(0) | BIT(1) | BIT(11))) #define SEC_PREFETCH_DISABLE BIT(1) #define SEC_SVA_DISABLE_READY (BIT(7) | BIT(11)) +#define SEC_SVA_PREFETCH_INFO 0x301ED4 +#define SEC_SVA_STALL_NUM GENMASK(23, 8) +#define SEC_SVA_PREFETCH_NUM GENMASK(2, 0) +#define SEC_WAIT_SVA_READY 500000 +#define SEC_READ_SVA_STATUS_TIMES 3 +#define SEC_WAIT_US_MIN 10 +#define SEC_WAIT_US_MAX 20 +#define SEC_WAIT_QP_US_MIN 1000 +#define SEC_WAIT_QP_US_MAX 2000 +#define SEC_MAX_WAIT_TIMES 2000 =20 #define SEC_DELAY_10_US 10 #define SEC_POLL_TIMEOUT_US 1000 @@ -464,6 +474,33 @@ static void sec_set_endian(struct hisi_qm *qm) writel_relaxed(reg, qm->io_base + SEC_CONTROL_REG); } =20 +static int sec_wait_sva_ready(struct hisi_qm *qm, __u32 offset, __u32 mask) +{ + u32 val, try_times =3D 0; + u8 count =3D 0; + + /* + * Read the register value every 10-20us. If the value is 0 for three + * consecutive times, the SVA module is ready. + */ + do { + val =3D readl(qm->io_base + offset); + if (val & mask) + count =3D 0; + else if (++count =3D=3D SEC_READ_SVA_STATUS_TIMES) + break; + + usleep_range(SEC_WAIT_US_MIN, SEC_WAIT_US_MAX); + } while (++try_times < SEC_WAIT_SVA_READY); + + if (try_times =3D=3D SEC_WAIT_SVA_READY) { + pci_err(qm->pdev, "failed to wait sva prefetch ready\n"); + return -ETIMEDOUT; + } + + return 0; +} + static void sec_close_sva_prefetch(struct hisi_qm *qm) { u32 val; @@ -481,6 +518,8 @@ static void sec_close_sva_prefetch(struct hisi_qm *qm) SEC_DELAY_10_US, SEC_POLL_TIMEOUT_US); if (ret) pci_err(qm->pdev, "failed to close sva prefetch\n"); + + (void)sec_wait_sva_ready(qm, SEC_SVA_PREFETCH_INFO, SEC_SVA_STALL_NUM); } =20 static void sec_open_sva_prefetch(struct hisi_qm *qm) @@ -499,8 +538,15 @@ static void sec_open_sva_prefetch(struct hisi_qm *qm) ret =3D readl_relaxed_poll_timeout(qm->io_base + SEC_PREFETCH_CFG, val, !(val & SEC_PREFETCH_DISABLE), SEC_DELAY_10_US, SEC_POLL_TIMEOUT_US); - if (ret) + if (ret) { pci_err(qm->pdev, "failed to open sva prefetch\n"); + sec_close_sva_prefetch(qm); + return; + } + + ret =3D sec_wait_sva_ready(qm, SEC_SVA_TRANS, SEC_SVA_PREFETCH_NUM); + if (ret) + sec_close_sva_prefetch(qm); } =20 static void sec_engine_sva_config(struct hisi_qm *qm) diff --git a/drivers/crypto/hisilicon/zip/zip_main.c b/drivers/crypto/hisil= icon/zip/zip_main.c index 744f5a0197c3..7d55cd08cd1e 100644 --- a/drivers/crypto/hisilicon/zip/zip_main.c +++ b/drivers/crypto/hisilicon/zip/zip_main.c @@ -95,10 +95,16 @@ #define HZIP_PREFETCH_ENABLE (~(BIT(26) | BIT(17) | BIT(0))) #define HZIP_SVA_PREFETCH_DISABLE BIT(26) #define HZIP_SVA_DISABLE_READY (BIT(26) | BIT(30)) +#define HZIP_SVA_PREFETCH_NUM GENMASK(18, 16) +#define HZIP_SVA_STALL_NUM GENMASK(15, 0) #define HZIP_SHAPER_RATE_COMPRESS 750 #define HZIP_SHAPER_RATE_DECOMPRESS 140 -#define HZIP_DELAY_1_US 1 -#define HZIP_POLL_TIMEOUT_US 1000 +#define HZIP_DELAY_1_US 1 +#define HZIP_POLL_TIMEOUT_US 1000 +#define HZIP_WAIT_SVA_READY 500000 +#define HZIP_READ_SVA_STATUS_TIMES 3 +#define HZIP_WAIT_US_MIN 10 +#define HZIP_WAIT_US_MAX 20 =20 /* clock gating */ #define HZIP_PEH_CFG_AUTO_GATE 0x3011A8 @@ -462,7 +468,34 @@ static void hisi_zip_set_high_perf(struct hisi_qm *qm) writel(val, qm->io_base + HZIP_HIGH_PERF_OFFSET); } =20 -static void hisi_zip_open_sva_prefetch(struct hisi_qm *qm) +static int hisi_zip_wait_sva_ready(struct hisi_qm *qm, __u32 offset, __u32= mask) +{ + u32 val, try_times =3D 0; + u8 count =3D 0; + + /* + * Read the register value every 10-20us. If the value is 0 for three + * consecutive times, the SVA module is ready. + */ + do { + val =3D readl(qm->io_base + offset); + if (val & mask) + count =3D 0; + else if (++count =3D=3D HZIP_READ_SVA_STATUS_TIMES) + break; + + usleep_range(HZIP_WAIT_US_MIN, HZIP_WAIT_US_MAX); + } while (++try_times < HZIP_WAIT_SVA_READY); + + if (try_times =3D=3D HZIP_WAIT_SVA_READY) { + pci_err(qm->pdev, "failed to wait sva prefetch ready\n"); + return -ETIMEDOUT; + } + + return 0; +} + +static void hisi_zip_close_sva_prefetch(struct hisi_qm *qm) { u32 val; int ret; @@ -470,19 +503,20 @@ static void hisi_zip_open_sva_prefetch(struct hisi_qm= *qm) if (!test_bit(QM_SUPPORT_SVA_PREFETCH, &qm->caps)) return; =20 - /* Enable prefetch */ val =3D readl_relaxed(qm->io_base + HZIP_PREFETCH_CFG); - val &=3D HZIP_PREFETCH_ENABLE; + val |=3D HZIP_SVA_PREFETCH_DISABLE; writel(val, qm->io_base + HZIP_PREFETCH_CFG); =20 - ret =3D readl_relaxed_poll_timeout(qm->io_base + HZIP_PREFETCH_CFG, - val, !(val & HZIP_SVA_PREFETCH_DISABLE), + ret =3D readl_relaxed_poll_timeout(qm->io_base + HZIP_SVA_TRANS, + val, !(val & HZIP_SVA_DISABLE_READY), HZIP_DELAY_1_US, HZIP_POLL_TIMEOUT_US); if (ret) - pci_err(qm->pdev, "failed to open sva prefetch\n"); + pci_err(qm->pdev, "failed to close sva prefetch\n"); + + (void)hisi_zip_wait_sva_ready(qm, HZIP_SVA_TRANS, HZIP_SVA_STALL_NUM); } =20 -static void hisi_zip_close_sva_prefetch(struct hisi_qm *qm) +static void hisi_zip_open_sva_prefetch(struct hisi_qm *qm) { u32 val; int ret; @@ -490,15 +524,23 @@ static void hisi_zip_close_sva_prefetch(struct hisi_q= m *qm) if (!test_bit(QM_SUPPORT_SVA_PREFETCH, &qm->caps)) return; =20 + /* Enable prefetch */ val =3D readl_relaxed(qm->io_base + HZIP_PREFETCH_CFG); - val |=3D HZIP_SVA_PREFETCH_DISABLE; + val &=3D HZIP_PREFETCH_ENABLE; writel(val, qm->io_base + HZIP_PREFETCH_CFG); =20 - ret =3D readl_relaxed_poll_timeout(qm->io_base + HZIP_SVA_TRANS, - val, !(val & HZIP_SVA_DISABLE_READY), + ret =3D readl_relaxed_poll_timeout(qm->io_base + HZIP_PREFETCH_CFG, + val, !(val & HZIP_SVA_PREFETCH_DISABLE), HZIP_DELAY_1_US, HZIP_POLL_TIMEOUT_US); + if (ret) { + pci_err(qm->pdev, "failed to open sva prefetch\n"); + hisi_zip_close_sva_prefetch(qm); + return; + } + + ret =3D hisi_zip_wait_sva_ready(qm, HZIP_SVA_TRANS, HZIP_SVA_PREFETCH_NUM= ); if (ret) - pci_err(qm->pdev, "failed to close sva prefetch\n"); + hisi_zip_close_sva_prefetch(qm); } =20 static void hisi_zip_enable_clock_gate(struct hisi_qm *qm) @@ -522,6 +564,7 @@ static int hisi_zip_set_user_domain_and_cache(struct hi= si_qm *qm) void __iomem *base =3D qm->io_base; u32 dcomp_bm, comp_bm; u32 zip_core_en; + int ret; =20 /* qm user domain */ writel(AXUSER_BASE, base + QM_ARUSER_M_CFG_1); @@ -577,7 +620,15 @@ static int hisi_zip_set_user_domain_and_cache(struct h= isi_qm *qm) =20 hisi_zip_enable_clock_gate(qm); =20 - return hisi_dae_set_user_domain(qm); + ret =3D hisi_dae_set_user_domain(qm); + if (ret) + goto close_sva_prefetch; + + return 0; + +close_sva_prefetch: + hisi_zip_close_sva_prefetch(qm); + return ret; } =20 static void hisi_zip_master_ooo_ctrl(struct hisi_qm *qm, bool enable) --=20 2.33.0 From nobody Sat Oct 4 12:46:56 2025 Received: from szxga04-in.huawei.com (szxga04-in.huawei.com [45.249.212.190]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B537D252912; 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dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.19.163.44]) by szxga04-in.huawei.com (SkyGuard) with ESMTP id 4c3w7h58zjz2Cg5h; Sat, 16 Aug 2025 18:24:16 +0800 (CST) Received: from dggemv706-chm.china.huawei.com (unknown [10.3.19.33]) by mail.maildlp.com (Postfix) with ESMTPS id B00DA140295; Sat, 16 Aug 2025 18:28:37 +0800 (CST) Received: from kwepemq200001.china.huawei.com (7.202.195.16) by dggemv706-chm.china.huawei.com (10.3.19.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Sat, 16 Aug 2025 18:28:37 +0800 Received: from localhost.huawei.com (10.90.31.46) by kwepemq200001.china.huawei.com (7.202.195.16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Sat, 16 Aug 2025 18:28:36 +0800 From: Chenghai Huang To: , CC: , , , , , , , Subject: [PATCH 4/6] crypto: hisilicon/qm - check whether the input function and PF are on the same device Date: Sat, 16 Aug 2025 18:28:32 +0800 Message-ID: <20250816102834.828655-5-huangchenghai2@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20250816102834.828655-1-huangchenghai2@huawei.com> References: <20250816102834.828655-1-huangchenghai2@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: kwepems500002.china.huawei.com (7.221.188.17) To kwepemq200001.china.huawei.com (7.202.195.16) Content-Type: text/plain; charset="utf-8" From: Zhushuai Yin Function rate limiting is set through physical function driver. Users configure by providing function information and rate limit values. Before configuration, it is necessary to check whether the provided function and PF belong to the same device. Fixes: 22d7a6c39cab ("crypto: hisilicon/qm - add pci bdf number check") Signed-off-by: Zhushuai Yin Signed-off-by: Chenghai Huang --- drivers/crypto/hisilicon/qm.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/crypto/hisilicon/qm.c b/drivers/crypto/hisilicon/qm.c index a5cc0ccd94f1..2f96c673b60a 100644 --- a/drivers/crypto/hisilicon/qm.c +++ b/drivers/crypto/hisilicon/qm.c @@ -3826,6 +3826,10 @@ static ssize_t qm_get_qos_value(struct hisi_qm *qm, = const char *buf, } =20 pdev =3D container_of(dev, struct pci_dev, dev); + if (pci_physfn(pdev) !=3D qm->pdev) { + pci_err(qm->pdev, "the pdev input does not match the pf!\n"); + return -EINVAL; + } =20 *fun_index =3D pdev->devfn; =20 --=20 2.33.0 From nobody Sat Oct 4 12:46:56 2025 Received: from szxga01-in.huawei.com (szxga01-in.huawei.com [45.249.212.187]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DF56629A333; Sat, 16 Aug 2025 10:28:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.187 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755340128; cv=none; b=ouUPldwNCyMF/9woQ4UvU2YVXZjJukKF5FU/G0PmavGzLO6UEfjIrblWZmYMNu1imVelun36Z/VZWSlJ0mxLt4hHnBpI2HzM99QB7bIt6Vg8PFfWkcF3LuDE7Gpvt+mcY7VJMlpsBeyGX2E05PhzQu9w8Zu8LA1PsrCs2A4DSuQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755340128; c=relaxed/simple; bh=Qk7TgE5D86vpZ/c5iGhi8K849ydeJdz7eXwhUqjGqAg=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=lLm3y5Q6rwccDaFRPnl8p1De4LYJyZkGUaMnL2nWQzro3tbsO0lma3dFDOz0uZgijhZXkQLaTZe8t+zpFFbHWi0P7KEIIP5+szXimmuEBe5jseJFe5mn059uXTJnbZ3SzGUPW6d8cBOcw7rUWNb3zWIuso+1sNqJZEwe0+sXLes= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; arc=none smtp.client-ip=45.249.212.187 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.19.163.252]) by szxga01-in.huawei.com (SkyGuard) with ESMTP id 4c3w8j6l6dz13N0W; Sat, 16 Aug 2025 18:25:09 +0800 (CST) Received: from dggemv712-chm.china.huawei.com (unknown [10.1.198.32]) by mail.maildlp.com (Postfix) with ESMTPS id 18518180B66; Sat, 16 Aug 2025 18:28:38 +0800 (CST) Received: from kwepemq200001.china.huawei.com (7.202.195.16) by dggemv712-chm.china.huawei.com (10.1.198.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Sat, 16 Aug 2025 18:28:37 +0800 Received: from localhost.huawei.com (10.90.31.46) by kwepemq200001.china.huawei.com (7.202.195.16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Sat, 16 Aug 2025 18:28:37 +0800 From: Chenghai Huang To: , CC: , , , , , , , Subject: [PATCH 5/6] crypto: hisilicon/qm - request reserved interrupt for virtual function Date: Sat, 16 Aug 2025 18:28:33 +0800 Message-ID: <20250816102834.828655-6-huangchenghai2@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20250816102834.828655-1-huangchenghai2@huawei.com> References: <20250816102834.828655-1-huangchenghai2@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: kwepems500002.china.huawei.com (7.221.188.17) To kwepemq200001.china.huawei.com (7.202.195.16) Content-Type: text/plain; charset="utf-8" From: Weili Qian The device interrupt vector 3 is an error interrupt for physical function and a reserved interrupt for virtual function. However, the driver has not registered the reserved interrupt for virtual function. When allocating interrupts, the number of interrupts is allocated based on powers of two, which includes this interrupt. When the system enables GICv4 and the virtual function passthrough to the virtual machine, releasing the interrupt in the driver triggers a warning. The WARNING report is: WARNING: CPU: 62 PID: 14889 at arch/arm64/kvm/vgic/vgic-its.c:852 its_free_= ite+0x94/0xb4 Therefore, register a reserved interrupt for VF and set the IRQF_NO_AUTOEN flag to avoid that warning. Fixes: 3536cc55cada ("crypto: hisilicon/qm - support get device irq informa= tion from hardware registers") Signed-off-by: Weili Qian Signed-off-by: Chenghai Huang --- drivers/crypto/hisilicon/qm.c | 38 +++++++++++++++++++++++++++++------ 1 file changed, 32 insertions(+), 6 deletions(-) diff --git a/drivers/crypto/hisilicon/qm.c b/drivers/crypto/hisilicon/qm.c index 2f96c673b60a..102aff9ea19a 100644 --- a/drivers/crypto/hisilicon/qm.c +++ b/drivers/crypto/hisilicon/qm.c @@ -4732,6 +4732,15 @@ void hisi_qm_reset_done(struct pci_dev *pdev) } EXPORT_SYMBOL_GPL(hisi_qm_reset_done); =20 +static irqreturn_t qm_rsvd_irq(int irq, void *data) +{ + struct hisi_qm *qm =3D data; + + dev_info(&qm->pdev->dev, "Reserved interrupt, ignore!\n"); + + return IRQ_HANDLED; +} + static irqreturn_t qm_abnormal_irq(int irq, void *data) { struct hisi_qm *qm =3D data; @@ -5015,7 +5024,7 @@ static void qm_unregister_abnormal_irq(struct hisi_qm= *qm) struct pci_dev *pdev =3D qm->pdev; u32 irq_vector, val; =20 - if (qm->fun_type =3D=3D QM_HW_VF) + if (qm->fun_type =3D=3D QM_HW_VF && qm->ver < QM_HW_V3) return; =20 val =3D qm->cap_tables.qm_cap_table[QM_ABNORMAL_IRQ].cap_val; @@ -5032,17 +5041,28 @@ static int qm_register_abnormal_irq(struct hisi_qm = *qm) u32 irq_vector, val; int ret; =20 - if (qm->fun_type =3D=3D QM_HW_VF) - return 0; - val =3D qm->cap_tables.qm_cap_table[QM_ABNORMAL_IRQ].cap_val; if (!((val >> QM_IRQ_TYPE_SHIFT) & QM_ABN_IRQ_TYPE_MASK)) return 0; - irq_vector =3D val & QM_IRQ_VECTOR_MASK; + + /* For VF, this is a reserved interrupt in V3 version. */ + if (qm->fun_type =3D=3D QM_HW_VF) { + if (qm->ver < QM_HW_V3) + return 0; + + ret =3D request_irq(pci_irq_vector(pdev, irq_vector), qm_rsvd_irq, + IRQF_NO_AUTOEN, qm->dev_name, qm); + if (ret) { + dev_err(&pdev->dev, "failed to request reserved irq, ret =3D %d!\n", re= t); + return ret; + } + return 0; + } + ret =3D request_irq(pci_irq_vector(pdev, irq_vector), qm_abnormal_irq, 0,= qm->dev_name, qm); if (ret) - dev_err(&qm->pdev->dev, "failed to request abnormal irq, ret =3D %d", re= t); + dev_err(&qm->pdev->dev, "failed to request abnormal irq, ret =3D %d!\n",= ret); =20 return ret; } @@ -5408,6 +5428,12 @@ static int hisi_qm_pci_init(struct hisi_qm *qm) pci_set_master(pdev); =20 num_vec =3D qm_get_irq_num(qm); + if (!num_vec) { + dev_err(dev, "Device irq num is zero!\n"); + ret =3D -EINVAL; + goto err_get_pci_res; + } + num_vec =3D roundup_pow_of_two(num_vec); ret =3D pci_alloc_irq_vectors(pdev, num_vec, num_vec, PCI_IRQ_MSI); if (ret < 0) { dev_err(dev, "Failed to enable MSI vectors!\n"); --=20 2.33.0 From nobody Sat Oct 4 12:46:56 2025 Received: from szxga01-in.huawei.com (szxga01-in.huawei.com [45.249.212.187]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0A87829AAE9; Sat, 16 Aug 2025 10:28:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.187 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755340128; cv=none; b=RCIzZkmiGdOwjSwN7bjIPdQYIzlfLwZ45sGyoITRtUkCtyRILk9uWuCVnRbFT+b1GeNP43v43Om6UtFHFBIltCgkM7lYXJIq90EPmXnvVtGexhTHaNBDW5WnTU2NMgholAqqejHYMPuAZf67HRmkwkf5iOswnqaTrJ1x28Z9TZc= ARC-Message-Signature: i=1; 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Sat, 16 Aug 2025 18:28:38 +0800 (CST) Received: from kwepemq200001.china.huawei.com (7.202.195.16) by dggemv705-chm.china.huawei.com (10.3.19.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Sat, 16 Aug 2025 18:28:38 +0800 Received: from localhost.huawei.com (10.90.31.46) by kwepemq200001.china.huawei.com (7.202.195.16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Sat, 16 Aug 2025 18:28:37 +0800 From: Chenghai Huang To: , CC: , , , , , , , Subject: [PATCH 6/6] crypto: hisilicon/zip - enable literal length in stream mode compression Date: Sat, 16 Aug 2025 18:28:34 +0800 Message-ID: <20250816102834.828655-7-huangchenghai2@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20250816102834.828655-1-huangchenghai2@huawei.com> References: <20250816102834.828655-1-huangchenghai2@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: kwepems500002.china.huawei.com (7.221.188.17) To kwepemq200001.china.huawei.com (7.202.195.16) Content-Type: text/plain; charset="utf-8" In stream mode, the hardware needs to combine the length of the previous literal to calculate the length of the current literal. Signed-off-by: Chenghai Huang --- drivers/crypto/hisilicon/zip/zip_main.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/crypto/hisilicon/zip/zip_main.c b/drivers/crypto/hisil= icon/zip/zip_main.c index 7d55cd08cd1e..c75db858bb76 100644 --- a/drivers/crypto/hisilicon/zip/zip_main.c +++ b/drivers/crypto/hisilicon/zip/zip_main.c @@ -117,6 +117,9 @@ /* zip comp high performance */ #define HZIP_HIGH_PERF_OFFSET 0x301208 =20 +#define HZIP_LIT_LEN_EN_OFFSET 0x301204 +#define HZIP_LIT_LEN_EN_EN BIT(4) + enum { HZIP_HIGH_COMP_RATE, HZIP_HIGH_COMP_PERF, @@ -454,6 +457,20 @@ bool hisi_zip_alg_support(struct hisi_qm *qm, u32 alg) return false; } =20 +static void hisi_zip_literal_set(struct hisi_qm *qm) +{ + u32 val; + + if (qm->ver < QM_HW_V3) + return; + + val =3D readl_relaxed(qm->io_base + HZIP_LIT_LEN_EN_OFFSET); + val &=3D ~HZIP_LIT_LEN_EN_EN; + + /* enable literal length in stream mode compression */ + writel(val, qm->io_base + HZIP_LIT_LEN_EN_OFFSET); +} + static void hisi_zip_set_high_perf(struct hisi_qm *qm) { u32 val; @@ -616,6 +633,8 @@ static int hisi_zip_set_user_domain_and_cache(struct hi= si_qm *qm) CQC_CACHE_WB_ENABLE | FIELD_PREP(SQC_CACHE_WB_THRD, 1) | FIELD_PREP(CQC_CACHE_WB_THRD, 1), base + QM_CACHE_CTL); =20 + hisi_zip_literal_set(qm); + hisi_zip_set_high_perf(qm); =20 hisi_zip_enable_clock_gate(qm); --=20 2.33.0