From nobody Sat Oct 4 12:46:54 2025 Received: from sender4-op-o15.zoho.com (sender4-op-o15.zoho.com [136.143.188.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BEC8D11713; Sat, 16 Aug 2025 09:12:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.15 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755335522; cv=pass; b=tfiRPqrZGCL6nRbt9Qx2e7nBL8hIViRB+EZFqPVU8kYHOySKMZ058NBL/H0TLd/RTQ916P3qz0ntELq35iwTXoq/rbXaFdfVaR2rh20EuaNcvEXs1rjnzTXPa5Xs4zK7UhIthCbjldlIC+nTO9pIjyFLmud9abQtLRqbxhB0LBk= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755335522; c=relaxed/simple; bh=KAw3oWdlMD4tYuz/Q1EVYOc8isIt+msWO5h3a/6y1co=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=WOTJeGzWF5zH1w4mx4quQXygSkwOGHpG76AvsqI6hJ8Ij6KWISgwduiOO1t399oy70ecAsys8mRRz4swbd1c3S6rOdYcccMnN+f/QloLHo5fDE+DcnpZV3qjIhuC6MwX5opy5jU64F4xqTIBj8VqHdJPWSD2xVlPpOgWKg2agaM= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=icenowy.me; spf=pass smtp.mailfrom=icenowy.me; dkim=pass (2048-bit key) header.d=icenowy.me header.i=uwu@icenowy.me header.b=ARPjtAaH; arc=pass smtp.client-ip=136.143.188.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=icenowy.me Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=icenowy.me Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=icenowy.me header.i=uwu@icenowy.me header.b="ARPjtAaH" ARC-Seal: i=1; a=rsa-sha256; t=1755335499; cv=none; d=zohomail.com; s=zohoarc; b=PVc6NoeTR6YKm0QNmvUEJqGNsofza7y17lApa9d1iXK1yzX5FGY4ZNPY3YtFFRnWFBiInwnTkFFAtReDzgNOK5PPN8T4dLhZ3MPUb4vyro4UVWrqHVOoRfQ1/ST50x8PLx0Y/3FNpZSKVk/qdL5Zy4p/ryiSVNC8RLrObVSxG24= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1755335499; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:Subject:To:To:Message-Id:Reply-To; bh=fCVzUEHjBk9WIXhQ2mFElRGPPA6pTX38mHJTTDFKnsY=; b=hKB3GaKCUFLy/e3dLOg7dBayC0GMg0U+MTIaH5G5JG0WHqCTEdvXAzG+Jzmd7VRk7aWLhoZCL8huET0z7vD+4d313jWv78NOaDtGoR2heskZvzlbPquNoh4YaOTX7/0wnrPKasmGvQ621O1qRZy4Mycc2+NZJrM5qC68jhWoiI8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=icenowy.me; spf=pass smtp.mailfrom=uwu@icenowy.me; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1755335499; s=zmail2; d=icenowy.me; i=uwu@icenowy.me; h=From:From:To:To:Cc:Cc:Subject:Subject:Date:Date:Message-ID:In-Reply-To:References:MIME-Version:Content-Transfer-Encoding:Message-Id:Reply-To; bh=fCVzUEHjBk9WIXhQ2mFElRGPPA6pTX38mHJTTDFKnsY=; b=ARPjtAaHoCheB7GM4nhAYyz0p0UMfVSgTSjwSUrpMamONbOnzQU8WJvuNul7tPKB b0yA6xBLsbzau7ryG47c4OWG4MUsStihQN/pt2ALtxGx8GtzSzk+KYcnub/zhIX++sa Q+8n5F+yr9aiO8Fuhj71JB1gdVLNz46dZeBpM875KIeXuXrTD22sJt6TQ7U7BdmyO07 3VRg/Yvc0/TIPvubMpkh6rczdjwsA7b+cUZQr465CRwyBBegdFvhBm2gRtC2aJmWbp2 kjsRgqJTU0vvUr+hPg3k36sHEgKs0lTtnuYsKypjP4GXcGGM6vrV32wy/5W2WF4z/zr 3ZGqNXeKRg== Received: by mx.zohomail.com with SMTPS id 1755335497092175.64907767078034; Sat, 16 Aug 2025 02:11:37 -0700 (PDT) From: Icenowy Zheng To: Drew Fustini , Guo Ren , Fu Wei , Michael Turquette , Stephen Boyd , Michal Wilczynski Cc: Han Gao , Yao Zi , linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Icenowy Zheng Subject: [PATCH v3 1/4] clk: thead: Correct parent for DPU pixel clocks Date: Sat, 16 Aug 2025 17:11:10 +0800 Message-ID: <20250816091113.2596048-2-uwu@icenowy.me> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250816091113.2596048-1-uwu@icenowy.me> References: <20250816091113.2596048-1-uwu@icenowy.me> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMailClient: External Content-Type: text/plain; charset="utf-8" From: Michal Wilczynski The dpu0_pixelclk and dpu1_pixelclk gates were incorrectly parented to the video_pll_clk. According to the TH1520 TRM, the "dpu0_pixelclk" should be sourced from "DPU0 PLL DIV CLK". In this driver, "DPU0 PLL DIV CLK" corresponds to the `dpu0_clk` clock, which is a divider whose parent is the `dpu0_pll_clk`. This patch corrects the clock hierarchy by reparenting `dpu0_pixelclk` to `dpu0_clk`. By symmetry, `dpu1_pixelclk` is also reparented to its correct source, `dpu1_clk`. Fixes: 50d4b157fa96 ("clk: thead: Add clock support for VO subsystem in T-H= EAD TH1520 SoC") Reported-by: Icenowy Zheng Signed-off-by: Michal Wilczynski [Icenowy: add Drew's R-b and rebased atop ccu_gate refactor] Reviewed-by: Drew Fustini Signed-off-by: Icenowy Zheng --- Pulled into this patchset in v3 because of rebasing. drivers/clk/thead/clk-th1520-ap.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/clk/thead/clk-th1520-ap.c b/drivers/clk/thead/clk-th15= 20-ap.c index 8a5d699638379..ec52726fbea95 100644 --- a/drivers/clk/thead/clk-th1520-ap.c +++ b/drivers/clk/thead/clk-th1520-ap.c @@ -761,6 +761,10 @@ static struct ccu_div dpu0_clk =3D { }, }; =20 +static const struct clk_parent_data dpu0_clk_pd[] =3D { + { .hw =3D &dpu0_clk.common.hw } +}; + static struct ccu_div dpu1_clk =3D { .div =3D TH_CCU_DIV_FLAGS(0, 8, CLK_DIVIDER_ONE_BASED), .common =3D { @@ -773,6 +777,10 @@ static struct ccu_div dpu1_clk =3D { }, }; =20 +static const struct clk_parent_data dpu1_clk_pd[] =3D { + { .hw =3D &dpu1_clk.common.hw } +}; + static CLK_FIXED_FACTOR_HW(emmc_sdio_ref_clk, "emmc-sdio-ref", &video_pll_clk.common.hw, 4, 1, 0); =20 @@ -853,9 +861,9 @@ static CCU_GATE(CLK_GPU_CORE, gpu_core_clk, "gpu-core-c= lk", video_pll_clk_pd, static CCU_GATE(CLK_GPU_CFG_ACLK, gpu_cfg_aclk, "gpu-cfg-aclk", video_pll_clk_pd, 0x0, 4, 0); static CCU_GATE(CLK_DPU_PIXELCLK0, dpu0_pixelclk, "dpu0-pixelclk", - video_pll_clk_pd, 0x0, 5, 0); + dpu0_clk_pd, 0x0, 5, 0); static CCU_GATE(CLK_DPU_PIXELCLK1, dpu1_pixelclk, "dpu1-pixelclk", - video_pll_clk_pd, 0x0, 6, 0); + dpu1_clk_pd, 0x0, 6, 0); static CCU_GATE(CLK_DPU_HCLK, dpu_hclk, "dpu-hclk", video_pll_clk_pd, 0x0, 7, 0); static CCU_GATE(CLK_DPU_ACLK, dpu_aclk, "dpu-aclk", video_pll_clk_pd, 0x0, --=20 2.50.1 From nobody Sat Oct 4 12:46:54 2025 Received: from sender4-op-o15.zoho.com (sender4-op-o15.zoho.com [136.143.188.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A4ACC23F429; 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charset="utf-8" The 2nd control word of T-Head TH1520 PLLs contains a bit to put the VCO into reset state, which means disabling the PLL. Some PLLs are put to disabled state by the bootloader, and the clock driver should be able to enable them. Add support for enabling/disabling PLLs. PLLs other than DPU ones are set CLK_IS_CRITICAL to prevent killing the system -- they're meant to drive CPU or system buses (even the GMAC/Video ones are driving arbitrary buses). Signed-off-by: Icenowy Zheng Reviewed-by: Drew Fustini --- No changes in v2. Changes in v3: - Added Drew's R-b. drivers/clk/thead/clk-th1520-ap.c | 38 +++++++++++++++++++++++++++---- 1 file changed, 33 insertions(+), 5 deletions(-) diff --git a/drivers/clk/thead/clk-th1520-ap.c b/drivers/clk/thead/clk-th15= 20-ap.c index ec52726fbea95..d81445e24a96a 100644 --- a/drivers/clk/thead/clk-th1520-ap.c +++ b/drivers/clk/thead/clk-th1520-ap.c @@ -18,6 +18,7 @@ #define TH1520_PLL_FBDIV GENMASK(19, 8) #define TH1520_PLL_REFDIV GENMASK(5, 0) #define TH1520_PLL_BYPASS BIT(30) +#define TH1520_PLL_VCO_RST BIT(29) #define TH1520_PLL_DSMPD BIT(24) #define TH1520_PLL_FRAC GENMASK(23, 0) #define TH1520_PLL_FRAC_BITS 24 @@ -236,6 +237,30 @@ static const struct clk_ops ccu_div_ops =3D { .determine_rate =3D clk_hw_determine_rate_no_reparent, }; =20 +static void ccu_pll_disable(struct clk_hw *hw) +{ + struct ccu_pll *pll =3D hw_to_ccu_pll(hw); + + regmap_set_bits(pll->common.map, pll->common.cfg1, + TH1520_PLL_VCO_RST); +} + +static int ccu_pll_enable(struct clk_hw *hw) +{ + struct ccu_pll *pll =3D hw_to_ccu_pll(hw); + + return regmap_clear_bits(pll->common.map, pll->common.cfg1, + TH1520_PLL_VCO_RST); +} + +static int ccu_pll_is_enabled(struct clk_hw *hw) +{ + struct ccu_pll *pll =3D hw_to_ccu_pll(hw); + + return !regmap_test_bits(pll->common.map, pll->common.cfg1, + TH1520_PLL_VCO_RST); +} + static unsigned long th1520_pll_vco_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { @@ -293,6 +318,9 @@ static unsigned long ccu_pll_recalc_rate(struct clk_hw = *hw, } =20 static const struct clk_ops clk_pll_ops =3D { + .disable =3D ccu_pll_disable, + .enable =3D ccu_pll_enable, + .is_enabled =3D ccu_pll_is_enabled, .recalc_rate =3D ccu_pll_recalc_rate, }; =20 @@ -308,7 +336,7 @@ static struct ccu_pll cpu_pll0_clk =3D { .hw.init =3D CLK_HW_INIT_PARENTS_DATA("cpu-pll0", osc_24m_clk, &clk_pll_ops, - 0), + CLK_IS_CRITICAL), }, }; =20 @@ -320,7 +348,7 @@ static struct ccu_pll cpu_pll1_clk =3D { .hw.init =3D CLK_HW_INIT_PARENTS_DATA("cpu-pll1", osc_24m_clk, &clk_pll_ops, - 0), + CLK_IS_CRITICAL), }, }; =20 @@ -332,7 +360,7 @@ static struct ccu_pll gmac_pll_clk =3D { .hw.init =3D CLK_HW_INIT_PARENTS_DATA("gmac-pll", osc_24m_clk, &clk_pll_ops, - 0), + CLK_IS_CRITICAL), }, }; =20 @@ -352,7 +380,7 @@ static struct ccu_pll video_pll_clk =3D { .hw.init =3D CLK_HW_INIT_PARENTS_DATA("video-pll", osc_24m_clk, &clk_pll_ops, - 0), + CLK_IS_CRITICAL), }, }; =20 @@ -404,7 +432,7 @@ static struct ccu_pll tee_pll_clk =3D { .hw.init =3D CLK_HW_INIT_PARENTS_DATA("tee-pll", osc_24m_clk, &clk_pll_ops, - 0), + CLK_IS_CRITICAL), }, }; =20 --=20 2.50.1 From nobody Sat Oct 4 12:46:54 2025 Received: from sender4-op-o15.zoho.com (sender4-op-o15.zoho.com [136.143.188.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1AFE02417E0; Sat, 16 Aug 2025 09:12:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.15 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; 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charset="utf-8" The DPU pixel clock rate corresponds to the required dot clock of the display mode, so it needs to be tweakable. Add support to change it, by adding generic divider setting code, arming the code to the dpu0/dpu1 clocks, and setting the pixel clock connected to the DPU (after a gate) to CLK_SET_RATE_PARENT to propagate it to the dividers. Signed-off-by: Icenowy Zheng Reviewed-by: Drew Fustini --- Changes in v2: - Dropped round_rate() because of deprecation. - Changed the logic of determine_rate() to early return if the divider could be changed. Changes in v3: - Rebased atop ccu_gate refactor. - Fixed alignment issue of ccu_div_set_rate()'s signature. - Removed a meaningless assignment to curr_val in ccu_div_set_rate() because of being immediately overriden. - Added Drew's R-b. drivers/clk/thead/clk-th1520-ap.c | 63 ++++++++++++++++++++++++++++--- 1 file changed, 58 insertions(+), 5 deletions(-) diff --git a/drivers/clk/thead/clk-th1520-ap.c b/drivers/clk/thead/clk-th15= 20-ap.c index d81445e24a96a..54222b3219ccf 100644 --- a/drivers/clk/thead/clk-th1520-ap.c +++ b/drivers/clk/thead/clk-th1520-ap.c @@ -56,6 +56,7 @@ struct ccu_gate { =20 struct ccu_div { u32 enable; + u32 div_en; struct ccu_div_internal div; struct ccu_internal mux; struct ccu_common common; @@ -192,6 +193,55 @@ static unsigned long ccu_div_recalc_rate(struct clk_hw= *hw, return rate; } =20 +static int ccu_div_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + struct ccu_div *cd =3D hw_to_ccu_div(hw); + unsigned int val; + + if (cd->div_en) + return divider_determine_rate(hw, req, NULL, + cd->div.width, cd->div.flags); + + regmap_read(cd->common.map, cd->common.cfg0, &val); + val =3D val >> cd->div.shift; + val &=3D GENMASK(cd->div.width - 1, 0); + return divider_ro_determine_rate(hw, req, NULL, cd->div.width, + cd->div.flags, val); +} + +static int ccu_div_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct ccu_div *cd =3D hw_to_ccu_div(hw); + int val =3D divider_get_val(rate, parent_rate, NULL, + cd->div.width, cd->div.flags); + unsigned int curr_val, reg_val; + + if (val < 0) + return val; + + regmap_read(cd->common.map, cd->common.cfg0, ®_val); + curr_val =3D reg_val >> cd->div.shift; + curr_val &=3D GENMASK(cd->div.width - 1, 0); + + if (!cd->div_en && curr_val !=3D val) + return -EINVAL; + + reg_val &=3D ~cd->div_en; + regmap_write(cd->common.map, cd->common.cfg0, reg_val); + udelay(1); + + reg_val &=3D ~GENMASK(cd->div.width + cd->div.shift - 1, cd->div.shift); + reg_val |=3D val << cd->div.shift; + regmap_write(cd->common.map, cd->common.cfg0, reg_val); + + reg_val |=3D cd->div_en; + regmap_write(cd->common.map, cd->common.cfg0, reg_val); + + return 0; +} + static u8 ccu_div_get_parent(struct clk_hw *hw) { struct ccu_div *cd =3D hw_to_ccu_div(hw); @@ -234,7 +284,8 @@ static const struct clk_ops ccu_div_ops =3D { .get_parent =3D ccu_div_get_parent, .set_parent =3D ccu_div_set_parent, .recalc_rate =3D ccu_div_recalc_rate, - .determine_rate =3D clk_hw_determine_rate_no_reparent, + .set_rate =3D ccu_div_set_rate, + .determine_rate =3D ccu_div_determine_rate, }; =20 static void ccu_pll_disable(struct clk_hw *hw) @@ -778,6 +829,7 @@ static struct ccu_div venc_clk =3D { }; =20 static struct ccu_div dpu0_clk =3D { + .div_en =3D BIT(8), .div =3D TH_CCU_DIV_FLAGS(0, 8, CLK_DIVIDER_ONE_BASED), .common =3D { .clkid =3D CLK_DPU0, @@ -785,7 +837,7 @@ static struct ccu_div dpu0_clk =3D { .hw.init =3D CLK_HW_INIT_PARENTS_HW("dpu0", dpu0_pll_clk_parent, &ccu_div_ops, - 0), + CLK_SET_RATE_UNGATE), }, }; =20 @@ -794,6 +846,7 @@ static const struct clk_parent_data dpu0_clk_pd[] =3D { }; =20 static struct ccu_div dpu1_clk =3D { + .div_en =3D BIT(8), .div =3D TH_CCU_DIV_FLAGS(0, 8, CLK_DIVIDER_ONE_BASED), .common =3D { .clkid =3D CLK_DPU1, @@ -801,7 +854,7 @@ static struct ccu_div dpu1_clk =3D { .hw.init =3D CLK_HW_INIT_PARENTS_HW("dpu1", dpu1_pll_clk_parent, &ccu_div_ops, - 0), + CLK_SET_RATE_UNGATE), }, }; =20 @@ -889,9 +942,9 @@ static CCU_GATE(CLK_GPU_CORE, gpu_core_clk, "gpu-core-c= lk", video_pll_clk_pd, static CCU_GATE(CLK_GPU_CFG_ACLK, gpu_cfg_aclk, "gpu-cfg-aclk", video_pll_clk_pd, 0x0, 4, 0); static CCU_GATE(CLK_DPU_PIXELCLK0, dpu0_pixelclk, "dpu0-pixelclk", - dpu0_clk_pd, 0x0, 5, 0); + dpu0_clk_pd, 0x0, 5, CLK_SET_RATE_PARENT); static CCU_GATE(CLK_DPU_PIXELCLK1, dpu1_pixelclk, "dpu1-pixelclk", - dpu1_clk_pd, 0x0, 6, 0); + dpu1_clk_pd, 0x0, 6, CLK_SET_RATE_PARENT); static CCU_GATE(CLK_DPU_HCLK, dpu_hclk, "dpu-hclk", video_pll_clk_pd, 0x0, 7, 0); static CCU_GATE(CLK_DPU_ACLK, dpu_aclk, "dpu-aclk", video_pll_clk_pd, 0x0, --=20 2.50.1 From nobody Sat Oct 4 12:46:54 2025 Received: from sender4-op-o15.zoho.com (sender4-op-o15.zoho.com [136.143.188.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A4B6923D29F; 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charset="utf-8" The AXI crossbar of TH1520 has no proper timeout handling, which means gating AXI clocks can easily lead to bus timeout and thus system hang. Set all AXI clock gates to CLK_IS_CRITICAL. All these clock gates are ungated by default on system reset. In addition, convert all current CLK_IGNORE_UNUSED usage to CLK_IS_CRITICAL to prevent unwanted clock gating. Signed-off-by: Icenowy Zheng Reviewed-by: Drew Fustini --- No changes in v2 except for rebasing error fixes (which I sent as FIXED patches in v1). Changes in v3: - Rebased atop ccu_gate refactor. - Added Drew's R-b. drivers/clk/thead/clk-th1520-ap.c | 44 +++++++++++++++---------------- 1 file changed, 22 insertions(+), 22 deletions(-) diff --git a/drivers/clk/thead/clk-th1520-ap.c b/drivers/clk/thead/clk-th15= 20-ap.c index 54222b3219ccf..26e55e1c60148 100644 --- a/drivers/clk/thead/clk-th1520-ap.c +++ b/drivers/clk/thead/clk-th1520-ap.c @@ -559,7 +559,7 @@ static struct ccu_div axi4_cpusys2_aclk =3D { .hw.init =3D CLK_HW_INIT_PARENTS_HW("axi4-cpusys2-aclk", gmac_pll_clk_parent, &ccu_div_ops, - 0), + CLK_IS_CRITICAL), }, }; =20 @@ -581,7 +581,7 @@ static struct ccu_div axi_aclk =3D { .hw.init =3D CLK_HW_INIT_PARENTS_DATA("axi-aclk", axi_parents, &ccu_div_ops, - 0), + CLK_IS_CRITICAL), }, }; =20 @@ -730,7 +730,7 @@ static struct ccu_div apb_pclk =3D { .hw.init =3D CLK_HW_INIT_PARENTS_DATA("apb-pclk", apb_parents, &ccu_div_ops, - CLK_IGNORE_UNUSED), + CLK_IS_CRITICAL), }, }; =20 @@ -761,7 +761,7 @@ static struct ccu_div vi_clk =3D { .hw.init =3D CLK_HW_INIT_PARENTS_HW("vi", video_pll_clk_parent, &ccu_div_ops, - 0), + CLK_IS_CRITICAL), }, }; =20 @@ -786,7 +786,7 @@ static struct ccu_div vo_axi_clk =3D { .hw.init =3D CLK_HW_INIT_PARENTS_HW("vo-axi", video_pll_clk_parent, &ccu_div_ops, - 0), + CLK_IS_CRITICAL), }, }; =20 @@ -811,7 +811,7 @@ static struct ccu_div vp_axi_clk =3D { .hw.init =3D CLK_HW_INIT_PARENTS_HW("vp-axi", video_pll_clk_parent, &ccu_div_ops, - CLK_IGNORE_UNUSED), + CLK_IS_CRITICAL), }, }; =20 @@ -872,27 +872,27 @@ static const struct clk_parent_data emmc_sdio_ref_clk= _pd[] =3D { static CCU_GATE(CLK_BROM, brom_clk, "brom", ahb2_cpusys_hclk_pd, 0x100, 4,= 0); static CCU_GATE(CLK_BMU, bmu_clk, "bmu", axi4_cpusys2_aclk_pd, 0x100, 5, 0= ); static CCU_GATE(CLK_AON2CPU_A2X, aon2cpu_a2x_clk, "aon2cpu-a2x", axi4_cpus= ys2_aclk_pd, - 0x134, 8, 0); + 0x134, 8, CLK_IS_CRITICAL); static CCU_GATE(CLK_X2X_CPUSYS, x2x_cpusys_clk, "x2x-cpusys", axi4_cpusys2= _aclk_pd, - 0x134, 7, 0); + 0x134, 7, CLK_IS_CRITICAL); static CCU_GATE(CLK_CPU2AON_X2H, cpu2aon_x2h_clk, "cpu2aon-x2h", axi_aclk_= pd, - 0x138, 8, CLK_IGNORE_UNUSED); + 0x138, 8, CLK_IS_CRITICAL); static CCU_GATE(CLK_CPU2PERI_X2H, cpu2peri_x2h_clk, "cpu2peri-x2h", axi4_c= pusys2_aclk_pd, - 0x140, 9, CLK_IGNORE_UNUSED); + 0x140, 9, CLK_IS_CRITICAL); static CCU_GATE(CLK_PERISYS_APB1_HCLK, perisys_apb1_hclk, "perisys-apb1-hc= lk", perisys_ahb_hclk_pd, - 0x150, 9, CLK_IGNORE_UNUSED); + 0x150, 9, CLK_IS_CRITICAL); static CCU_GATE(CLK_PERISYS_APB2_HCLK, perisys_apb2_hclk, "perisys-apb2-hc= lk", perisys_ahb_hclk_pd, - 0x150, 10, CLK_IGNORE_UNUSED); + 0x150, 10, CLK_IS_CRITICAL); static CCU_GATE(CLK_PERISYS_APB3_HCLK, perisys_apb3_hclk, "perisys-apb3-hc= lk", perisys_ahb_hclk_pd, - 0x150, 11, CLK_IGNORE_UNUSED); + 0x150, 11, CLK_IS_CRITICAL); static CCU_GATE(CLK_PERISYS_APB4_HCLK, perisys_apb4_hclk, "perisys-apb4-hc= lk", perisys_ahb_hclk_pd, 0x150, 12, 0); static const struct clk_parent_data perisys_apb4_hclk_pd[] =3D { { .hw =3D &perisys_apb4_hclk.gate.hw }, }; =20 -static CCU_GATE(CLK_NPU_AXI, npu_axi_clk, "npu-axi", axi_aclk_pd, 0x1c8, 5= , 0); -static CCU_GATE(CLK_CPU2VP, cpu2vp_clk, "cpu2vp", axi_aclk_pd, 0x1e0, 13, = 0); +static CCU_GATE(CLK_NPU_AXI, npu_axi_clk, "npu-axi", axi_aclk_pd, 0x1c8, 5= , CLK_IS_CRITICAL); +static CCU_GATE(CLK_CPU2VP, cpu2vp_clk, "cpu2vp", axi_aclk_pd, 0x1e0, 13, = CLK_IS_CRITICAL); static CCU_GATE(CLK_EMMC_SDIO, emmc_sdio_clk, "emmc-sdio", emmc_sdio_ref_c= lk_pd, 0x204, 30, 0); static CCU_GATE(CLK_GMAC1, gmac1_clk, "gmac1", gmac_pll_clk_pd, 0x204, 26,= 0); static CCU_GATE(CLK_PADCTRL1, padctrl1_clk, "padctrl1", perisys_apb_pclk_p= d, 0x204, 24, 0); @@ -936,11 +936,11 @@ static CCU_GATE(CLK_SRAM2, sram2_clk, "sram2", axi_ac= lk_pd, 0x20c, 2, 0); static CCU_GATE(CLK_SRAM3, sram3_clk, "sram3", axi_aclk_pd, 0x20c, 1, 0); =20 static CCU_GATE(CLK_AXI4_VO_ACLK, axi4_vo_aclk, "axi4-vo-aclk", - video_pll_clk_pd, 0x0, 0, 0); + video_pll_clk_pd, 0x0, 0, CLK_IS_CRITICAL); static CCU_GATE(CLK_GPU_CORE, gpu_core_clk, "gpu-core-clk", video_pll_clk_= pd, 0x0, 3, 0); static CCU_GATE(CLK_GPU_CFG_ACLK, gpu_cfg_aclk, "gpu-cfg-aclk", - video_pll_clk_pd, 0x0, 4, 0); + video_pll_clk_pd, 0x0, 4, CLK_IS_CRITICAL); static CCU_GATE(CLK_DPU_PIXELCLK0, dpu0_pixelclk, "dpu0-pixelclk", dpu0_clk_pd, 0x0, 5, CLK_SET_RATE_PARENT); static CCU_GATE(CLK_DPU_PIXELCLK1, dpu1_pixelclk, "dpu1-pixelclk", @@ -972,9 +972,9 @@ static CCU_GATE(CLK_MIPI_DSI1_REFCLK, mipi_dsi1_refclk,= "mipi-dsi1-refclk", static CCU_GATE(CLK_HDMI_I2S, hdmi_i2s_clk, "hdmi-i2s-clk", video_pll_clk_= pd, 0x0, 19, 0); static CCU_GATE(CLK_X2H_DPU1_ACLK, x2h_dpu1_aclk, "x2h-dpu1-aclk", - video_pll_clk_pd, 0x0, 20, 0); + video_pll_clk_pd, 0x0, 20, CLK_IS_CRITICAL); static CCU_GATE(CLK_X2H_DPU_ACLK, x2h_dpu_aclk, "x2h-dpu-aclk", - video_pll_clk_pd, 0x0, 21, 0); + video_pll_clk_pd, 0x0, 21, CLK_IS_CRITICAL); static CCU_GATE(CLK_AXI4_VO_PCLK, axi4_vo_pclk, "axi4-vo-pclk", video_pll_clk_pd, 0x0, 22, 0); static CCU_GATE(CLK_IOPMP_VOSYS_DPU_PCLK, iopmp_vosys_dpu_pclk, @@ -984,11 +984,11 @@ static CCU_GATE(CLK_IOPMP_VOSYS_DPU1_PCLK, iopmp_vosy= s_dpu1_pclk, static CCU_GATE(CLK_IOPMP_VOSYS_GPU_PCLK, iopmp_vosys_gpu_pclk, "iopmp-vosys-gpu-pclk", video_pll_clk_pd, 0x0, 25, 0); static CCU_GATE(CLK_IOPMP_DPU1_ACLK, iopmp_dpu1_aclk, "iopmp-dpu1-aclk", - video_pll_clk_pd, 0x0, 27, 0); + video_pll_clk_pd, 0x0, 27, CLK_IS_CRITICAL); static CCU_GATE(CLK_IOPMP_DPU_ACLK, iopmp_dpu_aclk, "iopmp-dpu-aclk", - video_pll_clk_pd, 0x0, 28, 0); + video_pll_clk_pd, 0x0, 28, CLK_IS_CRITICAL); static CCU_GATE(CLK_IOPMP_GPU_ACLK, iopmp_gpu_aclk, "iopmp-gpu-aclk", - video_pll_clk_pd, 0x0, 29, 0); + video_pll_clk_pd, 0x0, 29, CLK_IS_CRITICAL); static CCU_GATE(CLK_MIPIDSI0_PIXCLK, mipi_dsi0_pixclk, "mipi-dsi0-pixclk", video_pll_clk_pd, 0x0, 30, 0); static CCU_GATE(CLK_MIPIDSI1_PIXCLK, mipi_dsi1_pixclk, "mipi-dsi1-pixclk", --=20 2.50.1