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Sat, 16 Aug 2025 01:47:34 -0700 (PDT) From: iuncuim To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Andre Przywara , Michael Turquette , Stephen Boyd , Vinod Koul , Kishon Vijay Abraham I , Philipp Zabel Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, linux-clk@vger.kernel.org, linux-sunxi@lists.linux.dev Subject: [PATCH 1/7] clk: sunxi-ng: a523: add missing usb related clocks Date: Sat, 16 Aug 2025 16:46:54 +0800 Message-ID: <20250816084700.569524-2-iuncuim@gmail.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250816084700.569524-1-iuncuim@gmail.com> References: <20250816084700.569524-1-iuncuim@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Mikhail Kalashnikov Several clocks were omitted when adding the original driver. These clocks are necessary for USB 3.0 to work correctly. I added these declarations according to the driver's BSP code. Signed-off-by: Mikhail Kalashnikov --- drivers/clk/sunxi-ng/ccu-sun55i-a523.c | 32 +++++++++++++++++++++ drivers/clk/sunxi-ng/ccu-sun55i-a523.h | 2 +- include/dt-bindings/clock/sun55i-a523-ccu.h | 4 +++ 3 files changed, 37 insertions(+), 1 deletion(-) diff --git a/drivers/clk/sunxi-ng/ccu-sun55i-a523.c b/drivers/clk/sunxi-ng/= ccu-sun55i-a523.c index 1a9a1cb86..7bf41e628 100644 --- a/drivers/clk/sunxi-ng/ccu-sun55i-a523.c +++ b/drivers/clk/sunxi-ng/ccu-sun55i-a523.c @@ -853,6 +853,31 @@ static struct ccu_mux usb_ohci1_clk =3D { }, }; =20 +static SUNXI_CCU_GATE_DATA(usb2_clk, "usb2", osc24M, 0xa80, BIT(31), 0); + +static const struct clk_parent_data usb3_parents[] =3D { + { .fw_name =3D "hosc" }, + { .hw =3D &pll_periph0_200M_clk.hw }, + { .hw =3D &pll_periph1_200M_clk.hw }, +}; + +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(usb3_clk, "usb3", usb3_parents, 0xa8= 4, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_parent_data usb3_suspend_parents[] =3D { + { .fw_name =3D "losc" }, +}; + +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(usb3_suspend_clk, "usb3-suspend", + usb3_suspend_parents, 0xa88, + 0, 5, /* M */ + 24, 1, /* mux */ + BIT(31), /* gate */ + 0); + static SUNXI_CCU_GATE_HWS(bus_ohci0_clk, "bus-ohci0", ahb_hws, 0xa8c, BIT(0), 0); static SUNXI_CCU_GATE_HWS(bus_ohci1_clk, "bus-ohci1", ahb_hws, 0xa8c, @@ -1290,6 +1315,9 @@ static struct ccu_common *sun55i_a523_ccu_clks[] =3D { &bus_ths_clk.common, &usb_ohci0_clk.common, &usb_ohci1_clk.common, + &usb2_clk.common, + &usb3_clk.common, + &usb3_suspend_clk.common, &bus_ohci0_clk.common, &bus_ohci1_clk.common, &bus_ehci0_clk.common, @@ -1422,6 +1450,7 @@ static struct clk_hw_onecell_data sun55i_a523_hw_clks= =3D { [CLK_MBUS_DMA] =3D &mbus_dma_clk.common.hw, [CLK_MBUS_VE] =3D &mbus_ve_clk.common.hw, [CLK_MBUS_CE] =3D &mbus_ce_clk.common.hw, + [CLK_MBUS_USB3] =3D &mbus_usb3_clk.common.hw, [CLK_MBUS_CSI] =3D &mbus_csi_clk.common.hw, [CLK_MBUS_ISP] =3D &mbus_isp_clk.common.hw, [CLK_MBUS_EMAC1] =3D &mbus_gmac1_clk.common.hw, @@ -1474,6 +1503,9 @@ static struct clk_hw_onecell_data sun55i_a523_hw_clks= =3D { [CLK_BUS_THS] =3D &bus_ths_clk.common.hw, [CLK_USB_OHCI0] =3D &usb_ohci0_clk.common.hw, [CLK_USB_OHCI1] =3D &usb_ohci1_clk.common.hw, + [CLK_USB2] =3D &usb2_clk.common.hw, + [CLK_USB3] =3D &usb3_clk.common.hw, + [CLK_USB3_SUSPEND] =3D &usb3_suspend_clk.common.hw, [CLK_BUS_OHCI0] =3D &bus_ohci0_clk.common.hw, [CLK_BUS_OHCI1] =3D &bus_ohci1_clk.common.hw, [CLK_BUS_EHCI0] =3D &bus_ehci0_clk.common.hw, diff --git a/drivers/clk/sunxi-ng/ccu-sun55i-a523.h b/drivers/clk/sunxi-ng/= ccu-sun55i-a523.h index fc8dd42f1..d6916c728 100644 --- a/drivers/clk/sunxi-ng/ccu-sun55i-a523.h +++ b/drivers/clk/sunxi-ng/ccu-sun55i-a523.h @@ -9,6 +9,6 @@ #include #include =20 -#define CLK_NUMBER (CLK_FANOUT2 + 1) +#define CLK_NUMBER (CLK_MBUS_USB3 + 1) =20 #endif /* _CCU_SUN55I_A523_H */ diff --git a/include/dt-bindings/clock/sun55i-a523-ccu.h b/include/dt-bindi= ngs/clock/sun55i-a523-ccu.h index c8259ac5a..26b2e9dc8 100644 --- a/include/dt-bindings/clock/sun55i-a523-ccu.h +++ b/include/dt-bindings/clock/sun55i-a523-ccu.h @@ -185,5 +185,9 @@ #define CLK_FANOUT0 176 #define CLK_FANOUT1 177 #define CLK_FANOUT2 178 +#define CLK_USB2 179 +#define CLK_USB3 180 +#define CLK_USB3_SUSPEND 181 +#define CLK_MBUS_USB3 182 =20 #endif /* _DT_BINDINGS_CLK_SUN55I_A523_CCU_H_ */ --=20 2.50.1 From nobody Sat Oct 4 12:41:14 2025 Received: from mail-pl1-f175.google.com (mail-pl1-f175.google.com [209.85.214.175]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2A3BE23AE95; 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charset="utf-8" From: Mikhail Kalashnikov It seems that there are actually three usb2 phys in the processor, which makes it incompatible with D1. The third phy is used together with USB3/PCIe combophy with DWC3 controller. In the BSP code, the third PHY requires a separate glue driver, but it seems that it is not needed. According to the BSP code, the third phy does not have a reset line; the only reset is declared in the DWC3 node, but none of this is documented. Since sun4i-usb-phy driver requires a reset, I added RST_BUS_3 here. Signed-off-by: Mikhail Kalashnikov --- .../arm64/boot/dts/allwinner/sun55i-a523.dtsi | 21 ++++++++++++------- 1 file changed, 13 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi b/arch/arm64/bo= ot/dts/allwinner/sun55i-a523.dtsi index 6b6f2296b..e4ed4fa82 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi @@ -503,22 +503,27 @@ usb_otg: usb@4100000 { }; =20 usbphy: phy@4100400 { - compatible =3D "allwinner,sun55i-a523-usb-phy", - "allwinner,sun20i-d1-usb-phy"; + compatible =3D "allwinner,sun55i-a523-usb-phy"; reg =3D <0x4100400 0x100>, <0x4101800 0x100>, - <0x4200800 0x100>; + <0x4200800 0x100>, + <0x4e00000 0x100>; reg-names =3D "phy_ctrl", "pmu0", - "pmu1"; + "pmu1", + "pmu2"; clocks =3D <&osc24M>, - <&osc24M>; + <&osc24M>, + <&ccu CLK_USB2>; clock-names =3D "usb0_phy", - "usb1_phy"; + "usb1_phy", + "usb2_phy"; resets =3D <&ccu RST_USB_PHY0>, - <&ccu RST_USB_PHY1>; + <&ccu RST_USB_PHY1>, + <&ccu RST_BUS_3>; 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Sat, 16 Aug 2025 01:47:54 -0700 (PDT) From: iuncuim To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Andre Przywara , Michael Turquette , Stephen Boyd , Vinod Koul , Kishon Vijay Abraham I , Philipp Zabel Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, linux-clk@vger.kernel.org, linux-sunxi@lists.linux.dev Subject: [PATCH 3/7] phy: sun4i-usb: a523: add support for the USB2 PHY Date: Sat, 16 Aug 2025 16:46:56 +0800 Message-ID: <20250816084700.569524-4-iuncuim@gmail.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250816084700.569524-1-iuncuim@gmail.com> References: <20250816084700.569524-1-iuncuim@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Mikhail Kalashnikov Previously, USB PHY was compatible with D1 and did not require separatedata options. But now we need to add a third PHY, which makes it incompatible. The third PHY is used together with USB3/PCIe combophy with DWC3 controller. In the BSP code, the third PHY requires a separate glue driver, but it seems that it is not needed. Signed-off-by: Mikhail Kalashnikov --- drivers/phy/allwinner/phy-sun4i-usb.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c b/drivers/phy/allwinner/= phy-sun4i-usb.c index 8873aed3a..bb79339f2 100644 --- a/drivers/phy/allwinner/phy-sun4i-usb.c +++ b/drivers/phy/allwinner/phy-sun4i-usb.c @@ -1025,6 +1025,15 @@ static const struct sun4i_usb_phy_cfg sun50i_h616_cf= g =3D { .siddq_in_base =3D true, }; =20 +static const struct sun4i_usb_phy_cfg sun55i_a523_cfg =3D { + .num_phys =3D 3, + .phyctl_offset =3D REG_PHYCTL_A33, + .dedicated_clocks =3D true, + .hci_phy_ctl_clear =3D PHY_CTL_SIDDQ, + .phy0_dual_route =3D true, + .siddq_in_base =3D true, +}; + static const struct of_device_id sun4i_usb_phy_of_match[] =3D { { .compatible =3D "allwinner,sun4i-a10-usb-phy", .data =3D &sun4i_a10_cfg= }, { .compatible =3D "allwinner,sun5i-a13-usb-phy", .data =3D &sun5i_a13_cfg= }, @@ -1041,6 +1050,7 @@ static const struct of_device_id sun4i_usb_phy_of_mat= ch[] =3D { .data =3D &sun50i_a64_cfg}, { .compatible =3D "allwinner,sun50i-h6-usb-phy", .data =3D &sun50i_h6_cfg= }, { .compatible =3D "allwinner,sun50i-h616-usb-phy", .data =3D &sun50i_h616= _cfg }, + { .compatible =3D "allwinner,sun55i-a523-usb-phy", .data =3D &sun55i_a523= _cfg }, { .compatible =3D "allwinner,suniv-f1c100s-usb-phy", .data =3D &suniv_f1c100s_cfg }, { }, --=20 2.50.1 From nobody Sat Oct 4 12:41:14 2025 Received: from mail-pf1-f178.google.com (mail-pf1-f178.google.com [209.85.210.178]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3E63E23AE95; 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Sat, 16 Aug 2025 01:48:04 -0700 (PDT) Received: from junAIR ([212.192.12.80]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2446d57f12esm31048215ad.157.2025.08.16.01.47.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 16 Aug 2025 01:48:04 -0700 (PDT) From: iuncuim To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Andre Przywara , Michael Turquette , Stephen Boyd , Vinod Koul , Kishon Vijay Abraham I , Philipp Zabel Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, linux-clk@vger.kernel.org, linux-sunxi@lists.linux.dev Subject: [PATCH 4/7] phy: allwinner: a523: add USB3/PCIe PHY driver Date: Sat, 16 Aug 2025 16:46:57 +0800 Message-ID: <20250816084700.569524-5-iuncuim@gmail.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250816084700.569524-1-iuncuim@gmail.com> References: <20250816084700.569524-1-iuncuim@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Mikhail Kalashnikov The A523 family of processors features a combophy for USB 3.0 and PCIe, developed by Innosilicon. Simultaneous operation of both interfaces is not supported by design. Currently, the driver only adds support for USB 3.0. PCIe support is currently unavailable and will be added later. All data on phy configuration is taken from the manufacturer's BSP driver. Signed-off-by: Mikhail Kalashnikov --- drivers/phy/allwinner/Kconfig | 9 + drivers/phy/allwinner/Makefile | 1 + drivers/phy/allwinner/phy-sun55i-usb3-pcie.c | 267 +++++++++++++++++++ 3 files changed, 277 insertions(+) create mode 100644 drivers/phy/allwinner/phy-sun55i-usb3-pcie.c diff --git a/drivers/phy/allwinner/Kconfig b/drivers/phy/allwinner/Kconfig index fb584518b..af2a82e51 100644 --- a/drivers/phy/allwinner/Kconfig +++ b/drivers/phy/allwinner/Kconfig @@ -57,3 +57,12 @@ config PHY_SUN50I_USB3 part of Allwinner H6 SoC. =20 This driver controls each individual USB 2+3 host PHY combo. + +config PHY_SUN55I_USB3_PCIE + tristate "Allwinner A523 Innosilicon USB3/PCIe Combophy Driver" + depends on ARCH_SUNXI || COMPILE_TEST + depends on RESET_CONTROLLER + select GENERIC_PHY + help + Enable this to support the Allwinner PCIe/USB3.0 combo PHY + with Innosilicon IP block founded in A523/A527/H728/T527 SOC diff --git a/drivers/phy/allwinner/Makefile b/drivers/phy/allwinner/Makefile index bd74901a1..5948a27ef 100644 --- a/drivers/phy/allwinner/Makefile +++ b/drivers/phy/allwinner/Makefile @@ -3,3 +3,4 @@ obj-$(CONFIG_PHY_SUN4I_USB) +=3D phy-sun4i-usb.o obj-$(CONFIG_PHY_SUN6I_MIPI_DPHY) +=3D phy-sun6i-mipi-dphy.o obj-$(CONFIG_PHY_SUN9I_USB) +=3D phy-sun9i-usb.o obj-$(CONFIG_PHY_SUN50I_USB3) +=3D phy-sun50i-usb3.o +obj-$(CONFIG_PHY_SUN55I_USB3_PCIE) +=3D phy-sun55i-usb3-pcie.o diff --git a/drivers/phy/allwinner/phy-sun55i-usb3-pcie.c b/drivers/phy/all= winner/phy-sun55i-usb3-pcie.c new file mode 100644 index 000000000..905c54a67 --- /dev/null +++ b/drivers/phy/allwinner/phy-sun55i-usb3-pcie.c @@ -0,0 +1,267 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Driver for Innosilicon USB3.0/PCIe phy found in Allwinner A523 processo= rs. + * Currently, the driver only supports the USB3.0 part. + * + * Copyright (C) 2025 Mikhail Kalashnikov + * Based on phy-sun50i-usb3.c, which is: + * Copyright (C) 2017 Icenowy Zheng + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define PHY_SYS_VER 0x00 + +#define PHY_USB3_BGR 0x08 +/* Control bits for the USB3 part */ +#define USB3_RESETN BIT(0) +#define USB3_ACLK_EN BIT(17) +#define USB3_HCLK_EN BIT(16) + +#define PHY_CTL 0x10 +/* Control bits for the common part */ +#define PHY_RSTN BIT(0) +/* Bit for selecting internal(0) or external(1) clock */ +#define PHY_CLK_SEL BIT(30) +/* Bit for selecting PCIe(0) or USB3(1) role */ +#define PHY_USE_SEL BIT(31) + +#define PHY_CLK_OFFSET 0x80000 + +struct sun55i_usb3_pcie_phy { + struct device *dev; + struct phy *phy; + void __iomem *regs; + void __iomem *regs_clk; + struct reset_control *reset; + struct clk *clk; +}; + +/* + * These values are derived from the manufacturer's driver code. + * Comments are preserved. + */ +static void sun55i_usb3_phy_open(struct sun55i_usb3_pcie_phy *phy) +{ + u32 val; + + val =3D readl(phy->regs_clk + 0x1418); + val &=3D ~(GENMASK(17, 16)); + val |=3D BIT(25); + writel(val, phy->regs_clk + 0x1418); + + /* reg_rx_eq_bypass[3]=3D1, rx_ctle_res_cal_bypass */ + val =3D readl(phy->regs_clk + 0x674); + val |=3D BIT(3); + writel(val, phy->regs_clk + 0x674); + + /* rx_ctle_res_cal=3D0xf, 0x4->0xf */ + val =3D readl(phy->regs_clk + 0x704); + val |=3D BIT(8) | BIT(9) | BIT(11); + writel(val, phy->regs_clk + 0x704); + + /* CDR_div_fin_gain1 */ + val =3D readl(phy->regs_clk + 0x400); + val |=3D BIT(4); + writel(val, phy->regs_clk + 0x400); + + /* CDR_div1_fin_gain1 */ + val =3D readl(phy->regs_clk + 0x404); + val |=3D GENMASK(3, 0); + val |=3D BIT(5); + writel(val, phy->regs_clk + 0x404); + + /* CDR_div3_fin_gain1 */ + val =3D readl(phy->regs_clk + 0x408); + val |=3D BIT(5); + writel(val, phy->regs_clk + 0x408); + + val =3D readl(phy->regs_clk + 0x109c); + val |=3D BIT(1); + writel(val, phy->regs_clk + 0x109c); + + /* SSC configure */ + /* div_N */ + val =3D readl(phy->regs_clk + 0x107c); + val &=3D ~(GENMASK(17, 12)); + val |=3D BIT(12); + writel(val, phy->regs_clk + 0x107c); + + /* modulation freq div */ + val =3D readl(phy->regs_clk + 0x1020); + val &=3D ~(GENMASK(4, 0)); + val |=3D BIT(1) | BIT(2); + writel(val, phy->regs_clk + 0x1020); + + /* spread[6:0], 400*9=3D4410ppm ssc */ + val =3D readl(phy->regs_clk + 0x1034); + val &=3D ~(GENMASK(22, 16)); + val |=3D BIT(16) | BIT(19); + writel(val, phy->regs_clk + 0x1034); + + val =3D readl(phy->regs_clk + 0x101c); + /* don't disable ssc =3D 0 */ + val &=3D ~BIT(28); + /* choose downspread */ + val |=3D BIT(27); + writel(val, phy->regs_clk + 0x101c); +} + +static int sun55i_usb3_pcie_clk_init(struct sun55i_usb3_pcie_phy *phy) +{ + u32 val; + int ret; + + ret =3D clk_prepare_enable(phy->clk); + if (ret) + return ret; + + ret =3D reset_control_deassert(phy->reset); + if (ret) { + clk_disable_unprepare(phy->clk); + return ret; + } + + val =3D readl(phy->regs + PHY_CTL); + val |=3D PHY_USE_SEL | PHY_RSTN; + val &=3D ~PHY_CLK_SEL; + writel(val, phy->regs + PHY_CTL); + + val =3D readl(phy->regs + PHY_USB3_BGR); + val |=3D USB3_ACLK_EN | USB3_HCLK_EN | USB3_RESETN; + writel(val, phy->regs + PHY_USB3_BGR); + + return 0; +} + +static int sun55i_usb3_pcie_phy_init(struct phy *_phy) +{ + struct sun55i_usb3_pcie_phy *phy =3D phy_get_drvdata(_phy); + + sun55i_usb3_phy_open(phy); + + return 0; +} + +static int sun55i_usb3_pcie_phy_exit(struct phy *_phy) +{ + struct sun55i_usb3_pcie_phy *phy =3D phy_get_drvdata(_phy); + + reset_control_assert(phy->reset); + clk_disable_unprepare(phy->clk); + + return 0; +} + +static void sun55i_usb3_pcie_phy_power_set(struct phy *_phy, bool on) +{ + struct sun55i_usb3_pcie_phy *phy =3D phy_get_drvdata(_phy); + u32 val; + + val =3D readl(phy->regs_clk + 0x14); + val =3D on ? (val & ~BIT(26)) : (val | BIT(26)); + writel(val, phy->regs_clk + 0x14); + + val =3D readl(phy->regs_clk); + val =3D on ? (val & ~BIT(10)) : (val | BIT(10)); + writel(val, phy->regs_clk); +} + +static int sun55i_usb3_pcie_phy_power_on(struct phy *_phy) +{ + sun55i_usb3_pcie_phy_power_set(_phy, true); + + return 0; +} + +static int sun55i_usb3_pcie_phy_power_off(struct phy *_phy) +{ + sun55i_usb3_pcie_phy_power_set(_phy, false); + + return 0; +} + +static const struct phy_ops sun55i_usb3_pcie_phy_ops =3D { + .init =3D sun55i_usb3_pcie_phy_init, + .exit =3D sun55i_usb3_pcie_phy_exit, + .power_on =3D sun55i_usb3_pcie_phy_power_on, + .power_off =3D sun55i_usb3_pcie_phy_power_off, + .owner =3D THIS_MODULE, +}; + +static int sun55i_usb3_pcie_phy_probe(struct platform_device *pdev) +{ + struct sun55i_usb3_pcie_phy *phy; + struct device *dev =3D &pdev->dev; + struct phy_provider *phy_provider; + int ret; + + phy =3D devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL); + if (!phy) + return -ENOMEM; + + phy->dev =3D dev; + phy->clk =3D devm_clk_get(dev, NULL); + if (IS_ERR(phy->clk)) { + if (PTR_ERR(phy->clk) !=3D -EPROBE_DEFER) + dev_err(dev, "failed to get phy clock\n"); + return PTR_ERR(phy->clk); + } + + phy->reset =3D devm_reset_control_get(dev, NULL); + if (IS_ERR(phy->reset)) { + dev_err(dev, "failed to get reset control\n"); + return PTR_ERR(phy->reset); + } + + phy->regs =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(phy->regs)) + return PTR_ERR(phy->regs); + + phy->regs_clk =3D phy->regs + PHY_CLK_OFFSET; + if (IS_ERR(phy->regs_clk)) + return PTR_ERR(phy->regs_clk); + + phy->phy =3D devm_phy_create(dev, NULL, &sun55i_usb3_pcie_phy_ops); + if (IS_ERR(phy->phy)) { + dev_err(dev, "failed to create PHY\n"); + return PTR_ERR(phy->phy); + } + + phy_set_drvdata(phy->phy, phy); + phy_provider =3D devm_of_phy_provider_register(dev, of_phy_simple_xlate); + + ret =3D sun55i_usb3_pcie_clk_init(phy); + if (ret) + return ret; + dev_info(phy->dev, "phy version is: 0x%x\n", readl(phy->regs)); + + return PTR_ERR_OR_ZERO(phy_provider); +} + +static const struct of_device_id sun55i_usb3_pcie_phy_of_match[] =3D { + { .compatible =3D "allwinner,sun55i-a523-usb3-pcie-phy" }, + { }, +}; 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charset="utf-8" From: Mikhail Kalashnikov After adding the phy driver, we can also add phy node. In addition to the clk and reset lines, the power domain PD_PCIE is declared in this node according to the bsp dtb. So let's mention it.=20 Currently, phy driver does not support role selection and only works in USB3.0 mode. Signed-off-by: Mikhail Kalashnikov --- arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi b/arch/arm64/bo= ot/dts/allwinner/sun55i-a523.dtsi index e4ed4fa82..233365496 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi @@ -606,6 +606,16 @@ mdio0: mdio { }; }; =20 + combophy: phy@4f00000 { + compatible =3D "allwinner,sun55i-a523-usb3-pcie-phy"; + reg =3D <0x04f00000 0x100000>; + clocks =3D <&ccu CLK_USB3>; + resets =3D <&ccu RST_BUS_PCIE_USB3>; + #phy-cells =3D <0>; + power-domains =3D <&pck600 PD_PCIE>; + status =3D "disabled"; + }; + ppu: power-controller@7001400 { compatible =3D "allwinner,sun55i-a523-ppu"; reg =3D <0x07001400 0x400>; --=20 2.50.1 From nobody Sat Oct 4 12:41:14 2025 Received: from mail-pg1-f173.google.com (mail-pg1-f173.google.com [209.85.215.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A1B0D23BF83; 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charset="utf-8" From: Mikhail Kalashnikov After adding the phy bindings, we can also add dwc3 node, which uses the previously added usbphy2 and part of usb3 from combophy. All settings declared in dwc3 node are obtained from the x96qproplus' dtb. BSP contains an additional glue driver for dwc3, but it seems that it is not needed. Signed-off-by: Mikhail Kalashnikov --- .../arm64/boot/dts/allwinner/sun55i-a523.dtsi | 21 +++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi b/arch/arm64/bo= ot/dts/allwinner/sun55i-a523.dtsi index 233365496..ec170888a 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi @@ -606,6 +606,27 @@ mdio0: mdio { }; }; =20 + dwc3: usb@4d00000 { + compatible =3D "snps,dwc3"; + reg =3D <0x04d00000 0x100000>; + interrupts =3D ; + dr_mode =3D "host"; + clocks =3D <&ccu CLK_MBUS_USB3>, <&ccu CLK_USB3>, + <&ccu CLK_USB2>, <&ccu CLK_USB3_SUSPEND>; + clock-names =3D "bus_clk", "ref_clk3", "ref_clk2", "suspend"; + maximum-speed =3D "super-speed"; + phy_type =3D "utmi"; + snps,dis_enblslpm_quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,dis_u3_susphy_quirk; + snps,dis_u2_susphy_quirk; + snps,dis_rxdet_inp3_quirk; + phys =3D <&usbphy 2>, <&combophy>; + phy-names =3D "usb2-phy", "usb3-phy"; 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Sat, 16 Aug 2025 01:48:30 -0700 (PDT) From: iuncuim To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Andre Przywara , Michael Turquette , Stephen Boyd , Vinod Koul , Kishon Vijay Abraham I , Philipp Zabel Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, linux-clk@vger.kernel.org, linux-sunxi@lists.linux.dev Subject: [PATCH 7/7] arm64: dts: allwinner: a523: activate USB3 for all boards Date: Sat, 16 Aug 2025 16:47:00 +0800 Message-ID: <20250816084700.569524-8-iuncuim@gmail.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250816084700.569524-1-iuncuim@gmail.com> References: <20250816084700.569524-1-iuncuim@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Mikhail Kalashnikov Currently, these devices have a USB 3.0 port. Therefore, we can activate it. Signed-off-by: Mikhail Kalashnikov --- arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts | 8 ++++++++ arch/arm64/boot/dts/allwinner/sun55i-h728-x96qpro+.dts | 8 ++++++++ arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts | 8 ++++++++ 3 files changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts b/arch= /arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts index 553ad774e..6842f8e8d 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts +++ b/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts @@ -47,6 +47,14 @@ reg_usb_vbus: vbus { }; }; =20 +&combophy { + status =3D "okay"; +}; + +&dwc3 { + status =3D "okay"; +}; + &ehci0 { status =3D "okay"; }; diff --git a/arch/arm64/boot/dts/allwinner/sun55i-h728-x96qpro+.dts b/arch/= arm64/boot/dts/allwinner/sun55i-h728-x96qpro+.dts index a96927fbd..19388bc11 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-h728-x96qpro+.dts +++ b/arch/arm64/boot/dts/allwinner/sun55i-h728-x96qpro+.dts @@ -46,6 +46,14 @@ reg_vcc3v3: vcc3v3 { }; }; =20 +&combophy { + status =3D "okay"; +}; + +&dwc3 { + status =3D "okay"; +}; + &ehci0 { status =3D "okay"; }; diff --git a/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts b/arch= /arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts index b9eeb6753..6f05cd297 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts +++ b/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts @@ -57,6 +57,14 @@ reg_usb_vbus: vbus { }; }; =20 +&combophy { + status =3D "okay"; +}; + +&dwc3 { + status =3D "okay"; +}; + &ehci0 { status =3D "okay"; }; --=20 2.50.1