From nobody Sat Oct 4 12:41:16 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 22DE81F582A; Fri, 15 Aug 2025 16:55:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755276926; cv=none; b=h0RMSnmhE2FsKzVhZqlNGqtxbdoIM6HjaHPbdXHhpNlOZriWa2fN6RkXVEbAYdCIUqw2XZfanMqPK8wLrTc72T+mAUuj2tOkmhL0amsgpCeDyj78hB7wsJHcyUufzcHgtcFAkjSkAM4dDVbC75BO1uxOuROSEqCYeKBWWpI7Ga8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755276926; c=relaxed/simple; bh=inws8rGfKLYVfokZMZsnBzF7qQWjCw/1Z/VQ/H87srg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=CpiU5QZkyjGL2Bn6Hz5QyOcBqpRigYKjP5GqkOrkjhfBkgDWMTZALm4LbqFZv4YrAfk0WawKQ3yX7ldS5LRKZmJrnQCb9zTY9SU48ULCcllykkeYFsGpihg73OH+8M80CoEY+RpxtvwF96kEDtgFAixwwdn17dvFmr56HpyKTuQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=D6EZQOYO; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="D6EZQOYO" Received: by smtp.kernel.org (Postfix) with ESMTPS id CB57DC4CEF5; Fri, 15 Aug 2025 16:55:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755276925; bh=inws8rGfKLYVfokZMZsnBzF7qQWjCw/1Z/VQ/H87srg=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=D6EZQOYOAUAeF305N1gV7XWP8PF60SeQAOjLMO1wlTgas6veveIMLTz2fnidz4Oud MBlT+tUJBdT2vTIoqV7HNodxVm56PUe6uX4yrHIgZ0N9Nz+XJxoUgztaIG9Zqjyzfp FTaX3rEtIAcmi+r3E0BWxyri9Kr7Nke5dLq6on1qne25HkZ4DjjXw3HYTfuulfG1Qf h1F1nKc7xxYp/slEvjKOo1513TSPOxA4UK9Fyb8dRDqvgN/fEXfbjq1Bb+OFXQyl8n JvuJPqVf84UATwehLRVjdeeeix5KdgoczSsPe0THCCw4Oqmnoc3845oP1d85TXiv1b ++Pk/8wWvYmcw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id C2C56CA0ED1; Fri, 15 Aug 2025 16:55:25 +0000 (UTC) From: Rohan G Thomas via B4 Relay Date: Sat, 16 Aug 2025 00:55:23 +0800 Subject: [PATCH net-next v2 1/3] net: stmmac: xgmac: Do not enable RX FIFO Overflow interrupts Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250816-xgmac-minor-fixes-v2-1-699552cf8a7f@altera.com> References: <20250816-xgmac-minor-fixes-v2-0-699552cf8a7f@altera.com> In-Reply-To: <20250816-xgmac-minor-fixes-v2-0-699552cf8a7f@altera.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Alexandre Torgue , Serge Semin , Romain Gantois , Jose Abreu , Ong Boon Leong Cc: netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rohan G Thomas , Matthew Gerlach , Andrew Lunn X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1755276924; l=1566; i=rohan.g.thomas@altera.com; s=20250815; h=from:subject:message-id; bh=E0GCiOkgubMN2NevEVBVfzpHtZM3l1Fx7YIgaGSXhBE=; b=OAU0E3PwMrRPvcg/pVQaA9iV5Ql2eiNQoRq+NwfecsLEHn+IbcprNx58bAx8/1GqsKDlnfZ81 uRjhsjDGB0fA/n07LCtDi99v7dWkmYGkYG6I80P8piIOVSRWcgMpRt7 X-Developer-Key: i=rohan.g.thomas@altera.com; a=ed25519; pk=5yZXkXswhfUILKAQwoIn7m6uSblwgV5oppxqde4g4TY= X-Endpoint-Received: by B4 Relay for rohan.g.thomas@altera.com/20250815 with auth_id=494 X-Original-From: Rohan G Thomas Reply-To: rohan.g.thomas@altera.com From: Rohan G Thomas Enabling RX FIFO Overflow interrupts is counterproductive and causes an interrupt storm when RX FIFO overflows. Disabling this interrupt has no side effect and eliminates interrupt storms when the RX FIFO overflows. Commit 8a7cb245cf28 ("net: stmmac: Do not enable RX FIFO overflow interrupts") disables RX FIFO overflow interrupts for DWMAC4 IP and removes the corresponding handling of this interrupt. This patch is doing the same thing for XGMAC IP. Fixes: 2142754f8b9c ("net: stmmac: Add MAC related callbacks for XGMAC2") Signed-off-by: Rohan G Thomas Reviewed-by: Matthew Gerlach Reviewed-by: Andrew Lunn --- drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c b/drivers/n= et/ethernet/stmicro/stmmac/dwxgmac2_dma.c index 5dcc95bc0ad28b756accf9670c5fa00aa94fcfe3..7201a38842651a865493fce0cef= e757d6ae9bafa 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c @@ -203,10 +203,6 @@ static void dwxgmac2_dma_rx_mode(struct stmmac_priv *p= riv, void __iomem *ioaddr, } =20 writel(value, ioaddr + XGMAC_MTL_RXQ_OPMODE(channel)); - - /* Enable MTL RX overflow */ - value =3D readl(ioaddr + XGMAC_MTL_QINTEN(channel)); - writel(value | XGMAC_RXOIE, ioaddr + XGMAC_MTL_QINTEN(channel)); } =20 static void dwxgmac2_dma_tx_mode(struct stmmac_priv *priv, void __iomem *i= oaddr, --=20 2.32.0 From nobody Sat Oct 4 12:41:16 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 29A012E5D01; Fri, 15 Aug 2025 16:55:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755276926; cv=none; b=aD69kpTPqkbDUizQQluH4KKtyiitR1Dev4d8d4SPlcuCL6oN2jbVFd7JZ2AL+Orxn76uEAJPD0hPcJgwpXybEWqGNHUbBFEcOZs0Ta2X+Ufofa62H42WO2jkT6duUVZ3s6Zadp9Q2gAogtFaAXKusE7SaijZvg5g5q8xG5oC480= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755276926; c=relaxed/simple; bh=6xBCAXnSlcx0bxZ2sjWbWn7Mur09UyOs+oTuzhzmA4E=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=tqLtjQye+talf3QGEPDA7ccZJeYd7zTkLJlViVPNDHVeq1yYF9vyGexjxlianjdAahVE8xIJ7Xz2Dqa+3KugNW41BP4MQXH+f+f/K5JdMeWTaRlABKnZppR1C8z4BF1YY507lUxuGtc1v6RZ3qd2YXkY18j4DWpDmXOwPudFNBc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=u9qsoYtY; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="u9qsoYtY" Received: by smtp.kernel.org (Postfix) with ESMTPS id DEE28C4CEEB; Fri, 15 Aug 2025 16:55:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755276925; bh=6xBCAXnSlcx0bxZ2sjWbWn7Mur09UyOs+oTuzhzmA4E=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=u9qsoYtY8xbYZ62xiDLN2pNUkxMPq+P8OJKsfLpLbk/e4cN3+NwnyP4WyWtue/jmQ vaXDxlTXA0dGpVLyw+MM8WqrpU7RLfaVM66oemPeruiCR4o+Jrp4JARDBMG42/oxM7 d88Jn+d0MDNbBGqIWg3fItjbJk4CgNPrMWtf3v3VX2nrL5gooQm0+2LbtiyPEMGJWT BWqtr/w4I7KM7ZyqJKpeOzfwWbIeo3Lxk1dz3XiQbTCeNqQETPg6cNcwbyuRNhaU7m KRY9p5yOfjWXBE0ZvcWiXLBzuh5PbCMY6YL/8L/tWkFUlVblLg2P8ARh22MmE3QYFG 4jtCs1GxjUBtg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id D1483CA0EE9; Fri, 15 Aug 2025 16:55:25 +0000 (UTC) From: Rohan G Thomas via B4 Relay Date: Sat, 16 Aug 2025 00:55:24 +0800 Subject: [PATCH net-next v2 2/3] net: stmmac: xgmac: Correct supported speed modes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250816-xgmac-minor-fixes-v2-2-699552cf8a7f@altera.com> References: <20250816-xgmac-minor-fixes-v2-0-699552cf8a7f@altera.com> In-Reply-To: <20250816-xgmac-minor-fixes-v2-0-699552cf8a7f@altera.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Alexandre Torgue , Serge Semin , Romain Gantois , Jose Abreu , Ong Boon Leong Cc: netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rohan G Thomas , Matthew Gerlach X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1755276924; l=3618; i=rohan.g.thomas@altera.com; s=20250815; h=from:subject:message-id; bh=6eGqFb1P97Yuh/qwyhD4J2RxKPXc8iQ4mAKJ/Gaog14=; b=sS1sFpVUZEdaR1i/EWOsh3aSr1uMvAn4QF0IyWlIZCG0RUR15KLjXCU+GLHuNspxJCNcqz+x9 4ZfPlJ4tFGKC+mEafY40fO7taTEU3awXeEsWJEe8KBPsQu4atO8Vj/Y X-Developer-Key: i=rohan.g.thomas@altera.com; a=ed25519; pk=5yZXkXswhfUILKAQwoIn7m6uSblwgV5oppxqde4g4TY= X-Endpoint-Received: by B4 Relay for rohan.g.thomas@altera.com/20250815 with auth_id=494 X-Original-From: Rohan G Thomas Reply-To: rohan.g.thomas@altera.com From: Rohan G Thomas Correct supported speed modes as per the XGMAC databook. Commit 9cb54af214a7 ("net: stmmac: Fix IP-cores specific MAC capabilities") removes support for 10M, 100M and 1000HD. 1000HD is not supported by XGMAC IP, but it does support 10M and 100M FD mode for XGMAC version >=3D 2_20, and it also supports 10M and 100M HD mode if the HDSEL bit is set in the MAC_HW_FEATURE0 reg. This commit enables support for 10M and 100M speed modes for XGMAC IP based on XGMAC version and MAC capabilities. Fixes: 9cb54af214a7 ("net: stmmac: Fix IP-cores specific MAC capabilities") Signed-off-by: Rohan G Thomas Reviewed-by: Matthew Gerlach --- drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c | 13 +++++++++++-- drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c | 5 +++++ 2 files changed, 16 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c b/drivers/= net/ethernet/stmicro/stmmac/dwxgmac2_core.c index 6cadf8de4fdfdb18af1a112b883b3d33a53da638..00e929bf280baec7aa8d2a75fc5= ceea4a52c9979 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c @@ -49,6 +49,14 @@ static void dwxgmac2_core_init(struct mac_device_info *h= w, writel(XGMAC_INT_DEFAULT_EN, ioaddr + XGMAC_INT_EN); } =20 +static void dwxgmac2_update_caps(struct stmmac_priv *priv) +{ + if (!priv->dma_cap.mbps_10_100) + priv->hw->link.caps &=3D ~(MAC_10 | MAC_100); + else if (!priv->dma_cap.half_duplex) + priv->hw->link.caps &=3D ~(MAC_10HD | MAC_100HD); +} + static void dwxgmac2_set_mac(void __iomem *ioaddr, bool enable) { u32 tx =3D readl(ioaddr + XGMAC_TX_CONFIG); @@ -1424,6 +1432,7 @@ static void dwxgmac2_set_arp_offload(struct mac_devic= e_info *hw, bool en, =20 const struct stmmac_ops dwxgmac210_ops =3D { .core_init =3D dwxgmac2_core_init, + .update_caps =3D dwxgmac2_update_caps, .set_mac =3D dwxgmac2_set_mac, .rx_ipc =3D dwxgmac2_rx_ipc, .rx_queue_enable =3D dwxgmac2_rx_queue_enable, @@ -1532,8 +1541,8 @@ int dwxgmac2_setup(struct stmmac_priv *priv) mac->mcast_bits_log2 =3D ilog2(mac->multicast_filter_bins); =20 mac->link.caps =3D MAC_ASYM_PAUSE | MAC_SYM_PAUSE | - MAC_1000FD | MAC_2500FD | MAC_5000FD | - MAC_10000FD; + MAC_10 | MAC_100 | MAC_1000FD | + MAC_2500FD | MAC_5000FD | MAC_10000FD; mac->link.duplex =3D 0; mac->link.speed10 =3D XGMAC_CONFIG_SS_10_MII; mac->link.speed100 =3D XGMAC_CONFIG_SS_100_MII; diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c b/drivers/n= et/ethernet/stmicro/stmmac/dwxgmac2_dma.c index 7201a38842651a865493fce0cefe757d6ae9bafa..18e92b3c6df4200c51ee56f9231= 58e3ae1cf5ef8 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c @@ -384,6 +384,9 @@ static int dwxgmac2_get_hw_feature(void __iomem *ioaddr, { u32 hw_cap; =20 + struct stmmac_priv *priv =3D container_of(dma_cap, struct stmmac_priv, + dma_cap); + /* MAC HW feature 0 */ hw_cap =3D readl(ioaddr + XGMAC_HW_FEATURE0); dma_cap->edma =3D (hw_cap & XGMAC_HWFEAT_EDMA) >> 31; @@ -406,6 +409,8 @@ static int dwxgmac2_get_hw_feature(void __iomem *ioaddr, dma_cap->vlhash =3D (hw_cap & XGMAC_HWFEAT_VLHASH) >> 4; dma_cap->half_duplex =3D (hw_cap & XGMAC_HWFEAT_HDSEL) >> 3; dma_cap->mbps_1000 =3D (hw_cap & XGMAC_HWFEAT_GMIISEL) >> 1; + if (dma_cap->mbps_1000 && priv->synopsys_id >=3D DWXGMAC_CORE_2_20) + dma_cap->mbps_10_100 =3D 1; =20 /* MAC HW feature 1 */ hw_cap =3D readl(ioaddr + XGMAC_HW_FEATURE1); --=20 2.32.0 From nobody Sat Oct 4 12:41:16 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 29A6A225791; Fri, 15 Aug 2025 16:55:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Fri, 15 Aug 2025 16:55:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755276925; bh=55kubHT3CJFxFuq24D29Jn26nVbHxHRFemaSWvj8LQI=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=juVHBy2NniTI8XXEZLofsypYZ8qJxEgdBugSKMIc7wWAyYCFEwN49xMWEnxCqznoW AiUc2Zep3keHBWeM4QDotUPPIY7eOSC4KH+Pf8LHO9RdnTElf0+cSbT5gykGhZJJoP zk956u9MRbblCaICmlVg+2RUOyq1DaKuP6eClq27Wmcc7wIhXEs9e6XCXFVhienw0W wQMWkhyTKAawXCAi+oFly0QKhS1elAk4509UZb1l0r1VVQIqM/4vUpbt+0XH99bmV/ oa1sd+0U0xailsbEtDGvd3TRitoK2ImXmDbMLAITNhe0b1VFDC6HsxiW+W9bDYVSBI 0rX8ZUkOyKUCA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id E0B52CA0EE6; Fri, 15 Aug 2025 16:55:25 +0000 (UTC) From: Rohan G Thomas via B4 Relay Date: Sat, 16 Aug 2025 00:55:25 +0800 Subject: [PATCH net-next v2 3/3] net: stmmac: Set CIC bit only for TX queues with COE Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250816-xgmac-minor-fixes-v2-3-699552cf8a7f@altera.com> References: <20250816-xgmac-minor-fixes-v2-0-699552cf8a7f@altera.com> In-Reply-To: <20250816-xgmac-minor-fixes-v2-0-699552cf8a7f@altera.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Alexandre Torgue , Serge Semin , Romain Gantois , Jose Abreu , Ong Boon Leong Cc: netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rohan G Thomas , Matthew Gerlach X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1755276924; l=2589; i=rohan.g.thomas@altera.com; s=20250815; h=from:subject:message-id; bh=yd3hqIo3OLgBTjQIzdKCEjVqydvJBVOrIiCiUuaG6/c=; b=+cHw+nFGJfkWJlSFZ0NXzeGjhVaWsNuNMNLqh7oqYs4wwZmPAZeL0M6lamXsjwyeBJ1m02nwF iIh/OnEkKBpBCP1P/iBNCeG/zFdrap4rauGxuqJwia0FXrG8Ix4p64N X-Developer-Key: i=rohan.g.thomas@altera.com; a=ed25519; pk=5yZXkXswhfUILKAQwoIn7m6uSblwgV5oppxqde4g4TY= X-Endpoint-Received: by B4 Relay for rohan.g.thomas@altera.com/20250815 with auth_id=494 X-Original-From: Rohan G Thomas Reply-To: rohan.g.thomas@altera.com From: Rohan G Thomas Currently, in the AF_XDP transmit paths, the CIC bit of TX Desc3 is set for all packets. Setting this bit for packets transmitting through queues that don't support checksum offloading causes the TX DMA to get stuck after transmitting some packets. This patch ensures the CIC bit of TX Desc3 is set only if the TX queue supports checksum offloading. Fixes: 132c32ee5bc0 ("net: stmmac: Add TX via XDP zero-copy socket") Signed-off-by: Rohan G Thomas Reviewed-by: Matthew Gerlach --- drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/ne= t/ethernet/stmicro/stmmac/stmmac_main.c index 9a77390b7f9da4199ad6ac15a2149e2c703900ce..88b7e0aed14428c1884f4c3610c= 4112e9be8fd59 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c @@ -2584,6 +2584,7 @@ static bool stmmac_xdp_xmit_zc(struct stmmac_priv *pr= iv, u32 queue, u32 budget) struct netdev_queue *nq =3D netdev_get_tx_queue(priv->dev, queue); struct stmmac_tx_queue *tx_q =3D &priv->dma_conf.tx_queue[queue]; struct stmmac_txq_stats *txq_stats =3D &priv->xstats.txq_stats[queue]; + bool csum =3D !priv->plat->tx_queues_cfg[queue].coe_unsupported; struct xsk_buff_pool *pool =3D tx_q->xsk_pool; unsigned int entry =3D tx_q->cur_tx; struct dma_desc *tx_desc =3D NULL; @@ -2671,7 +2672,7 @@ static bool stmmac_xdp_xmit_zc(struct stmmac_priv *pr= iv, u32 queue, u32 budget) } =20 stmmac_prepare_tx_desc(priv, tx_desc, 1, xdp_desc.len, - true, priv->mode, true, true, + csum, priv->mode, true, true, xdp_desc.len); =20 stmmac_enable_dma_transmission(priv, priv->ioaddr, queue); @@ -4983,6 +4984,7 @@ static int stmmac_xdp_xmit_xdpf(struct stmmac_priv *p= riv, int queue, { struct stmmac_txq_stats *txq_stats =3D &priv->xstats.txq_stats[queue]; struct stmmac_tx_queue *tx_q =3D &priv->dma_conf.tx_queue[queue]; + bool csum =3D !priv->plat->tx_queues_cfg[queue].coe_unsupported; unsigned int entry =3D tx_q->cur_tx; struct dma_desc *tx_desc; dma_addr_t dma_addr; @@ -5034,7 +5036,7 @@ static int stmmac_xdp_xmit_xdpf(struct stmmac_priv *p= riv, int queue, stmmac_set_desc_addr(priv, tx_desc, dma_addr); =20 stmmac_prepare_tx_desc(priv, tx_desc, 1, xdpf->len, - true, priv->mode, true, true, + csum, priv->mode, true, true, xdpf->len); =20 tx_q->tx_count_frames++; --=20 2.32.0