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[31.53.6.191]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-45a1c6c324fsm59523755e9.1.2025.08.15.07.47.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Aug 2025 07:47:51 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Geert Uytterhoeven , Linus Walleij Cc: Biju Das , Lad Prabhakar , linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Biju Das Subject: [PATCH 1/2] pinctrl: renesas: rzg2l: Fix OEN resume Date: Fri, 15 Aug 2025 15:47:44 +0100 Message-ID: <20250815144749.143832-2-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250815144749.143832-1-biju.das.jz@bp.renesas.com> References: <20250815144749.143832-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das The write to PFC_OEN register is controlled by the write protect register (PWPR). Currently we are setting OEN register in resume() without enabling the write access in PWPR leading to incorrect operation. Fixes: cd39805be85b ("pinctrl: renesas: rzg2l: Unify OEN handling across RZ= /{G2L,V2H,V2N}") Signed-off-by: Biju Das --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/rene= sas/pinctrl-rzg2l.c index b182b3b8a542..2b5d16594bb7 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -3165,6 +3165,8 @@ static int rzg2l_pinctrl_resume_noirq(struct device *= dev) const struct rzg2l_hwcfg *hwcfg =3D pctrl->data->hwcfg; const struct rzg2l_register_offsets *regs =3D &hwcfg->regs; struct rzg2l_pinctrl_reg_cache *cache =3D pctrl->cache; + unsigned long flags; + u8 pwpr; int ret; =20 if (!atomic_read(&pctrl->wakeup_path)) { @@ -3174,7 +3176,15 @@ static int rzg2l_pinctrl_resume_noirq(struct device = *dev) } =20 writeb(cache->qspi, pctrl->base + QSPI); + spin_lock_irqsave(&pctrl->lock, flags); + if (pctrl->data->hwcfg->oen_pwpr_lock) { + pwpr =3D readb(pctrl->base + regs->pwpr); + writeb(pwpr | PWPR_REGWE_B, pctrl->base + regs->pwpr); + } writeb(cache->oen, pctrl->base + pctrl->data->hwcfg->regs.oen); + if (pctrl->data->hwcfg->oen_pwpr_lock) + writeb(pwpr & ~PWPR_REGWE_B, pctrl->base + regs->pwpr); + spin_unlock_irqrestore(&pctrl->lock, flags); for (u8 i =3D 0; i < 2; i++) { if (regs->sd_ch) writeb(cache->sd_ch[i], pctrl->base + SD_CH(regs->sd_ch, i)); --=20 2.43.0