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[31.53.6.191]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-45a1c6c324fsm59523755e9.1.2025.08.15.07.47.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Aug 2025 07:47:51 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Geert Uytterhoeven , Linus Walleij Cc: Biju Das , Lad Prabhakar , linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Biju Das Subject: [PATCH 1/2] pinctrl: renesas: rzg2l: Fix OEN resume Date: Fri, 15 Aug 2025 15:47:44 +0100 Message-ID: <20250815144749.143832-2-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250815144749.143832-1-biju.das.jz@bp.renesas.com> References: <20250815144749.143832-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das The write to PFC_OEN register is controlled by the write protect register (PWPR). Currently we are setting OEN register in resume() without enabling the write access in PWPR leading to incorrect operation. Fixes: cd39805be85b ("pinctrl: renesas: rzg2l: Unify OEN handling across RZ= /{G2L,V2H,V2N}") Signed-off-by: Biju Das --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/rene= sas/pinctrl-rzg2l.c index b182b3b8a542..2b5d16594bb7 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -3165,6 +3165,8 @@ static int rzg2l_pinctrl_resume_noirq(struct device *= dev) const struct rzg2l_hwcfg *hwcfg =3D pctrl->data->hwcfg; const struct rzg2l_register_offsets *regs =3D &hwcfg->regs; struct rzg2l_pinctrl_reg_cache *cache =3D pctrl->cache; + unsigned long flags; + u8 pwpr; int ret; =20 if (!atomic_read(&pctrl->wakeup_path)) { @@ -3174,7 +3176,15 @@ static int rzg2l_pinctrl_resume_noirq(struct device = *dev) } =20 writeb(cache->qspi, pctrl->base + QSPI); + spin_lock_irqsave(&pctrl->lock, flags); + if (pctrl->data->hwcfg->oen_pwpr_lock) { + pwpr =3D readb(pctrl->base + regs->pwpr); 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[31.53.6.191]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-45a1c6c324fsm59523755e9.1.2025.08.15.07.47.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Aug 2025 07:47:51 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Geert Uytterhoeven , Linus Walleij Cc: Biju Das , Lad Prabhakar , linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Biju Das Subject: [PATCH 2/2] pinctrl: renesas: rzg2l: Don't reconfigure the pin if it is same as reset values Date: Fri, 15 Aug 2025 15:47:45 +0100 Message-ID: <20250815144749.143832-3-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250815144749.143832-1-biju.das.jz@bp.renesas.com> References: <20250815144749.143832-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Don't reconfigure the pin if the pin's configuration values are same as reset values during resume() to avoid spurious IRQ. E.g: For NMI function the PS0 pin configuration are PMC =3D 1 and PFC =3D 0 and is same as that of reset values. Currently during resume the pin is already in NMI function. But the code is forcefully setting it to GPIO HI-Z state and then again reconfiguring to NMI function leading to spurious IRQ. Signed-off-by: Biju Das --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 34 +++++++++++++++---------- 1 file changed, 21 insertions(+), 13 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/rene= sas/pinctrl-rzg2l.c index 2b5d16594bb7..086fcb18c6d8 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -3103,27 +3103,35 @@ static void rzg2l_pinctrl_pm_setup_pfc(struct rzg2l= _pinctrl *pctrl) pm =3D readw(pctrl->base + PM(off)); for_each_set_bit(pin, &pinmap, max_pin) { struct rzg2l_pinctrl_reg_cache *cache =3D pctrl->cache; + u32 pfc_mask; + u32 pfc_val; =20 /* Nothing to do if PFC was not configured before. */ if (!(cache->pmc[port] & BIT(pin))) continue; =20 - /* Set pin to 'Non-use (Hi-Z input protection)' */ - pm &=3D ~(PM_MASK << (pin * 2)); - writew(pm, pctrl->base + PM(off)); + pfc_val =3D readl(pctrl->base + PFC(off)); + pfc_mask =3D PFC_MASK << (pin * 4); =20 - /* Temporarily switch to GPIO mode with PMC register */ - pmc &=3D ~BIT(pin); - writeb(pmc, pctrl->base + PMC(off)); + /* Nothing to do if reset value of the pin is same as cached value */ + if ((cache->pfc[port] & pfc_mask) !=3D (pfc_val & pfc_mask)) { + /* Set pin to 'Non-use (Hi-Z input protection)' */ + pm &=3D ~(PM_MASK << (pin * 2)); + writew(pm, pctrl->base + PM(off)); =20 - /* Select Pin function mode. */ - pfc &=3D ~(PFC_MASK << (pin * 4)); - pfc |=3D (cache->pfc[port] & (PFC_MASK << (pin * 4))); - writel(pfc, pctrl->base + PFC(off)); + /* Temporarily switch to GPIO mode with PMC register */ + pmc &=3D ~BIT(pin); + writeb(pmc, pctrl->base + PMC(off)); =20 - /* Switch to Peripheral pin function. */ - pmc |=3D BIT(pin); - writeb(pmc, pctrl->base + PMC(off)); + /* Select Pin function mode. */ + pfc &=3D ~pfc_mask; + pfc |=3D cache->pfc[port] & pfc_mask; + writel(pfc, pctrl->base + PFC(off)); + + /* Switch to Peripheral pin function. */ + pmc |=3D BIT(pin); + writeb(pmc, pctrl->base + PMC(off)); + } } } =20 --=20 2.43.0