From: Xuyang Dong <dongxuyang@eswincomputing.com> This series depends on the vendor prefix patch [1] and config option patch [2]. [1] https://lore.kernel.org/all/20250616112316.3833343-4-pinkesh.vaghela@einfochips.com/ [2] https://lore.kernel.org/all/20250616112316.3833343-3-pinkesh.vaghela@einfochips.com/ Updates: Changes in v4: - Updated YAML file - Changed name from cpu-default-frequency to cpu-default-freq-hz. - Dropped $ref of cpu-default-frequency. - Added cpu-default-frequency for required. - Removed cpu-default-frequency in updated file, because there was no need to add cpu-default-frequency. - Moved DIVIDER to DIV. - Arranged the IDs in order. - Dropped EIC7700_NR_CLKS. - Removed dt-bindings eswin,eic7700-clock.h. Because IDs was not used, and used clock device nodes. - According to the updated driver codes, the YAML has been updated. - Updated driver file - Remove undocumented parameters "cpu_no_boost_1_6ghz" and "cpu-default-frequency". - Modified the comment and used the correct Linux coding style. - Removed codes of voltage, because it was not the clock driver. - Updated the formula of clock frequency calculation. Removed the logic that only used register selection. - Used CLK_OF_DECLARE() to register clocks. Registered pll-clock, mux-clock, divider-clock, and gate-clock in clk-eic7700.c. The specific implementation of clock registration was in clk.c. - Added eic7700-clocks.dtsi. - Moved device information to DTS. Put all clocks' node in the eic7700-clocks.dtsi. - Link to v3: https://lore.kernel.org/all/20250624103212.287-1-dongxuyang@eswincomputing.com/ Changes in v3: - Update example, drop child node and add '#clock-cells' to the parent node. - Change parent node from sys-crg to clock-controller for this yaml. - Drop "syscon", "simple-mfd" to clear warnings/errors by using "make dt_binding_check". And these are not necessary. - Add "cpu-default-frequency" definition in yaml for "undocumented ABI". - Drop Reviewed-by, this is misunderstanding. We have not received such an email. - Link to v2: https://lore.kernel.org/all/20250523090747.1830-1-dongxuyang@eswincomputing.com/ Changes in v2: - Update example, drop child node. - Clear warnings/errors for using "make dt_binding_check". - Change to the correct format. - Drop some non-stanard code. - Use dev_err_probe() in probe functions. - Link to v1: https://lore.kernel.org/all/20250514002233.187-1-dongxuyang@eswincomputing.com/ Xuyang Dong (3): clock: eswin: Documentation for eic7700 SoC clock: eswin: Add eic7700 clock driver riscv: dts: eswin: Add clock driver support .../bindings/clock/eswin,eic7700-clock.yaml | 381 +++ arch/riscv/boot/dts/eswin/eic7700-clocks.dtsi | 2283 +++++++++++++++++ drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/eswin/Kconfig | 10 + drivers/clk/eswin/Makefile | 8 + drivers/clk/eswin/clk-eic7700.c | 44 + drivers/clk/eswin/clk.c | 734 ++++++ drivers/clk/eswin/clk.h | 69 + 9 files changed, 3531 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/eswin,eic7700-clock.yaml create mode 100644 arch/riscv/boot/dts/eswin/eic7700-clocks.dtsi create mode 100644 drivers/clk/eswin/Kconfig create mode 100644 drivers/clk/eswin/Makefile create mode 100644 drivers/clk/eswin/clk-eic7700.c create mode 100644 drivers/clk/eswin/clk.c create mode 100644 drivers/clk/eswin/clk.h -- 2.17.1 From: Xuyang Dong <dongxuyang@eswincomputing.com> Add device tree binding documentation for the ESWIN eic7700 clock controller module. Signed-off-by: Yifeng Huang <huangyifeng@eswincomputing.com> Signed-off-by: Xuyang Dong <dongxuyang@eswincomputing.com> --- .../bindings/clock/eswin,eic7700-clock.yaml | 381 ++++++++++++++++++ 1 file changed, 381 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/eswin,eic7700-clock.yaml diff --git a/Documentation/devicetree/bindings/clock/eswin,eic7700-clock.yaml b/Documentation/devicetree/bindings/clock/eswin,eic7700-clock.yaml new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/Documentation/devicetree/bindings/clock/eswin,eic7700-clock.yaml @@ -XXX,XX +XXX,XX @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/eswin,eic7700-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Eswin EIC7700 SoC clock controller + +maintainers: + - Yifeng Huang <huangyifeng@eswincomputing.com> + - Xuyang Dong <dongxuyang@eswincomputing.com> + +description: + The clock controller generates and supplies clock to all the modules + for eic7700 SoC. + +properties: + compatible: + const: eswin,eic7700-clock + + reg: + maxItems: 1 + + '#clock-cells': + const: 0 + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + +required: + - compatible + - reg + - '#clock-cells' + - '#address-cells' + - '#size-cells' + +patternProperties: + "^fixed-rate.*": + type: object + $ref: /schemas/clock/fixed-clock.yaml# + + ".*pll@[a-f0-9]+$": + type: object + + properties: + compatible: + const: eswin,pll-clock + + reg: + items: + - description: PLL's config 0 register + - description: PLL's config 1 register + - description: PLL's config 2 register + - description: PLL's status register + + '#clock-cells': + const: 0 + + clock-output-names: + maxItems: 1 + + enable-shift: + description: Bit shift of the enable register. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 31 + + enable-width: + description: Width of the enable register. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 31 + + refdiv-shift: + description: Bit shift of the reference divider register. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 31 + + refdiv-width: + description: Width of the reference divider register. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 31 + + fbdiv-shift: + description: Bit shift of the feedback divider register. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 31 + + fbdiv-width: + description: Width of the feedback divider register. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 31 + + frac-shift: + description: Bit shift of the fractional divider register. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 31 + + frac-width: + description: Width of the fractional divider register. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 31 + + postdiv1-shift: + description: Bit shift of the post divider 1 register. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 31 + + postdiv1-width: + description: Width of the post divider 1 register. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 31 + + postdiv2-shift: + description: Bit shift of the post divider 2 register. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 31 + + postdiv2-width: + description: Width of the post divider 2 register. + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 31 + + lock-shift: + description: Bit shift of the lock register. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 31 + + lock-width: + description: Width of the lock register. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 31 + + required: + - compatible + - reg + - '#clock-cells' + - clock-output-names + - enable-shift + - enable-width + - refdiv-shift + - refdiv-width + - fbdiv-shift + - fbdiv-width + - frac-shift + - frac-width + - postdiv1-shift + - postdiv1-width + - postdiv2-shift + - postdiv2-width + - lock-shift + - lock-width + + additionalProperties: false + + ".*mux@[a-f0-9]+$": + type: object + + properties: + compatible: + const: eswin,mux-clock + + reg: + maxItems: 1 + + clocks: + minItems: 2 + maxItems: 3 + + '#clock-cells': + const: 0 + + clock-output-names: + maxItems: 1 + + shift: + description: Bit shift of the select register. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 31 + + width: + description: Width of the select register. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 31 + + + required: + - compatible + - reg + - clocks + - '#clock-cells' + - clock-output-names + - shift + - width + + additionalProperties: false + + "^fixed-factor.*": + type: object + $ref: /schemas/clock/fixed-factor-clock.yaml# + + ".*div@[a-f0-9]+$": + type: object + + properties: + compatible: + const: eswin,divider-clock + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + '#clock-cells': + const: 0 + + clock-output-names: + maxItems: 1 + + shift: + description: Bit shift of the divider register. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 31 + + width: + description: Width of the divider register. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 31 + + div-flags: + description: Flags of the divider register. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 31 + + required: + - compatible + - reg + - clocks + - '#clock-cells' + - clock-output-names + - shift + - width + - div-flags + + additionalProperties: false + + ".*gate@[a-f0-9]+$": + type: object + + properties: + compatible: + const: eswin,gate-clock + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + '#clock-cells': + const: 0 + + clock-output-names: + maxItems: 1 + + bit-index: + description: Bit shift of the gate enable register. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 31 + + required: + - compatible + - reg + - clocks + - '#clock-cells' + - clock-output-names + - bit-index + + additionalProperties: false + +additionalProperties: false + +examples: + - | + clock-controller@51828000 { + compatible = "eswin,eic7700-clock"; + reg = <0x51828000 0x80000>; + #clock-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + fixed_rate_clk_xtal_24m: fixed-rate-clk-xtal-24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "fixed_rate_clk_xtal_24m"; + }; + + clk_pll_cpu: clk-cpu-pll@64 { + compatible = "eswin,pll-clock"; + reg = <0x64>, <0x68>, <0x6c>, <0xa4>; + #clock-cells = <0>; + enable-shift = <0>; + enable-width = <1>; + refdiv-shift = <12>; + refdiv-width = <6>; + fbdiv-shift = <20>; + fbdiv-width = <12>; + frac-shift = <4>; + frac-width = <24>; + postdiv1-shift = <1>; + postdiv1-width = <3>; + postdiv2-shift = <16>; + postdiv2-width = <3>; + lock-shift = <5>; + lock-width = <1>; + clock-output-names = "clk_pll_cpu"; + }; + + mux_cpu_root_3mux1: cpu-root-3mux1-mux@208 { + compatible = "eswin,mux-clock"; + reg = <0x208>; + #clock-cells = <0>; + clocks = <&clk_pll_cpu>, + <&fixed_factor_u84_core_lp_div2>, + <&fixed_rate_clk_xtal_24m>; + shift = <0>; + width = <2>; + clock-output-names = "mux_cpu_root_3mux1"; + }; + + fixed_factor_cpu_div2: fixed-factor-cpu-div2 { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&mux_cpu_root_3mux1>; + clock-div = <2>; + clock-mult = <1>; + clock-output-names = "fixed_factor_cpu_div2"; + }; + + divider_u84_rtc_toggle: u84-rtc-toggle-div@1ec { + compatible = "eswin,divider-clock"; + reg = <0x1ec>; + #clock-cells = <0>; + clocks = <&fixed_rate_clk_xtal_24m>; + shift = <16>; + width = <5>; + div-flags = <0x5>; + clock-output-names = "divider_u84_rtc_toggle"; + }; + + gate_vi_phy_cfg: vi-phy-cfg-gate@1ac { + compatible = "eswin,gate-clock"; + reg = <0x1ac>; + #clock-cells = <0>; + clocks = <&fixed_rate_clk_xtal_24m>; + bit-index = <1>; + clock-output-names = "gate_vi_phy_cfg"; + }; + }; -- 2.17.1 From: Xuyang Dong <dongxuyang@eswincomputing.com> This driver depends on the CCF framework implementation. Based on this driver, other modules in the SoC can use the APIs provided by CCF to perform clock-related operations. The driver supports eic7700 series chips. Signed-off-by: Yifeng Huang <huangyifeng@eswincomputing.com> Signed-off-by: Xuyang Dong <dongxuyang@eswincomputing.com> --- drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/eswin/Kconfig | 10 + drivers/clk/eswin/Makefile | 8 + drivers/clk/eswin/clk-eic7700.c | 44 ++ drivers/clk/eswin/clk.c | 734 ++++++++++++++++++++++++++++++++ drivers/clk/eswin/clk.h | 69 +++ 7 files changed, 867 insertions(+) create mode 100644 drivers/clk/eswin/Kconfig create mode 100644 drivers/clk/eswin/Makefile create mode 100644 drivers/clk/eswin/clk-eic7700.c create mode 100644 drivers/clk/eswin/clk.c create mode 100644 drivers/clk/eswin/clk.h diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index XXXXXXX..XXXXXXX 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -XXX,XX +XXX,XX @@ source "drivers/clk/actions/Kconfig" source "drivers/clk/analogbits/Kconfig" source "drivers/clk/baikal-t1/Kconfig" source "drivers/clk/bcm/Kconfig" +source "drivers/clk/eswin/Kconfig" source "drivers/clk/hisilicon/Kconfig" source "drivers/clk/imgtec/Kconfig" source "drivers/clk/imx/Kconfig" diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index XXXXXXX..XXXXXXX 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_CLK_BAIKAL_T1) += baikal-t1/ obj-y += bcm/ obj-$(CONFIG_ARCH_BERLIN) += berlin/ obj-$(CONFIG_ARCH_DAVINCI) += davinci/ +obj-$(CONFIG_ARCH_ESWIN) += eswin/ obj-$(CONFIG_ARCH_HISI) += hisilicon/ obj-y += imgtec/ obj-y += imx/ diff --git a/drivers/clk/eswin/Kconfig b/drivers/clk/eswin/Kconfig new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/drivers/clk/eswin/Kconfig @@ -XXX,XX +XXX,XX @@ +# SPDX-License-Identifier: GPL-2.0 + +config COMMON_CLK_EIC7700 + bool "EIC7700 Clock Driver" + depends on ARCH_ESWIN + help + Build the Eswin EIC7700 SoC clock driver based on the + common clock framework. This driver provides support + for the clock control on the Eswin EIC7700 SoC, + which is essential for managing clock rates and power management. diff --git a/drivers/clk/eswin/Makefile b/drivers/clk/eswin/Makefile new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/drivers/clk/eswin/Makefile @@ -XXX,XX +XXX,XX @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Eswin Clock specific Makefile +# + +obj-y += clk.o + +obj-$(CONFIG_COMMON_CLK_EIC7700) += clk-eic7700.o diff --git a/drivers/clk/eswin/clk-eic7700.c b/drivers/clk/eswin/clk-eic7700.c new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/drivers/clk/eswin/clk-eic7700.c @@ -XXX,XX +XXX,XX @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2025, Beijing ESWIN Computing Technology Co., Ltd.. + * All rights reserved. + * + * ESWIN EIC7700 CLK Provider Driver + * + * Authors: + * Yifeng Huang <huangyifeng@eswincomputing.com> + * Xuyang Dong <dongxuyang@eswincomputing.com> + */ + +#include <linux/clk.h> +#include <linux/clk-provider.h> +#include <linux/kernel.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/of_address.h> +#include "clk.h" + +static void __init eic7700_clk_pll_init(struct device_node *np) +{ + eswin_clk_pll_register(np); +} + +static void __init eic7700_clk_mux_init(struct device_node *np) +{ + eswin_clk_mux_register(np); +} + +static void __init eic7700_clk_div_init(struct device_node *np) +{ + eswin_clk_div_register(np); +} + +static void __init eic7700_clk_gate_init(struct device_node *np) +{ + eswin_clk_gate_register(np); +} + +CLK_OF_DECLARE(eic7700_clk_pll, "eswin,pll-clock", eic7700_clk_pll_init); +CLK_OF_DECLARE(eic7700_clk_mux, "eswin,mux-clock", eic7700_clk_mux_init); +CLK_OF_DECLARE(eic7700_clk_div, "eswin,divider-clock", eic7700_clk_div_init); +CLK_OF_DECLARE(eic7700_clk_gate, "eswin,gate-clock", eic7700_clk_gate_init); diff --git a/drivers/clk/eswin/clk.c b/drivers/clk/eswin/clk.c new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/drivers/clk/eswin/clk.c @@ -XXX,XX +XXX,XX @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2025, Beijing ESWIN Computing Technology Co., Ltd.. + * All rights reserved. + * + * Authors: + * Yifeng Huang <huangyifeng@eswincomputing.com> + * Xuyang Dong <dongxuyang@eswincomputing.com> + */ + +#include <linux/clk.h> +#include <linux/clkdev.h> +#include <linux/clk-provider.h> +#include <linux/delay.h> +#include <linux/io.h> +#include <linux/math.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/of_device.h> +#include <linux/of_platform.h> +#include <linux/slab.h> +#include <linux/util_macros.h> +#include "clk.h" + +enum pll_clk { + CLK_APLL_FOUT1 = 1, + CLK_PLL_CPU +}; + +static enum pll_clk str_to_pll_clk(const char *str) +{ + if (!strcmp(str, "clk_apll_fout1")) + return CLK_APLL_FOUT1; + else if (!strcmp(str, "clk_pll_cpu")) + return CLK_PLL_CPU; + else + return 0; +} + +static void __iomem *parent_base; + +static void __init get_parent_base(struct device_node *parent_np) +{ + if (!parent_base) { + parent_base = of_iomap(parent_np, 0); + if (IS_ERR(parent_base)) { + pr_err("%s: Failed to map registers\n", __func__); + parent_base = NULL; + } + } +} + +/** + * eswin_calc_pll - calculate PLL values + * @frac_val: fractional divider + * @fbdiv_val: feedback divider + * @rate: reference rate + * + * Calculate PLL values for frac and fbdiv + */ +static void eswin_calc_pll(u32 *frac_val, u32 *fbdiv_val, u64 rate) +{ + u32 rem, tmp1, tmp2; + + rate = rate * 4; + rem = do_div(rate, 1000); + if (rem) + tmp1 = rem; + + rem = do_div(rate, 1000); + if (rem) + tmp2 = rem; + + rem = do_div(rate, 24); + /* fbdiv = rate * 4 / 24000000 */ + *fbdiv_val = rate; + /* frac = rate * 4 % 24000000 * (2 ^ 24) */ + *frac_val = ((1000 * (1000 * rem + tmp2) + tmp1) << 21) / 3 / 1000000; +} + +static inline struct eswin_clk_pll *to_pll_clk(struct clk_hw *hw) +{ + return container_of(hw, struct eswin_clk_pll, hw); +} + +static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct eswin_clk_pll *clk = to_pll_clk(hw); + const char *clk_name = clk_hw_get_name(&clk->hw); + + if (!clk_name) + return -ENOMEM; + + u32 frac_val = 0, fbdiv_val, refdiv_val = 1, postdiv1_val = 0; + u32 val; + int ret; + struct clk *clk_cpu_mux = NULL; + struct clk *clk_cpu_lp_pll = NULL; + struct clk *clk_cpu_pll = NULL; + int try_count = 0; + bool lock_flag = false; + + eswin_calc_pll(&frac_val, &fbdiv_val, (u64)rate); + + /* Must switch the CPU to other CLK before we change the CPU PLL. */ + if (str_to_pll_clk(clk_name) == CLK_PLL_CPU) { + clk_cpu_mux = __clk_lookup("mux_cpu_root_3mux1"); + if (!clk_cpu_mux) { + pr_err("%s %d, failed to get %s\n", __func__, __LINE__, + "mux_cpu_root_3mux1"); + return -EINVAL; + } + clk_cpu_lp_pll = __clk_lookup("fixed_factor_u84_core_lp_div2"); + if (!clk_cpu_lp_pll) { + pr_err("%s %d, failed to get %s\n", __func__, __LINE__, + "fixed_factor_u84_core_lp_div2"); + return -EINVAL; + } + ret = clk_prepare_enable(clk_cpu_lp_pll); + if (ret) { + pr_err("%s %d, failed to enable %s, ret %d\n", + __func__, __LINE__, + "fixed_factor_u84_core_lp_div2", ret); + return ret; + } + clk_cpu_pll = __clk_lookup("clk_pll_cpu"); + if (!clk_cpu_pll) { + pr_err("%s %d, failed to get %s\n", __func__, __LINE__, + "clk_pll_cpu"); + clk_disable_unprepare(clk_cpu_lp_pll); + return -EINVAL; + } + + ret = clk_set_parent(clk_cpu_mux, clk_cpu_lp_pll); + if (ret) { + pr_err("%s %d, failed to switch %s to %s, ret %d\n", + __func__, __LINE__, "mux_cpu_root_3mux1", + "fixed_factor_u84_core_lp_div2", ret); + clk_disable_unprepare(clk_cpu_lp_pll); + return -EPERM; + } + } + + /* first disable PLL */ + val = readl_relaxed(clk->ctrl_reg0); + val &= ~(((1 << clk->pllen_width) - 1) << clk->pllen_shift); + val |= 0 << clk->pllen_shift; + writel_relaxed(val, clk->ctrl_reg0); + + val = readl_relaxed(clk->ctrl_reg0); + val &= ~(((1 << clk->fbdiv_width) - 1) << clk->fbdiv_shift); + val &= ~(((1 << clk->refdiv_width) - 1) << clk->refdiv_shift); + val |= refdiv_val << clk->refdiv_shift; + val |= fbdiv_val << clk->fbdiv_shift; + writel_relaxed(val, clk->ctrl_reg0); + + val = readl_relaxed(clk->ctrl_reg1); + val &= ~(((1 << clk->frac_width) - 1) << clk->frac_shift); + val |= frac_val << clk->frac_shift; + writel_relaxed(val, clk->ctrl_reg1); + + val = readl_relaxed(clk->ctrl_reg2); + val &= ~(((1 << clk->postdiv1_width) - 1) << clk->postdiv1_shift); + val |= postdiv1_val << clk->postdiv1_shift; + writel_relaxed(val, clk->ctrl_reg2); + + /* at last, enable PLL */ + val = readl_relaxed(clk->ctrl_reg0); + val &= ~(((1 << clk->pllen_width) - 1) << clk->pllen_shift); + val |= 1 << clk->pllen_shift; + writel_relaxed(val, clk->ctrl_reg0); + + /* usually the PLL would lock in 50us */ + do { + usleep_range(refdiv_val * 80, refdiv_val * 80 * 2); + val = readl_relaxed(clk->status_reg); + if (val & 1 << clk->lock_shift) { + lock_flag = true; + break; + } + } while (try_count++ < 10); + + if (!lock_flag) { + pr_err("%s %d, failed to lock the cpu pll", __func__, __LINE__); + return -EBUSY; + } + + if (str_to_pll_clk(clk_name) == CLK_PLL_CPU) { + ret = clk_set_parent(clk_cpu_mux, clk_cpu_pll); + if (ret) { + pr_err("%s %d, failed to switch %s to %s, ret %d\n", + __func__, __LINE__, "mux_cpu_root_3mux1", + "clk_pll_cpu", ret); + return -EPERM; + } + clk_disable_unprepare(clk_cpu_lp_pll); + } + return ret; +} + +static unsigned long clk_pll_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct eswin_clk_pll *clk = to_pll_clk(hw); + const char *clk_name = clk_hw_get_name(&clk->hw); + + if (!clk_name) + return -ENOMEM; + + u64 frac_val, fbdiv_val, refdiv_val, tmp, rem; + u32 postdiv1_val; + u32 val; + u64 rate = 0; + + val = readl_relaxed(clk->ctrl_reg0); + val = val >> clk->fbdiv_shift; + val &= ((1 << clk->fbdiv_width) - 1); + fbdiv_val = val; + + val = readl_relaxed(clk->ctrl_reg0); + val = val >> clk->refdiv_shift; + val &= ((1 << clk->refdiv_width) - 1); + refdiv_val = val; + + val = readl_relaxed(clk->ctrl_reg1); + val = val >> clk->frac_shift; + val &= ((1 << clk->frac_width) - 1); + frac_val = val; + + val = readl_relaxed(clk->ctrl_reg2); + val = val >> clk->postdiv1_shift; + val &= ((1 << clk->postdiv1_width) - 1); + postdiv1_val = val; + + /* rate = 24000000 * (fbdiv + frac / (2 ^ 24)) / 4 */ + if (str_to_pll_clk(clk_name)) { + tmp = 1000 * frac_val; + rem = do_div(tmp, BIT(24)); + if (rem) + rate = (u64)(6000 * (1000 * fbdiv_val + tmp) + + ((6000 * rem) >> 24) + 1); + else + rate = (u64)(6000 * 1000 * fbdiv_val); + } + + return rate; +} + +static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *parent_rate) +{ + struct eswin_clk_pll *clk = to_pll_clk(hw); + const char *clk_name = clk_hw_get_name(&clk->hw); + + if (!clk_name) + return -ENOMEM; + + int index; + u64 round_rate = 0; + + /* Must be sorted in ascending order */ + u64 apll_clk[] = { APLL_LOW_FREQ, APLL_HIGH_FREQ }; + u64 cpu_pll_clk[] = { CLK_FREQ_100M, CLK_FREQ_200M, CLK_FREQ_400M, + CLK_FREQ_500M, CLK_FREQ_600M, CLK_FREQ_700M, + CLK_FREQ_800M, CLK_FREQ_900M, CLK_FREQ_1000M, + CLK_FREQ_1200M, CLK_FREQ_1300M, CLK_FREQ_1400M, + CLK_FREQ_1500M, CLK_FREQ_1600M, CLK_FREQ_1700M, + CLK_FREQ_1800M }; + + switch (str_to_pll_clk(clk_name)) { + case CLK_APLL_FOUT1: + index = find_closest(rate, apll_clk, ARRAY_SIZE(apll_clk)); + round_rate = apll_clk[index]; + break; + case CLK_PLL_CPU: + index = find_closest(rate, cpu_pll_clk, + ARRAY_SIZE(cpu_pll_clk)); + round_rate = cpu_pll_clk[index]; + break; + default: + pr_err("%s %d, unknown clk %s\n", __func__, __LINE__, + clk_name); + break; + } + return round_rate; +} + +static const struct clk_ops eswin_clk_pll_ops = { + .set_rate = clk_pll_set_rate, + .recalc_rate = clk_pll_recalc_rate, + .round_rate = clk_pll_round_rate, +}; + +void __init eswin_clk_gate_register(struct device_node *np) +{ + struct clk_hw *clk_hw; + struct device_node *parent_np; + const char *clk_name; + const char *parent_name; + u32 idx_bit; + u32 reg; + int ret; + + parent_np = of_get_parent(np); + if (!parent_np) { + pr_err("%s: Failed to get parent node\n", __func__); + return; + } + + if (of_device_is_compatible(parent_np, "eswin,eic7700-clock")) + get_parent_base(parent_np); + else + return; + + if (IS_ERR(parent_base)) { + pr_err("%s: Failed to map registers\n", __func__); + goto put_node; + } + + ret = of_property_read_string(np, "clock-output-names", &clk_name); + if (ret) { + pr_err("%s: Missing clock-output-names\n", __func__); + goto put_node; + } + + parent_name = of_clk_get_parent_name(np, 0); + if (!parent_name) + goto put_node; + + ret = of_property_read_u32(np, "bit-index", &idx_bit); + if (ret) { + pr_err("%s: Missing bit-index for gate %s\n", __func__, + clk_name); + goto put_node; + } + + ret = of_property_read_u32(np, "reg", &reg); + if (ret) { + pr_err("%s: Missing reg for gate %s\n", __func__, clk_name); + goto put_node; + } + + clk_hw = clk_hw_register_gate(NULL, clk_name, parent_name, + CLK_SET_RATE_PARENT, + parent_base + reg, idx_bit, 0, NULL); + + if (IS_ERR(clk_hw)) { + pr_err("%s: Failed to register gate clock %s: %ld\n", + __func__, clk_name, PTR_ERR(clk_hw)); + goto put_node; + } + ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, clk_hw); + if (ret) { + pr_err("%s: Failed to add clock provider: %d\n", __func__, ret); + clk_hw_unregister_gate(clk_hw); + } + +put_node: + of_node_put(parent_np); +} + +void __init eswin_clk_mux_register(struct device_node *np) +{ + struct clk *clk; + const char *clk_name = NULL; + const char **parent_names = NULL; + struct device_node *parent_np; + u32 shift, width; + u32 reg; + u8 num_parents; + u32 mask = 0; + int ret, i; + + parent_np = of_get_parent(np); + if (!parent_np) { + pr_err("%s: Failed to get parent node\n", __func__); + return; + } + + if (of_device_is_compatible(parent_np, "eswin,eic7700-clock")) + get_parent_base(parent_np); + else + return; + + if (IS_ERR(parent_base)) { + pr_err("%s: Failed to map registers\n", __func__); + goto put_node; + } + + ret = of_property_read_string(np, "clock-output-names", &clk_name); + if (ret) { + pr_err("%s: Missing clock-output-names\n", __func__); + goto put_node; + } + + num_parents = of_clk_get_parent_count(np); + if (!num_parents) { + pr_err("%s: No parents for mux %s\n", __func__, clk_name); + goto put_node; + } + + parent_names = kcalloc(num_parents, sizeof(*parent_names), + GFP_KERNEL); + if (!parent_names) + goto put_node; + + for (i = 0; i < num_parents; i++) { + parent_names[i] = of_clk_get_parent_name(np, i); + if (!parent_names[i]) { + pr_err("%s: Failed to get parent name %d for %s\n", + __func__, i, clk_name); + goto free_parents; + } + } + + ret = of_property_read_u32(np, "shift", &shift); + if (ret) { + pr_err("%s: Missing shift for mux %s\n", __func__, clk_name); + goto free_parents; + } + + ret = of_property_read_u32(np, "width", &width); + if (ret) { + pr_err("%s: Missing width for mux %s\n", __func__, clk_name); + goto free_parents; + } + + ret = of_property_read_u32(np, "reg", &reg); + if (ret) { + pr_err("%s: Missing reg for mux %s\n", __func__, clk_name); + goto free_parents; + } + + mask = BIT(width) - 1; + clk = clk_register_mux_table(NULL, clk_name, parent_names, num_parents, + CLK_SET_RATE_PARENT, parent_base + reg, + shift, mask, 0, NULL, NULL); + + if (IS_ERR(clk)) { + pr_err("%s: Failed to register mux clock %s: %ld\n", __func__, + clk_name, PTR_ERR(clk)); + goto free_parents; + } + + ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, clk); + if (ret) { + pr_err("%s: Failed to add clock provider: %d\n", __func__, ret); + clk_unregister_mux(clk); + } + +free_parents: + kfree(parent_names); +put_node: + of_node_put(parent_np); +} + +void __init eswin_clk_div_register(struct device_node *np) +{ + struct clk_hw *clk_hw; + struct device_node *parent_np; + const char *clk_name; + const char *parent_name; + u32 shift, width, div_flags; + u32 reg; + int ret; + + parent_np = of_get_parent(np); + if (!parent_np) { + pr_err("%s: Failed to get parent node\n", __func__); + return; + } + + if (of_device_is_compatible(parent_np, "eswin,eic7700-clock")) + get_parent_base(parent_np); + else + return; + + if (IS_ERR(parent_base)) { + pr_err("%s: Failed to map registers\n", __func__); + goto put_node; + } + + ret = of_property_read_string(np, "clock-output-names", &clk_name); + if (ret) { + pr_err("%s: Missing clock-output-names\n", __func__); + goto put_node; + } + + parent_name = of_clk_get_parent_name(np, 0); + if (!parent_name) { + pr_err("%s: No parent for div %s\n", __func__, clk_name); + goto put_node; + } + + ret = of_property_read_u32(np, "shift", &shift); + if (ret) { + pr_err("%s: Missing shift for div %s\n", __func__, clk_name); + goto put_node; + } + + ret = of_property_read_u32(np, "width", &width); + if (ret) { + pr_err("%s: Missing width for div %s\n", __func__, clk_name); + goto put_node; + } + + ret = of_property_read_u32(np, "div-flags", &div_flags); + if (ret) { + pr_err("%s: Missing div-flags for div %s\n", __func__, + clk_name); + goto put_node; + } + + ret = of_property_read_u32(np, "reg", &reg); + if (ret) { + pr_err("%s: Missing reg for div %s\n", __func__, clk_name); + goto put_node; + } + + clk_hw = clk_hw_register_divider(NULL, clk_name, parent_name, 0, + parent_base + reg, shift, width, + div_flags, NULL); + + if (IS_ERR(clk_hw)) { + pr_err("%s: Failed to register divider clock %s: %ld\n", + __func__, clk_name, PTR_ERR(clk_hw)); + goto put_node; + } + + ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, clk_hw); + if (ret) { + pr_err("%s: Failed to add clock provider: %d\n", __func__, ret); + clk_hw_unregister_divider(clk_hw); + } + +put_node: + of_node_put(parent_np); +} + +void __init eswin_clk_pll_register(struct device_node *np) +{ + struct eswin_clk_pll *p_clk = NULL; + struct clk *clk = NULL; + struct clk_init_data init = {}; + struct device_node *parent_np; + const char *clk_name; + const char *parent_name; + int ret; + u32 reg[4]; + u32 en_shift, en_width; + u32 refdiv_shift, refdiv_width; + u32 fbdiv_shift, fbdiv_width; + u32 frac_shift, frac_width; + u32 postdiv1_shift, postdiv1_width; + u32 postdiv2_shift, postdiv2_width; + u32 lock_shift, lock_width; + + parent_np = of_get_parent(np); + if (!parent_np) { + pr_err("%s: Failed to get parent node\n", __func__); + return; + } + + if (of_device_is_compatible(parent_np, "eswin,eic7700-clock")) + get_parent_base(parent_np); + else + return; + + if (IS_ERR(parent_base)) { + pr_err("%s: Failed to map registers\n", __func__); + goto put_node; + } + + ret = of_property_read_string(np, "clock-output-names", &clk_name); + if (ret) { + pr_err("%s: Missing clock-output-names\n", __func__); + goto put_node; + } + + ret = of_property_read_u32(np, "enable-shift", &en_shift); + if (ret) { + pr_err("%s: Missing enable-shift for pll %s\n", __func__, + clk_name); + goto put_node; + } + + ret = of_property_read_u32(np, "enable-width", &en_width); + if (ret) { + pr_err("%s: Missing enable-width for pll %s\n", __func__, + clk_name); + goto put_node; + } + + ret = of_property_read_u32(np, "refdiv-shift", &refdiv_shift); + if (ret) { + pr_err("%s: Missing refdiv-shift for pll %s\n", __func__, + clk_name); + goto put_node; + } + + ret = of_property_read_u32(np, "refdiv-width", &refdiv_width); + if (ret) { + pr_err("%s: Missing refdiv-width for pll %s\n", __func__, + clk_name); + goto put_node; + } + + ret = of_property_read_u32(np, "fbdiv-shift", &fbdiv_shift); + if (ret) { + pr_err("%s: Missing fbdiv-shift for pll %s\n", __func__, + clk_name); + goto put_node; + } + + ret = of_property_read_u32(np, "fbdiv-width", &fbdiv_width); + if (ret) { + pr_err("%s: Missing fbdiv-width for pll %s\n", __func__, + clk_name); + goto put_node; + } + + ret = of_property_read_u32(np, "frac-shift", &frac_shift); + if (ret) { + pr_err("%s: Missing frac-shift for pll %s\n", __func__, + clk_name); + goto put_node; + } + + ret = of_property_read_u32(np, "frac-width", &frac_width); + if (ret) { + pr_err("%s: Missing frac-width for pll %s\n", __func__, + clk_name); + goto put_node; + } + + ret = of_property_read_u32(np, "postdiv1-shift", &postdiv1_shift); + if (ret) { + pr_err("%s: Missing postdiv1-shift for pll %s\n", __func__, + clk_name); + goto put_node; + } + + ret = of_property_read_u32(np, "postdiv1-width", &postdiv1_width); + if (ret) { + pr_err("%s: Missing postdiv1-width for pll %s\n", __func__, + clk_name); + goto put_node; + } + + ret = of_property_read_u32(np, "postdiv2-shift", &postdiv2_shift); + if (ret) { + pr_err("%s: Missing postdiv2-shift for pll %s\n", __func__, + clk_name); + goto put_node; + } + + ret = of_property_read_u32(np, "postdiv2-width", &postdiv2_width); + if (ret) { + pr_err("%s: Missing postdiv2-width for pll %s\n", __func__, + clk_name); + goto put_node; + } + + ret = of_property_read_u32(np, "lock-shift", &lock_shift); + if (ret) { + pr_err("%s: Missing lock-shift for pll %s\n", __func__, + clk_name); + goto put_node; + } + + ret = of_property_read_u32(np, "lock-width", &lock_width); + if (ret) { + pr_err("%s: Missing lock-width for pll %s\n", __func__, + clk_name); + goto put_node; + } + + ret = of_property_read_u32_array(np, "reg", reg, 4); + if (ret) { + pr_err("%s: Missing reg for pll %s\n", __func__, clk_name); + goto put_node; + } + + p_clk = kzalloc(sizeof(*p_clk), GFP_KERNEL); + if (!p_clk) + goto put_node; + + p_clk->ctrl_reg0 = parent_base + reg[0]; + p_clk->pllen_shift = en_shift; + p_clk->pllen_width = en_width; + p_clk->refdiv_shift = refdiv_shift; + p_clk->refdiv_width = refdiv_width; + p_clk->fbdiv_shift = fbdiv_shift; + p_clk->fbdiv_width = fbdiv_width; + + p_clk->ctrl_reg1 = parent_base + reg[1]; + p_clk->frac_shift = frac_shift; + p_clk->frac_width = frac_width; + + p_clk->ctrl_reg2 = parent_base + reg[2]; + p_clk->postdiv1_shift = postdiv1_shift; + p_clk->postdiv1_width = postdiv1_width; + p_clk->postdiv2_shift = postdiv2_shift; + p_clk->postdiv2_width = postdiv2_width; + + p_clk->status_reg = parent_base + reg[3]; + p_clk->lock_shift = lock_shift; + p_clk->lock_width = lock_width; + + init.name = clk_name; + init.flags = 0; + init.parent_names = parent_name ? &parent_name : NULL; + init.num_parents = parent_name ? 1 : 0; + init.ops = &eswin_clk_pll_ops; + p_clk->hw.init = &init; + + clk = clk_register(NULL, &p_clk->hw); + if (IS_ERR(clk)) { + pr_err("%s: Failed to register pll clock %s: %ld\n", __func__, + clk_name, PTR_ERR(clk)); + kfree(p_clk); + goto put_node; + } + + ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, clk); + if (ret) { + pr_err("%s: Failed to add clock provider: %d\n", __func__, ret); + clk_unregister(clk); + } + +put_node: + of_node_put(parent_np); +} diff --git a/drivers/clk/eswin/clk.h b/drivers/clk/eswin/clk.h new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/drivers/clk/eswin/clk.h @@ -XXX,XX +XXX,XX @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2025, Beijing ESWIN Computing Technology Co., Ltd.. + * All rights reserved. + * + * Authors: + * Yifeng Huang <huangyifeng@eswincomputing.com> + * Xuyang Dong <dongxuyang@eswincomputing.com> + */ + +#ifndef __ESWIN_CLK_H__ +#define __ESWIN_CLK_H__ + +#include <linux/clk-provider.h> +#include <linux/io.h> +#include <linux/platform_device.h> + +#define CLK_FREQ_1800M 1800000000 +#define CLK_FREQ_1700M 1700000000 +#define CLK_FREQ_1600M 1600000000 +#define CLK_FREQ_1500M 1500000000 +#define CLK_FREQ_1400M 1400000000 +#define CLK_FREQ_1300M 1300000000 +#define CLK_FREQ_1200M 1200000000 +#define CLK_FREQ_1000M 1000000000 +#define CLK_FREQ_900M 900000000 +#define CLK_FREQ_800M 800000000 +#define CLK_FREQ_700M 700000000 +#define CLK_FREQ_600M 600000000 +#define CLK_FREQ_500M 500000000 +#define CLK_FREQ_400M 400000000 +#define CLK_FREQ_200M 200000000 +#define CLK_FREQ_100M 100000000 +#define CLK_FREQ_24M 24000000 + +#define APLL_HIGH_FREQ 983040000 +#define APLL_LOW_FREQ 225792000 + +struct eswin_clk_pll { + struct clk_hw hw; + void __iomem *ctrl_reg0; + u8 pllen_shift; + u8 pllen_width; + u8 refdiv_shift; + u8 refdiv_width; + u8 fbdiv_shift; + u8 fbdiv_width; + + void __iomem *ctrl_reg1; + u8 frac_shift; + u8 frac_width; + + void __iomem *ctrl_reg2; + u8 postdiv1_shift; + u8 postdiv1_width; + u8 postdiv2_shift; + u8 postdiv2_width; + + void __iomem *status_reg; + u8 lock_shift; + u8 lock_width; +}; + +void __init eswin_clk_gate_register(struct device_node *np); +void __init eswin_clk_mux_register(struct device_node *np); +void __init eswin_clk_div_register(struct device_node *np); +void __init eswin_clk_pll_register(struct device_node *np); + +#endif /* __ESWIN_CLK_H__ */ -- 2.17.1 From: Xuyang Dong <dongxuyang@eswincomputing.com> Add clock device tree support for eic7700 SoC. Signed-off-by: Yifeng Huang <huangyifeng@eswincomputing.com> Signed-off-by: Xuyang Dong <dongxuyang@eswincomputing.com> --- arch/riscv/boot/dts/eswin/eic7700-clocks.dtsi | 2283 +++++++++++++++++ 1 file changed, 2283 insertions(+) create mode 100644 arch/riscv/boot/dts/eswin/eic7700-clocks.dtsi diff --git a/arch/riscv/boot/dts/eswin/eic7700-clocks.dtsi b/arch/riscv/boot/dts/eswin/eic7700-clocks.dtsi new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/arch/riscv/boot/dts/eswin/eic7700-clocks.dtsi @@ -XXX,XX +XXX,XX @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (c) 2025, Beijing ESWIN Computing Technology Co., Ltd. + */ + +/ { + clock-controller@51828000 { + compatible = "eswin,eic7700-clock"; + reg = <0x000000 0x51828000 0x000000 0x80000>; + #clock-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + /* fixed clock */ + fixed_rate_clk_apll_fout2: fixed-rate-apll-fout2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "fixed_rate_clk_apll_fout2"; + }; + fixed_rate_clk_apll_fout3: fixed-rate-apll-fout3 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "fixed_rate_clk_apll_fout3"; + }; + fixed_rate_clk_spll0_fout1: fixed-rate-spll0-fout1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1600000000>; + clock-output-names = "fixed_rate_clk_spll0_fout1"; + }; + fixed_rate_clk_spll0_fout2: fixed-rate-spll0-fout2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <800000000>; + clock-output-names = "fixed_rate_clk_spll0_fout2"; + }; + fixed_rate_clk_spll0_fout3: fixed-rate-spll0-fout3 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <400000000>; + clock-output-names = "fixed_rate_clk_spll0_fout3"; + }; + fixed_rate_clk_spll1_fout1: fixed-rate-spll1-fout1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1500000000>; + clock-output-names = "fixed_rate_clk_spll1_fout1"; + }; + fixed_rate_clk_spll1_fout2: fixed-rate-spll1-fout2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <300000000>; + clock-output-names = "fixed_rate_clk_spll1_fout2"; + }; + fixed_rate_clk_spll1_fout3: fixed-rate-spll1-fout3 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <250000000>; + clock-output-names = "fixed_rate_clk_spll1_fout3"; + }; + fixed_rate_clk_spll2_fout1: fixed-rate-spll2-fout1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <2080000000>; + clock-output-names = "fixed_rate_clk_spll2_fout1"; + }; + fixed_rate_clk_spll2_fout2: fixed-rate-spll2-fout2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1040000000>; + clock-output-names = "fixed_rate_clk_spll2_fout2"; + }; + fixed_rate_clk_spll2_fout3: fixed-rate-spll2-fout3 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <416000000>; + clock-output-names = "fixed_rate_clk_spll2_fout3"; + }; + fixed_rate_clk_vpll_fout1: fixed-rate-vpll-fout1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1188000000>; + clock-output-names = "fixed_rate_clk_vpll_fout1"; + }; + fixed_rate_clk_vpll_fout2: fixed-rate-vpll-fout2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <594000000>; + clock-output-names = "fixed_rate_clk_vpll_fout2"; + }; + fixed_rate_clk_vpll_fout3: fixed-rate-vpll-fout3 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <49500000>; + clock-output-names = "fixed_rate_clk_vpll_fout3"; + }; + fixed_rate_clk_xtal_24m: fixed-rate-xtal-24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "fixed_rate_clk_xtal_24m"; + }; + fixed_rate_clk_xtal_32k: fixed-rate-xtal-32K { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "fixed_rate_clk_xtal_32k"; + }; + fixed_rate_ext_mclk: fixed-rate-ext-mclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "fixed_rate_ext_mclk"; + }; + fixed_rate_lpddr_ref_bak: fixed-rate-lpddr { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "fixed_rate_lpddr_ref_bak"; + }; + /* pll */ + clk_apll_fout1: clk-apll-fout1-pll@50 { + compatible = "eswin,pll-clock"; + reg = <0x50>, <0x54>, <0x58>, <0xa4>; + #clock-cells = <0>; + enable-shift = <0>; + enable-width = <1>; + refdiv-shift = <12>; + refdiv-width = <6>; + fbdiv-shift = <20>; + fbdiv-width = <12>; + frac-shift = <4>; + frac-width = <24>; + postdiv1-shift = <1>; + postdiv1-width = <3>; + postdiv2-shift = <16>; + postdiv2-width = <3>; + lock-shift = <4>; + lock-width = <1>; + clock-output-names = "clk_apll_fout1"; + }; + clk_pll_cpu: clk-cpu-pll@64 { + compatible = "eswin,pll-clock"; + reg = <0x64>, <0x68>, <0x6c>, <0xa4>; + #clock-cells = <0>; + enable-shift = <0>; + enable-width = <1>; + refdiv-shift = <12>; + refdiv-width = <6>; + fbdiv-shift = <20>; + fbdiv-width = <12>; + frac-shift = <4>; + frac-width = <24>; + postdiv1-shift = <1>; + postdiv1-width = <3>; + postdiv2-shift = <16>; + postdiv2-width = <3>; + lock-shift = <5>; + lock-width = <1>; + clock-output-names = "clk_pll_cpu"; + }; + /* fixed factor clock */ + fixed_factor_clk_1m_div24: fixed-factor-clk-1m-div24 { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&fixed_rate_clk_xtal_24m>; + clock-div = <24>; + clock-mult = <1>; + clock-output-names = "fixed_factor_clk_1m_div24"; + }; + fixed_factor_cpu_div2: fixed-factor-cpu-div2 { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&mux_cpu_root_3mux1>; + clock-div = <2>; + clock-mult = <1>; + clock-output-names = "fixed_factor_cpu_div2"; + }; + fixed_factor_hsp_rmii_ref_div6: fixed-factor-hsp-rmii-ref-div6 { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&fixed_rate_clk_spll1_fout2>; + clock-div = <6>; + clock-mult = <1>; + clock-output-names = "fixed_factor_hsp_rmii_ref_div6"; + }; + fixed_factor_lpcpu_bus_div2: fixed-factor-lpcpu-bus-div2 { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&mux_lpcpu_core_clk_2mux1>; + clock-div = <2>; + clock-mult = <1>; + clock-output-names = "fixed_factor_lpcpu_bus_div2"; + }; + fixed_factor_mipi_txesc_div10: fixed-factor-mipi-txesc-div10 { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&mux_syscfg_clk_root_2mux1>; + clock-div = <10>; + clock-mult = <1>; + clock-output-names = "fixed_factor_mipi_txesc_div10"; + }; + fixed_factor_pcie_aux_div4: fixed-factor-pcie-aux-div4 { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&mux_syscfg_clk_root_2mux1>; + clock-div = <4>; + clock-mult = <1>; + clock-output-names = "fixed_factor_pcie_aux_div4"; + }; + fixed_factor_pcie_cr_div2: fixed-factor-pcie-cr-div2 { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&mux_syscfg_clk_root_2mux1>; + clock-div = <2>; + clock-mult = <1>; + clock-output-names = "fixed_factor_pcie_cr_div2"; + }; + fixed_factor_pvt_div20: fixed-factor-pvt-div20 { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&fixed_rate_clk_xtal_24m>; + clock-div = <20>; + clock-mult = <1>; + clock-output-names = "fixed_factor_pvt_div20"; + }; + fixed_factor_scpu_bus_div2: fixed-factor-scpu-bus-div2 { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&mux_scpu_core_clk_2mux1>; + clock-div = <2>; + clock-mult = <1>; + clock-output-names = "fixed_factor_scpu_bus_div2"; + }; + fixed_factor_u84_core_lp_div2: fixed-factor-u84-core-lp-div2 { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&gate_clk_spll0_fout2>; + clock-div = <2>; + clock-mult = <1>; + clock-output-names = "fixed_factor_u84_core_lp_div2"; + }; + /* mux clock */ + mux_bootspi_clk_2mux1: bootspi-clk-2mux1-mux@104 { + compatible = "eswin,mux-clock"; + reg = <0x104>; + #clock-cells = <0>; + clocks = <&divider_bootspi_div>, + <&fixed_rate_clk_xtal_24m>; + shift = <0>; + width = <1>; + clock-output-names = "mux_bootspi_clk_2mux1"; + }; + mux_scpu_core_clk_2mux1: scpu-core-clk-2mux1-mux@10c { + compatible = "eswin,mux-clock"; + reg = <0x10c>; + #clock-cells = <0>; + clocks = <&divider_scpu_core_div>, + <&fixed_rate_clk_xtal_24m>; + shift = <0>; + width = <1>; + clock-output-names = "mux_scpu_core_clk_2mux1"; + }; + mux_lpcpu_core_clk_2mux1: lpcpu-core-clk-2mux1-mux@114 { + compatible = "eswin,mux-clock"; + reg = <0x114>; + #clock-cells = <0>; + clocks = <&divider_lpcpu_core_div>, + <&fixed_rate_clk_xtal_24m>; + shift = <0>; + width = <1>; + clock-output-names = "mux_lpcpu_core_clk_2mux1"; + }; + mux_ddr_aclk_root_2mux1: ddr-aclk-root-2mux1-mux@124 { + compatible = "eswin,mux-clock"; + reg = <0x124>; + #clock-cells = <0>; + clocks = <&fixed_rate_clk_spll2_fout1>, + <&fixed_rate_clk_spll0_fout1>; + shift = <16>; + width = <1>; + clock-output-names = "mux_ddr_aclk_root_2mux1"; + }; + mux_dsp_aclk_root_2mux1: dsp-aclk-root-2mux1-mux@138 { + compatible = "eswin,mux-clock"; + reg = <0x138>; + #clock-cells = <0>; + clocks = <&fixed_rate_clk_spll2_fout1>, + <&fixed_rate_clk_spll0_fout1>; + shift = <0>; + width = <1>; + clock-output-names = "mux_dsp_aclk_root_2mux1"; + }; + mux_d2d_aclk_root_2mux1: d2d-aclk-root-2mux1-mux@140 { + compatible = "eswin,mux-clock"; + reg = <0x140>; + #clock-cells = <0>; + clocks = <&fixed_rate_clk_spll2_fout1>, + <&fixed_rate_clk_spll0_fout1>; + shift = <0>; + width = <1>; + clock-output-names = "mux_d2d_aclk_root_2mux1"; + }; + mux_sata_phy_2mux1: sata-phy-2mux1-mux@154 { + compatible = "eswin,mux-clock"; + reg = <0x154>; + #clock-cells = <0>; + clocks = <&divider_sata_phy_ref_div>, + <&fixed_rate_lpddr_ref_bak>; + shift = <9>; + width = <1>; + clock-output-names = "mux_sata_phy_2mux1"; + }; + mux_eth_core_2mux1: eth-core-2mux1-mux@158 { + compatible = "eswin,mux-clock"; + reg = <0x158>; + #clock-cells = <0>; + clocks = <&fixed_rate_clk_spll1_fout3>, + <&fixed_rate_lpddr_ref_bak>; + shift = <1>; + width = <1>; + clock-output-names = "mux_eth_core_2mux1"; + }; + mux_rmii_ref_2mux1: rmii-ref-2mux1-mux@158 { + compatible = "eswin,mux-clock"; + reg = <0x158>; + #clock-cells = <0>; + clocks = <&fixed_factor_hsp_rmii_ref_div6>, + <&fixed_rate_lpddr_ref_bak>; + shift = <2>; + width = <1>; + clock-output-names = "mux_rmii_ref_2mux1"; + }; + mux_mshcore_root_3mux1_0: mshcore0-root-3mux1-mux@160 { + compatible = "eswin,mux-clock"; + reg = <0x160>; + #clock-cells = <0>; + clocks = <&fixed_rate_clk_spll0_fout3>, + <&fixed_rate_clk_spll2_fout3>; + shift = <0>; + width = <1>; + clock-output-names = "mux_mshcore_root_3mux1_0"; + }; + mux_mshcore_root_3mux1_1: mshcore1-root-3mux1-mux@164 { + compatible = "eswin,mux-clock"; + reg = <0x164>; + #clock-cells = <0>; + clocks = <&fixed_rate_clk_spll0_fout3>, + <&fixed_rate_clk_spll2_fout3>; + shift = <0>; + width = <1>; + clock-output-names = "mux_mshcore_root_3mux1_1"; + }; + mux_mshcore_root_3mux1_2: mshcore2-root-3mux1-mux@168 { + compatible = "eswin,mux-clock"; + reg = <0x168>; + #clock-cells = <0>; + clocks = <&fixed_rate_clk_spll0_fout3>, + <&fixed_rate_clk_spll2_fout3>; + shift = <0>; + width = <1>; + clock-output-names = "mux_mshcore_root_3mux1_2"; + }; + mux_npu_llclk_3mux1: npu-llclk-3mux1-mux@17c { + compatible = "eswin,mux-clock"; + reg = <0x17c>; + #clock-cells = <0>; + clocks = <&divider_npu_llc_src0_div>, + <&divider_npu_llc_src1_div>, + <&fixed_rate_clk_vpll_fout1>; + shift = <0>; + width = <2>; + clock-output-names = "mux_npu_llclk_3mux1"; + }; + mux_npu_core_3mux1: npu-core-3mux1-mux@180 { + compatible = "eswin,mux-clock"; + reg = <0x180>; + #clock-cells = <0>; + clocks = <&fixed_rate_clk_spll1_fout1>, + <&fixed_rate_clk_vpll_fout1>, + <&fixed_rate_clk_spll2_fout2>; + shift = <0>; + width = <2>; + clock-output-names = "mux_npu_core_3mux1"; + }; + mux_npu_e31_3mux1: npu-e31-3mux1-mux@180 { + compatible = "eswin,mux-clock"; + reg = <0x180>; + #clock-cells = <0>; + clocks = <&fixed_rate_clk_spll1_fout1>, + <&fixed_rate_clk_vpll_fout1>, + <&fixed_rate_clk_spll2_fout2>; + shift = <8>; + width = <2>; + clock-output-names = "mux_npu_e31_3mux1"; + }; + mux_vi_dw_root_2mux1: vi-dw-root-2mux1-mux@184 { + compatible = "eswin,mux-clock"; + reg = <0x184>; + #clock-cells = <0>; + clocks = <&fixed_rate_clk_vpll_fout1>, + <&fixed_rate_clk_spll0_fout1>; + shift = <0>; + width = <1>; + clock-output-names = "mux_vi_dw_root_2mux1"; + }; + mux_vi_aclk_root_2mux1: vi-aclk-root-2mux1-mux@188 { + compatible = "eswin,mux-clock"; + reg = <0x188>; + #clock-cells = <0>; + clocks = <&fixed_rate_clk_spll0_fout1>, + <&fixed_rate_clk_spll2_fout1>; + shift = <0>; + width = <1>; + clock-output-names = "mux_vi_aclk_root_2mux1"; + }; + mux_vi_dig_isp_root_2mux1: vi-dig-isp-root-2mux1-mux@18c { + compatible = "eswin,mux-clock"; + reg = <0x18c>; + #clock-cells = <0>; + clocks = <&fixed_rate_clk_vpll_fout1>, + <&fixed_rate_clk_spll0_fout1>; + shift = <0>; + width = <1>; + clock-output-names = "mux_vi_dig_isp_root_2mux1"; + }; + mux_vi_dvp_root_2mux1: vi-dvp-root-2mux1-mux@190 { + compatible = "eswin,mux-clock"; + reg = <0x190>; + #clock-cells = <0>; + clocks = <&fixed_rate_clk_vpll_fout1>, + <&fixed_rate_clk_spll0_fout1>; + shift = <0>; + width = <1>; + clock-output-names = "mux_vi_dvp_root_2mux1"; + }; + mux_vo_aclk_root_2mux1: vo-aclk-root-2mux1-mux@1b0 { + compatible = "eswin,mux-clock"; + reg = <0x1b0>; + #clock-cells = <0>; + clocks = <&fixed_rate_clk_spll0_fout1>, + <&fixed_rate_clk_spll2_fout1>; + shift = <0>; + width = <1>; + clock-output-names = "mux_vo_aclk_root_2mux1"; + }; + mux_vo_pixel_root_2mux1: vo-pixel-root-2mux1-mux@1b8 { + compatible = "eswin,mux-clock"; + reg = <0x1b8>; + #clock-cells = <0>; + clocks = <&fixed_rate_clk_vpll_fout1>, + <&fixed_rate_clk_spll2_fout2>; + shift = <0>; + width = <1>; + clock-output-names = "mux_vo_pixel_root_2mux1"; + }; + mux_vo_mclk_2mux_ext_mclk: vo-mclk-2mux-ext-mclk-mux@1bc { + compatible = "eswin,mux-clock"; + reg = <0x1bc>; + #clock-cells = <0>; + clocks = <&divider_vo_mclk_div>, + <&fixed_rate_ext_mclk>; + shift = <0>; + width = <1>; + clock-output-names = "mux_vo_mclk_2mux_ext_mclk"; + }; + mux_vcaclk_root_2mux1: vcaclk-root-2mux1-mux@1c4 { + compatible = "eswin,mux-clock"; + reg = <0x1c4>; + #clock-cells = <0>; + clocks = <&fixed_rate_clk_spll0_fout1>, + <&fixed_rate_clk_spll2_fout1>; + shift = <0>; + width = <1>; + clock-output-names = "mux_vcaclk_root_2mux1"; + }; + mux_vcdec_root_2mux1: vcdec-root-2mux1-mux@1c8 { + compatible = "eswin,mux-clock"; + reg = <0x1c8>; + #clock-cells = <0>; + clocks = <&fixed_rate_clk_spll0_fout1>, + <&fixed_rate_clk_spll2_fout1>; + shift = <0>; + width = <1>; + clock-output-names = "mux_vcdec_root_2mux1"; + }; + mux_aondma_axi2mux1: aondma-axi2mux1-mux@1e4 { + compatible = "eswin,mux-clock"; + reg = <0x1e4>; + #clock-cells = <0>; + clocks = <&divider_aondma_axi_div>, + <&fixed_rate_clk_xtal_24m>; + shift = <20>; + width = <1>; + clock-output-names = "mux_aondma_axi2mux1"; + }; + mux_cpu_aclk_2mux1: cpu-aclk-2mux1-mux@208 { + compatible = "eswin,mux-clock"; + reg = <0x208>; + #clock-cells = <0>; + clocks = <&fixed_factor_cpu_div2>, + <&mux_cpu_root_3mux1>; + shift = <20>; + width = <1>; + clock-output-names = "mux_cpu_aclk_2mux1"; + }; + mux_cpu_root_3mux1: cpu-root-3mux1-mux@208 { + compatible = "eswin,mux-clock"; + reg = <0x208>; + #clock-cells = <0>; + clocks = <&clk_pll_cpu>, + <&fixed_factor_u84_core_lp_div2>, + <&fixed_rate_clk_xtal_24m>; + shift = <0>; + width = <2>; + clock-output-names = "mux_cpu_root_3mux1"; + }; + mux_syscfg_clk_root_2mux1: syscfg-clk-root-2mux1-mux@20c { + compatible = "eswin,mux-clock"; + reg = <0x20c>; + #clock-cells = <0>; + clocks = <&divider_sys_cfg_div>, + <&fixed_rate_clk_xtal_24m>; + shift = <0>; + width = <1>; + clock-output-names = "mux_syscfg_clk_root_2mux1"; + }; + /* div clock */ + divider_noc_nsp_div: noc-nsp-div@100 { + compatible = "eswin,divider-clock"; + reg = <0x100>; + #clock-cells = <0>; + clocks = <&fixed_rate_clk_spll2_fout1>; + shift = <0>; + width = <3>; + div-flags = <0x1>; + clock-output-names = "divider_noc_nsp_div"; + }; + divider_bootspi_div: bootspi-div@104 { + compatible = "eswin,divider-clock"; + reg = <0x104>; + #clock-cells = <0>; + clocks = <&gate_clk_spll0_fout2>; + shift = <4>; + width = <6>; + div-flags = <0x1>; + clock-output-names = "divider_bootspi_div"; + }; + divider_scpu_core_div: scpu-core-div@10c { + compatible = "eswin,divider-clock"; + reg = <0x10c>; + #clock-cells = <0>; + clocks = <&fixed_rate_clk_spll0_fout1>; + shift = <4>; + width = <4>; + div-flags = <0x1>; + clock-output-names = "divider_scpu_core_div"; + }; + divider_lpcpu_core_div: lpcpu-core-div@114 { + compatible = "eswin,divider-clock"; + reg = <0x114>; + #clock-cells = <0>; + clocks = <&fixed_rate_clk_spll0_fout1>; + shift = <4>; + width = <4>; + div-flags = <0x1>; + clock-output-names = "divider_lpcpu_core_div"; + }; + divider_ddr_aclk_div: ddr-aclk-div@124 { + compatible = "eswin,divider-clock"; + reg = <0x124>; + #clock-cells = <0>; + clocks = <&mux_ddr_aclk_root_2mux1>; + shift = <20>; + width = <4>; + div-flags = <0x1>; + clock-output-names = "divider_ddr_aclk_div"; + }; + divider_gpu_aclk_div: gpu-aclk-div@12c { + compatible = "eswin,divider-clock"; + reg = <0x12c>; + #clock-cells = <0>; + clocks = <&fixed_rate_clk_spll0_fout1>; + shift = <4>; + width = <4>; + div-flags = <0x1>; + clock-output-names = "divider_gpu_aclk_div"; + }; + divider_dsp_aclk_div: dsp-aclk-div@138 { + compatible = "eswin,divider-clock"; + reg = <0x138>; + #clock-cells = <0>; + clocks = <&mux_dsp_aclk_root_2mux1>; + shift = <4>; + width = <4>; + div-flags = <0x1>; + clock-output-names = "divider_dsp_aclk_div"; + }; + divider_dsp_0_aclk_div: dsp-0-aclk-div@13c { + compatible = "eswin,divider-clock"; + reg = <0x13c>; + #clock-cells = <0>; + clocks = <&gate_dspt_aclk>; + shift = <19>; + width = <1>; + div-flags = <0x5>; + clock-output-names = "divider_dsp_0_aclk_div"; + }; + divider_dsp_1_aclk_div: dsp-1-aclk-div@13c { + compatible = "eswin,divider-clock"; + reg = <0x13c>; + #clock-cells = <0>; + clocks = <&gate_dspt_aclk>; + shift = <20>; + width = <1>; + div-flags = <0x5>; + clock-output-names = "divider_dsp_1_aclk_div"; + }; + divider_dsp_2_aclk_div: dsp-2-aclk-div@13c { + compatible = "eswin,divider-clock"; + reg = <0x13c>; + #clock-cells = <0>; + clocks = <&gate_dspt_aclk>; + shift = <21>; + width = <1>; + div-flags = <0x5>; + clock-output-names = "divider_dsp_2_aclk_div"; + }; + divider_dsp_3_aclk_div: dsp-3-aclk-div@13c { + compatible = "eswin,divider-clock"; + reg = <0x13c>; + #clock-cells = <0>; + clocks = <&gate_dspt_aclk>; + shift = <22>; + width = <1>; + div-flags = <0x5>; + clock-output-names = "divider_dsp_3_aclk_div"; + }; + divider_d2d_aclk_div: d2d-aclk-div@140 { + compatible = "eswin,divider-clock"; + reg = <0x140>; + #clock-cells = <0>; + clocks = <&mux_d2d_aclk_root_2mux1>; + shift = <4>; + width = <4>; + div-flags = <0x1>; + clock-output-names = "divider_d2d_aclk_div"; + }; + divider_hsp_aclk_div: hsp-aclk-div@148 { + compatible = "eswin,divider-clock"; + reg = <0x148>; + #clock-cells = <0>; + clocks = <&fixed_rate_clk_spll0_fout1>; + shift = <4>; + width = <4>; + div-flags = <0x1>; + clock-output-names = "divider_hsp_aclk_div"; + }; + divider_sata_phy_ref_div: sata-phy-ref-div@154 { + compatible = "eswin,divider-clock"; + reg = <0x154>; + #clock-cells = <0>; + clocks = <&fixed_rate_clk_spll1_fout2>; + shift = <0>; + width = <4>; + div-flags = <0x1>; + clock-output-names = "divider_sata_phy_ref_div"; + }; + divider_eth_txclk_div_0: eth-0-txclk-div@158 { + compatible = "eswin,divider-clock"; + reg = <0x158>; + #clock-cells = <0>; + clocks = <&mux_eth_core_2mux1>; + shift = <4>; + width = <7>; + div-flags = <0x1>; + clock-output-names = "divider_eth_txclk_div_0"; + }; + divider_eth_txclk_div_1: eth-1-txclk-div@15c { + compatible = "eswin,divider-clock"; + reg = <0x15c>; + #clock-cells = <0>; + clocks = <&mux_eth_core_2mux1>; + shift = <4>; + width = <7>; + div-flags = <0x1>; + clock-output-names = "divider_eth_txclk_div_1"; + }; + divider_mshc_core_div_0: mshc-0-core-div@160 { + compatible = "eswin,divider-clock"; + reg = <0x160>; + #clock-cells = <0>; + clocks = <&mux_mshcore_root_3mux1_0>; + shift = <4>; + width = <12>; + div-flags = <0x5>; + clock-output-names = "divider_mshc_core_div_0"; + }; + divider_mshc_core_div_1: mshc-1-core-div@164 { + compatible = "eswin,divider-clock"; + reg = <0x164>; + #clock-cells = <0>; + clocks = <&mux_mshcore_root_3mux1_1>; + shift = <4>; + width = <12>; + div-flags = <0x5>; + clock-output-names = "divider_mshc_core_div_1"; + }; + divider_mshc_core_div_2: mshc-2-core-div@168 { + compatible = "eswin,divider-clock"; + reg = <0x168>; + #clock-cells = <0>; + clocks = <&mux_mshcore_root_3mux1_2>; + shift = <4>; + width = <12>; + div-flags = <0x5>; + clock-output-names = "divider_mshc_core_div_2"; + }; + divider_pcie_aclk_div: pcie-aclk-div@170 { + compatible = "eswin,divider-clock"; + reg = <0x170>; + #clock-cells = <0>; + clocks = <&fixed_rate_clk_spll2_fout2>; + shift = <4>; + width = <4>; + div-flags = <0x1>; + clock-output-names = "divider_pcie_aclk_div"; + }; + divider_npu_aclk_div: npu-aclk-div@178 { + compatible = "eswin,divider-clock"; + reg = <0x178>; + #clock-cells = <0>; + clocks = <&fixed_rate_clk_spll0_fout1>; + shift = <4>; + width = <4>; + div-flags = <0x1>; + clock-output-names = "divider_npu_aclk_div"; + }; + divider_npu_llc_src0_div: npu-llc-src0-div@17c { + compatible = "eswin,divider-clock"; + reg = <0x17c>; + #clock-cells = <0>; + clocks = <&fixed_rate_clk_spll0_fout1>; + shift = <4>; + width = <4>; + div-flags = <0x1>; + clock-output-names = "divider_npu_llc_src0_div"; + }; + divider_npu_llc_src1_div: npu-llc-src1-div@17c { + compatible = "eswin,divider-clock"; + reg = <0x17c>; + #clock-cells = <0>; + clocks = <&fixed_rate_clk_spll2_fout1>; + shift = <8>; + width = <4>; + div-flags = <0x1>; + clock-output-names = "divider_npu_llc_src1_div"; + }; + divider_npu_coreclk_div: npu-coreclk-div@180 { + compatible = "eswin,divider-clock"; + reg = <0x180>; + #clock-cells = <0>; + clocks = <&mux_npu_core_3mux1>; + shift = <4>; + width = <4>; + div-flags = <0x5>; + clock-output-names = "divider_npu_coreclk_div"; + }; + divider_npu_e31_div: npu-e31-div@180 { + compatible = "eswin,divider-clock"; + reg = <0x180>; + #clock-cells = <0>; + clocks = <&mux_npu_e31_3mux1>; + shift = <12>; + width = <4>; + div-flags = <0x5>; + clock-output-names = "divider_npu_e31_div"; + }; + divider_vi_dw_div: vi-dw-div@184 { + compatible = "eswin,divider-clock"; + reg = <0x184>; + #clock-cells = <0>; + clocks = <&mux_vi_dw_root_2mux1>; + shift = <4>; + width = <4>; + div-flags = <0x1>; + clock-output-names = "divider_vi_dw_div"; + }; + divider_vi_aclk_div: vi-aclk-div@188 { + compatible = "eswin,divider-clock"; + reg = <0x188>; + #clock-cells = <0>; + clocks = <&mux_vi_aclk_root_2mux1>; + shift = <4>; + width = <4>; + div-flags = <0x1>; + clock-output-names = "divider_vi_aclk_div"; + }; + divider_vi_dig_isp_div: vi-dig-isp-div@18c { + compatible = "eswin,divider-clock"; + reg = <0x18c>; + #clock-cells = <0>; + clocks = <&mux_vi_dig_isp_root_2mux1>; + shift = <4>; + width = <4>; + div-flags = <0x1>; + clock-output-names = "divider_vi_dig_isp_div"; + }; + divider_vi_dvp_div: vi-dvp-div@190 { + compatible = "eswin,divider-clock"; + reg = <0x190>; + #clock-cells = <0>; + clocks = <&mux_vi_dvp_root_2mux1>; + shift = <4>; + width = <4>; + div-flags = <0x1>; + clock-output-names = "divider_vi_dvp_div"; + }; + divider_vi_shutter_div_0: vi-shutter-0-div@194 { + compatible = "eswin,divider-clock"; + reg = <0x194>; + #clock-cells = <0>; + clocks = <&fixed_rate_clk_vpll_fout2>; + shift = <4>; + width = <7>; + div-flags = <0x1>; + clock-output-names = "divider_vi_shutter_div_0"; + }; + divider_vi_shutter_div_1: vi-shutter-1-div@198 { + compatible = "eswin,divider-clock"; + reg = <0x198>; + #clock-cells = <0>; + clocks = <&fixed_rate_clk_vpll_fout2>; + shift = <4>; + width = <7>; + div-flags = <0x1>; + clock-output-names = "divider_vi_shutter_div_1"; + }; + divider_vi_shutter_div_2: vi-shutter-2-div@19c { + compatible = "eswin,divider-clock"; + reg = <0x19c>; + #clock-cells = <0>; + clocks = <&fixed_rate_clk_vpll_fout2>; + shift = <4>; + width = <7>; + div-flags = <0x1>; + clock-output-names = "divider_vi_shutter_div_2"; + }; + divider_vi_shutter_div_3: vi-shutter-3-div@1a0 { + compatible = "eswin,divider-clock"; + reg = <0x1a0>; + #clock-cells = <0>; + clocks = <&fixed_rate_clk_vpll_fout2>; + shift = <4>; + width = <7>; + div-flags = <0x1>; + clock-output-names = "divider_vi_shutter_div_3"; + }; + divider_vi_shutter_div_4: vi-shutter-4-div@1a4 { + compatible = "eswin,divider-clock"; + reg = <0x1a4>; + #clock-cells = <0>; + clocks = <&fixed_rate_clk_vpll_fout2>; + shift = <4>; + width = <7>; + div-flags = <0x1>; + clock-output-names = "divider_vi_shutter_div_4"; + }; + divider_vi_shutter_div_5: vi-shutter-5-div@1a8 { + compatible = "eswin,divider-clock"; + reg = <0x1a8>; + #clock-cells = <0>; + clocks = <&fixed_rate_clk_vpll_fout2>; + shift = <4>; + width = <7>; + div-flags = <0x1>; + clock-output-names = "divider_vi_shutter_div_5"; + }; + divider_vo_aclk_div: vo-aclk-div@1b0 { + compatible = "eswin,divider-clock"; + reg = <0x1b0>; + #clock-cells = <0>; + clocks = <&mux_vo_aclk_root_2mux1>; + shift = <4>; + width = <4>; + div-flags = <0x1>; + clock-output-names = "divider_vo_aclk_div"; + }; + divider_iesmclk_div: iesmclk-div@1b4 { + compatible = "eswin,divider-clock"; + reg = <0x1b4>; + #clock-cells = <0>; + clocks = <&fixed_rate_clk_spll0_fout3>; + shift = <4>; + width = <4>; + div-flags = <0x1>; + clock-output-names = "divider_iesmclk_div"; + }; + divider_vo_pixel_div: vo-pixel-div@1b8 { + compatible = "eswin,divider-clock"; + reg = <0x1b8>; + #clock-cells = <0>; + clocks = <&mux_vo_pixel_root_2mux1>; + shift = <4>; + width = <6>; + div-flags = <0x1>; + clock-output-names = "divider_vo_pixel_div"; + }; + divider_vo_mclk_div: vo-mclk-div@1bc { + compatible = "eswin,divider-clock"; + reg = <0x1bc>; + #clock-cells = <0>; + clocks = <&clk_apll_fout1>; + shift = <4>; + width = <8>; + div-flags = <0x1>; + clock-output-names = "divider_vo_mclk_div"; + }; + divider_vo_cec_div: vo-cec-div@1c0 { + compatible = "eswin,divider-clock"; + reg = <0x1c0>; + #clock-cells = <0>; + clocks = <&fixed_rate_clk_vpll_fout2>; + shift = <16>; + width = <16>; + div-flags = <0x5>; + clock-output-names = "divider_vo_cec_div"; + }; + divider_vc_aclk_div: vc-aclk-div@1c4 { + compatible = "eswin,divider-clock"; + reg = <0x1c4>; + #clock-cells = <0>; + clocks = <&mux_vcaclk_root_2mux1>; + shift = <4>; + width = <4>; + div-flags = <0x1>; + clock-output-names = "divider_vc_aclk_div"; + }; + divider_g2d_div: g2d-div@1cc { + compatible = "eswin,divider-clock"; + reg = <0x1cc>; + #clock-cells = <0>; + clocks = <&mux_dsp_aclk_root_2mux1>; + shift = <4>; + width = <4>; + div-flags = <0x1>; + clock-output-names = "divider_g2d_div"; + }; + divider_aondma_axi_div: aondma-axi-div@1e4 { + compatible = "eswin,divider-clock"; + reg = <0x1d4>; + #clock-cells = <0>; + clocks = <&fixed_rate_clk_spll0_fout1>; + shift = <4>; + width = <4>; + div-flags = <0x1>; + clock-output-names = "divider_aondma_axi_div"; + }; + divider_je_div: je-div@1d4 { + compatible = "eswin,divider-clock"; + reg = <0x1d4>; + #clock-cells = <0>; + clocks = <&mux_vcdec_root_2mux1>; + shift = <4>; + width = <4>; + div-flags = <0x1>; + clock-output-names = "divider_je_div"; + }; + divider_jd_div: jd-div@1d8 { + compatible = "eswin,divider-clock"; + reg = <0x1d8>; + #clock-cells = <0>; + clocks = <&mux_vcdec_root_2mux1>; + shift = <4>; + width = <4>; + div-flags = <0x1>; + clock-output-names = "divider_jd_div"; + }; + divider_vd_div: vd-div@1dc { + compatible = "eswin,divider-clock"; + reg = <0x1dc>; + #clock-cells = <0>; + clocks = <&mux_vcdec_root_2mux1>; + shift = <4>; + width = <4>; + div-flags = <0x1>; + clock-output-names = "divider_vd_div"; + }; + divider_ve_div: ve-div@1e0 { + compatible = "eswin,divider-clock"; + reg = <0x1e0>; + #clock-cells = <0>; + clocks = <&mux_vcdec_root_2mux1>; + shift = <4>; + width = <4>; + div-flags = <0x1>; + clock-output-names = "divider_ve_div"; + }; + divider_aon_rtc_div: aon-rtc-div@1ec{ + compatible = "eswin,divider-clock"; + reg = <0x1ec>; + #clock-cells = <0>; + clocks = <&fixed_factor_clk_1m_div24>; + shift = <21>; + width = <11>; + div-flags = <0x1>; + clock-output-names = "divider_aon_rtc_div"; + }; + divider_u84_rtc_toggle: u84-rtc-toggle-div@1ec { + compatible = "eswin,divider-clock"; + reg = <0x1ec>; + #clock-cells = <0>; + clocks = <&fixed_rate_clk_xtal_24m>; + shift = <16>; + width = <5>; + div-flags = <0x5>; + clock-output-names = "divider_u84_rtc_toggle"; + }; + divider_crypto_div: crypto-div@1f4 { + compatible = "eswin,divider-clock"; + reg = <0x1f4>; + #clock-cells = <0>; + clocks = <&fixed_rate_clk_spll0_fout1>; + shift = <4>; + width = <4>; + div-flags = <0x1>; + clock-output-names = "divider_crypto_div"; + }; + divider_sys_cfg_div: sys-cfg-div@20c { + compatible = "eswin,divider-clock"; + reg = <0x20c>; + #clock-cells = <0>; + clocks = <&fixed_rate_clk_spll0_fout3>; + shift = <4>; + width = <3>; + div-flags = <0x1>; + clock-output-names = "divider_sys_cfg_div"; + }; + /* gate clock */ + gate_clk_spll0_fout2: clk-spll0-fout2-gate@8 { + compatible = "eswin,gate-clock"; + reg = <0x8>; + #clock-cells = <0>; + clocks = <&fixed_rate_clk_spll0_fout2>; + bit-index = <31>; + clock-output-names = "gate_clk_spll0_fout2"; + }; + gate_noc_nsp_clk: noc-nsp-clk-gate@100 { + compatible = "eswin,gate-clock"; + reg = <0x100>; + #clock-cells = <0>; + clocks = <&divider_noc_nsp_div>; + bit-index = <31>; + clock-output-names = "gate_noc_nsp_clk"; + }; + gate_clk_bootspi: clk-bootspi-gate@104 { + compatible = "eswin,gate-clock"; + reg = <0x104>; + #clock-cells = <0>; + clocks = <&mux_bootspi_clk_2mux1>; + bit-index = <31>; + clock-output-names = "gate_clk_bootspi"; + }; + gate_clk_bootspi_cfg: clk-bootspi-cfg-gate@108 { + compatible = "eswin,gate-clock"; + reg = <0x108>; + #clock-cells = <0>; + clocks = <&mux_syscfg_clk_root_2mux1>; + bit-index = <31>; + clock-output-names = "gate_clk_bootspi_cfg"; + }; + gate_clk_scpu_core: clk-scpu-core-gate@10c { + compatible = "eswin,gate-clock"; + reg = <0x10c>; + #clock-cells = <0>; + clocks = <&mux_scpu_core_clk_2mux1>; + bit-index = <31>; + clock-output-names = "gate_clk_scpu_core"; + }; + gate_clk_scpu_bus: clk-scpu-bus-gate@110 { + compatible = "eswin,gate-clock"; + reg = <0x110>; + #clock-cells = <0>; + clocks = <&fixed_factor_scpu_bus_div2>; + bit-index = <31>; + clock-output-names = "gate_clk_scpu_bus"; + }; + gate_clk_lpcpu_core: clk-lpcpu-core-gate@114 { + compatible = "eswin,gate-clock"; + reg = <0x114>; + #clock-cells = <0>; + clocks = <&mux_lpcpu_core_clk_2mux1>; + bit-index = <31>; + clock-output-names = "gate_clk_lpcpu_core"; + }; + gate_clk_lpcpu_bus: clk-lpcpu-bus-gate@118 { + compatible = "eswin,gate-clock"; + reg = <0x118>; + #clock-cells = <0>; + clocks = <&fixed_factor_lpcpu_bus_div2>; + bit-index = <31>; + clock-output-names = "gate_clk_lpcpu_bus"; + }; + gate_tcu_aclk: tcu-aclk-gate@11c { + compatible = "eswin,gate-clock"; + reg = <0x11c>; + #clock-cells = <0>; + clocks = <&divider_ddr_aclk_div>; + bit-index = <31>; + clock-output-names = "gate_tcu_aclk"; + }; + gate_tcu_cfg_clk: tcu-cfg-clk-gate@120 { + compatible = "eswin,gate-clock"; + reg = <0x120>; + #clock-cells = <0>; + clocks = <&mux_syscfg_clk_root_2mux1>; + bit-index = <31>; + clock-output-names = "gate_tcu_cfg_clk"; + }; + gate_ddrt_cfg_clk: ddrt-cfg-clk-gate@124 { + compatible = "eswin,gate-clock"; + reg = <0x124>; + #clock-cells = <0>; + clocks = <&mux_syscfg_clk_root_2mux1>; + bit-index = <9>; + clock-output-names = "gate_ddrt_cfg_clk"; + }; + gate_ddrt0_p0_aclk: ddrt0-p0-aclk-gate@124 { + compatible = "eswin,gate-clock"; + reg = <0x124>; + #clock-cells = <0>; + clocks = <&divider_ddr_aclk_div>; + bit-index = <4>; + clock-output-names = "gate_ddrt0_p0_aclk"; + }; + gate_ddrt0_p1_aclk: ddrt0-p1-aclk-gate@124 { + compatible = "eswin,gate-clock"; + reg = <0x124>; + #clock-cells = <0>; + clocks = <&divider_ddr_aclk_div>; + bit-index = <5>; + clock-output-names = "gate_ddrt0_p1_aclk"; + }; + gate_ddrt0_p2_aclk: ddrt0-p2-aclk-gate@124 { + compatible = "eswin,gate-clock"; + reg = <0x124>; + #clock-cells = <0>; + clocks = <&divider_ddr_aclk_div>; + bit-index = <6>; + clock-output-names = "gate_ddrt0_p2_aclk"; + }; + gate_ddrt0_p3_aclk: ddrt0-p3-aclk-gate@124 { + compatible = "eswin,gate-clock"; + reg = <0x124>; + #clock-cells = <0>; + clocks = <&divider_ddr_aclk_div>; + bit-index = <7>; + clock-output-names = "gate_ddrt0_p3_aclk"; + }; + gate_ddrt0_p4_aclk: ddrt0-p4-aclk-gate@124 { + compatible = "eswin,gate-clock"; + reg = <0x124>; + #clock-cells = <0>; + clocks = <&divider_ddr_aclk_div>; + bit-index = <8>; + clock-output-names = "gate_ddrt0_p4_aclk"; + }; + gate_ddrt1_p0_aclk: ddrt1-p0-aclk-gate@128 { + compatible = "eswin,gate-clock"; + reg = <0x128>; + #clock-cells = <0>; + clocks = <&divider_ddr_aclk_div>; + bit-index = <4>; + clock-output-names = "gate_ddrt1_p0_aclk"; + }; + gate_ddrt1_p1_aclk: ddrt1-p1-aclk-gate@128 { + compatible = "eswin,gate-clock"; + reg = <0x128>; + #clock-cells = <0>; + clocks = <&divider_ddr_aclk_div>; + bit-index = <5>; + clock-output-names = "gate_ddrt1_p1_aclk"; + }; + gate_ddrt1_p2_aclk: ddrt1-p2-aclk-gate@128 { + compatible = "eswin,gate-clock"; + reg = <0x128>; + #clock-cells = <0>; + clocks = <&divider_ddr_aclk_div>; + bit-index = <6>; + clock-output-names = "gate_ddrt1_p2_aclk"; + }; + gate_ddrt1_p3_aclk: ddrt1-p3-aclk-gate@128 { + compatible = "eswin,gate-clock"; + reg = <0x128>; + #clock-cells = <0>; + clocks = <&divider_ddr_aclk_div>; + bit-index = <7>; + clock-output-names = "gate_ddrt1_p3_aclk"; + }; + gate_ddrt1_p4_aclk: ddrt1-p4-aclk-gate@128 { + compatible = "eswin,gate-clock"; + reg = <0x128>; + #clock-cells = <0>; + clocks = <&divider_ddr_aclk_div>; + bit-index = <8>; + clock-output-names = "gate_ddrt1_p4_aclk"; + }; + gate_gpu_aclk: gpu-aclk-gate@12c { + compatible = "eswin,gate-clock"; + reg = <0x12c>; + #clock-cells = <0>; + clocks = <&divider_gpu_aclk_div>; + bit-index = <31>; + clock-output-names = "gate_gpu_aclk"; + }; + gate_gpu_cfg_clk: gpu-cfg-clk-gate@130 { + compatible = "eswin,gate-clock"; + reg = <0x130>; + #clock-cells = <0>; + clocks = <&mux_syscfg_clk_root_2mux1>; + bit-index = <31>; + clock-output-names = "gate_gpu_cfg_clk"; + }; + gate_gpu_gray_clk: gpu-gray-clk-gate@134 { + compatible = "eswin,gate-clock"; + reg = <0x134>; + #clock-cells = <0>; + clocks = <&fixed_rate_clk_xtal_24m>; + bit-index = <31>; + clock-output-names = "gate_gpu_gray_clk"; + }; + gate_dspt_aclk: dspt-aclk-gate@138 { + compatible = "eswin,gate-clock"; + reg = <0x138>; + #clock-cells = <0>; + clocks = <&divider_dsp_aclk_div>; + bit-index = <31>; + clock-output-names = "gate_dspt_aclk"; + }; + gate_dspt_cfg_clk: dspt-cfg-clk-gate@13c { + compatible = "eswin,gate-clock"; + reg = <0x13c>; + #clock-cells = <0>; + clocks = <&mux_syscfg_clk_root_2mux1>; + bit-index = <31>; + clock-output-names = "gate_dspt_cfg_clk"; + }; + gate_d2d_aclk: d2d-aclk-gate@140 { + compatible = "eswin,gate-clock"; + reg = <0x140>; + #clock-cells = <0>; + clocks = <&divider_d2d_aclk_div>; + bit-index = <31>; + clock-output-names = "gate_d2d_aclk"; + }; + gate_d2d_cfg_clk: d2d-cfg-clk-gate@144 { + compatible = "eswin,gate-clock"; + reg = <0x144>; + #clock-cells = <0>; + clocks = <&mux_syscfg_clk_root_2mux1>; + bit-index = <31>; + clock-output-names = "gate_d2d_cfg_clk"; + }; + gate_clk_hsp_aclk: clk-hsp-aclk-gate@148 { + compatible = "eswin,gate-clock"; + reg = <0x148>; + #clock-cells = <0>; + clocks = <&divider_hsp_aclk_div>; + bit-index = <31>; + clock-output-names = "gate_clk_hsp_aclk"; + }; + gate_hsp_dma0_clk: hsp-dma0-clk-gate@148 { + compatible = "eswin,gate-clock"; + reg = <0x148>; + #clock-cells = <0>; + clocks = <&gate_clk_hsp_aclk>; + bit-index = <0>; + clock-output-names = "gate_hsp_dma0_clk"; + }; + gate_hsp_dma0_clk_test: hsp-dma0-clk-test-gate@148 { + compatible = "eswin,gate-clock"; + reg = <0x148>; + #clock-cells = <0>; + clocks = <&gate_clk_hsp_aclk>; + bit-index = <1>; + clock-output-names = "gate_hsp_dma0_clk_test"; + }; + gate_clk_hsp_cfgclk: clk-hsp-cfgclk-gate@14c { + compatible = "eswin,gate-clock"; + reg = <0x14c>; + #clock-cells = <0>; + clocks = <&mux_syscfg_clk_root_2mux1>; + bit-index = <31>; + clock-output-names = "gate_clk_hsp_cfgclk"; + }; + gate_hsp_sata_rbc_clk: hsp-sata-rbc-clk-gate@150 { + compatible = "eswin,gate-clock"; + reg = <0x150>; + #clock-cells = <0>; + clocks = <&fixed_rate_clk_spll1_fout2>; + bit-index = <0>; + clock-output-names = "gate_hsp_sata_rbc_clk"; + }; + gate_hsp_sata_oob_clk: hsp-sata-oob-clk-gate@154 { + compatible = "eswin,gate-clock"; + reg = <0x154>; + #clock-cells = <0>; + clocks = <&mux_sata_phy_2mux1>; + bit-index = <31>; + clock-output-names = "gate_hsp_sata_oob_clk"; + }; + gate_hsp_eth0_core_clk: hsp-eth0-core-clk-gate@158 { + compatible = "eswin,gate-clock"; + reg = <0x158>; + #clock-cells = <0>; + clocks = <&divider_eth_txclk_div_0>; + bit-index = <0>; + clock-output-names = "gate_hsp_eth0_core_clk"; + }; + gate_hsp_rmii_ref_0: hsp-rmii-ref-0-gate@158 { + compatible = "eswin,gate-clock"; + reg = <0x158>; + #clock-cells = <0>; + clocks = <&mux_rmii_ref_2mux1>; + bit-index = <31>; + clock-output-names = "gate_hsp_rmii_ref_0"; + }; + gate_hsp_eth1_core_clk: hsp-eth1-core-clk-gate@15c { + compatible = "eswin,gate-clock"; + reg = <0x15c>; + #clock-cells = <0>; + clocks = <&divider_eth_txclk_div_1>; + bit-index = <0>; + clock-output-names = "gate_hsp_eth1_core_clk"; + }; + gate_hsp_rmii_ref_1: hsp-rmii-ref-1-gate@15c { + compatible = "eswin,gate-clock"; + reg = <0x15c>; + #clock-cells = <0>; + clocks = <&mux_rmii_ref_2mux1>; + bit-index = <31>; + clock-output-names = "gate_hsp_rmii_ref_1"; + }; + gate_hsp_mshc0_core_clk: hsp-mshc0-core-clk-gate@160 { + compatible = "eswin,gate-clock"; + reg = <0x160>; + #clock-cells = <0>; + clocks = <&divider_mshc_core_div_0>; + bit-index = <16>; + clock-output-names = "gate_hsp_mshc0_core_clk"; + }; + gate_hsp_mshc1_core_clk: hsp-mshc1-core-clk-gate@164 { + compatible = "eswin,gate-clock"; + reg = <0x164>; + #clock-cells = <0>; + clocks = <&divider_mshc_core_div_1>; + bit-index = <16>; + clock-output-names = "gate_hsp_mshc1_core_clk"; + }; + gate_hsp_mshc2_core_clk: hsp-mshc2-core-clk-gate@168 { + compatible = "eswin,gate-clock"; + reg = <0x168>; + #clock-cells = <0>; + clocks = <&divider_mshc_core_div_2>; + bit-index = <16>; + clock-output-names = "gate_hsp_mshc2_core_clk"; + }; + gate_pciet_aclk: pciet-aclk-gate@170 { + compatible = "eswin,gate-clock"; + reg = <0x170>; + #clock-cells = <0>; + clocks = <&divider_pcie_aclk_div>; + bit-index = <31>; + clock-output-names = "gate_pciet_aclk"; + }; + gate_pciet_aux_clk: pciet-aux-clk-gate@174 { + compatible = "eswin,gate-clock"; + reg = <0x174>; + #clock-cells = <0>; + clocks = <&fixed_factor_pcie_aux_div4>; + bit-index = <1>; + clock-output-names = "gate_pciet_aux_clk"; + }; + gate_pciet_cfg_clk: pciet-cfg-clk-gate@174 { + compatible = "eswin,gate-clock"; + reg = <0x174>; + #clock-cells = <0>; + clocks = <&mux_syscfg_clk_root_2mux1>; + bit-index = <31>; + clock-output-names = "gate_pciet_cfg_clk"; + }; + gate_pciet_cr_clk: pciet-cr-clk-gate@174 { + compatible = "eswin,gate-clock"; + reg = <0x174>; + #clock-cells = <0>; + clocks = <&fixed_factor_pcie_cr_div2>; + bit-index = <0>; + clock-output-names = "gate_pciet_cr_clk"; + }; + gate_npu_aclk: npu-aclk-gate@178 { + compatible = "eswin,gate-clock"; + reg = <0x178>; + #clock-cells = <0>; + clocks = <&divider_npu_aclk_div>; + bit-index = <31>; + clock-output-names = "gate_npu_aclk"; + }; + gate_npu_cfg_clk: npu-cfg-clk-gate@178 { + compatible = "eswin,gate-clock"; + reg = <0x178>; + #clock-cells = <0>; + clocks = <&mux_syscfg_clk_root_2mux1>; + bit-index = <30>; + clock-output-names = "gate_npu_cfg_clk"; + }; + gate_npu_llc_aclk: npu-llc-aclk-gate@17c { + compatible = "eswin,gate-clock"; + reg = <0x17c>; + #clock-cells = <0>; + clocks = <&mux_npu_llclk_3mux1>; + bit-index = <31>; + clock-output-names = "gate_npu_llc_aclk"; + }; + gate_npu_clk: npu-clk-gate@180 { + compatible = "eswin,gate-clock"; + reg = <0x180>; + #clock-cells = <0>; + clocks = <&divider_npu_coreclk_div>; + bit-index = <31>; + clock-output-names = "gate_npu_clk"; + }; + gate_npu_e31_clk: npu-e31-clk-gate@180 { + compatible = "eswin,gate-clock"; + reg = <0x180>; + #clock-cells = <0>; + clocks = <&divider_npu_e31_div>; + bit-index = <30>; + clock-output-names = "gate_npu_e31_clk"; + }; + gate_vi_dig_dw_clk: vi-dig-dw-clk-gate@184 { + compatible = "eswin,gate-clock"; + reg = <0x184>; + #clock-cells = <0>; + clocks = <&divider_vi_dw_div>; + bit-index = <31>; + clock-output-names = "gate_vi_dig_dw_clk"; + }; + gate_vi_aclk: vi-aclk-gate@188 { + compatible = "eswin,gate-clock"; + reg = <0x188>; + #clock-cells = <0>; + clocks = <&divider_vi_aclk_div>; + bit-index = <31>; + clock-output-names = "gate_vi_aclk"; + }; + gate_vi_cfg_clk: vi-cfg-clk-gate@188 { + compatible = "eswin,gate-clock"; + reg = <0x188>; + #clock-cells = <0>; + clocks = <&mux_syscfg_clk_root_2mux1>; + bit-index = <30>; + clock-output-names = "gate_vi_cfg_clk"; + }; + gate_vi_dig_isp_clk: vi-dig-isp-clk-gate@18c { + compatible = "eswin,gate-clock"; + reg = <0x18c>; + #clock-cells = <0>; + clocks = <&divider_vi_dig_isp_div>; + bit-index = <31>; + clock-output-names = "gate_vi_dig_isp_clk"; + }; + gate_vi_dvp_clk: vi-dvp-clk-gate@190 { + compatible = "eswin,gate-clock"; + reg = <0x190>; + #clock-cells = <0>; + clocks = <&divider_vi_dvp_div>; + bit-index = <31>; + clock-output-names = "gate_vi_dvp_clk"; + }; + gate_vi_shutter_0: vi-shutter-0-gate@194 { + compatible = "eswin,gate-clock"; + reg = <0x194>; + #clock-cells = <0>; + clocks = <&divider_vi_shutter_div_0>; + bit-index = <31>; + clock-output-names = "gate_vi_shutter_0"; + }; + gate_vi_shutter_1: vi-shutter-1-gate@198 { + compatible = "eswin,gate-clock"; + reg = <0x198>; + #clock-cells = <0>; + clocks = <&divider_vi_shutter_div_1>; + bit-index = <31>; + clock-output-names = "gate_vi_shutter_1"; + }; + gate_vi_shutter_2: vi-shutter-2-gate@19c { + compatible = "eswin,gate-clock"; + reg = <0x19c>; + #clock-cells = <0>; + clocks = <&divider_vi_shutter_div_2>; + bit-index = <31>; + clock-output-names = "gate_vi_shutter_2"; + }; + gate_vi_shutter_3: vi-shutter-3-gate@1a0 { + compatible = "eswin,gate-clock"; + reg = <0x1a0>; + #clock-cells = <0>; + clocks = <&divider_vi_shutter_div_3>; + bit-index = <31>; + clock-output-names = "gate_vi_shutter_3"; + }; + gate_vi_shutter_4: vi-shutter-4-gate@1a4 { + compatible = "eswin,gate-clock"; + reg = <0x1a4>; + #clock-cells = <0>; + clocks = <&divider_vi_shutter_div_4>; + bit-index = <31>; + clock-output-names = "gate_vi_shutter_4"; + }; + gate_vi_shutter_5: vi-shutter-5-gate@1a8 { + compatible = "eswin,gate-clock"; + reg = <0x1a8>; + #clock-cells = <0>; + clocks = <&divider_vi_shutter_div_5>; + bit-index = <31>; + clock-output-names = "gate_vi_shutter_5"; + }; + gate_vi_phy_cfg: vi-phy-cfg-gate@1ac { + compatible = "eswin,gate-clock"; + reg = <0x1ac>; + #clock-cells = <0>; + clocks = <&fixed_rate_clk_xtal_24m>; + bit-index = <1>; + clock-output-names = "gate_vi_phy_cfg"; + }; + gate_vi_phy_txclkesc: vi-phy-txclkesc-gate@1ac { + compatible = "eswin,gate-clock"; + reg = <0x1ac>; + #clock-cells = <0>; + clocks = <&fixed_factor_mipi_txesc_div10>; + bit-index = <0>; + clock-output-names = "gate_vi_phy_txclkesc"; + }; + gate_vo_aclk: vo-aclk-gate@1b0 { + compatible = "eswin,gate-clock"; + reg = <0x1b0>; + #clock-cells = <0>; + clocks = <&divider_vo_aclk_div>; + bit-index = <31>; + clock-output-names = "gate_vo_aclk"; + }; + gate_vo_cfg_clk: vo-cfg-clk-gate@1b0 { + compatible = "eswin,gate-clock"; + reg = <0x1b0>; + #clock-cells = <0>; + clocks = <&mux_syscfg_clk_root_2mux1>; + bit-index = <30>; + clock-output-names = "gate_vo_cfg_clk"; + }; + gate_vo_hdmi_iesmclk: vo-hdmi-iesmclk-gate@1b4 { + compatible = "eswin,gate-clock"; + reg = <0x1b4>; + #clock-cells = <0>; + clocks = <&divider_iesmclk_div>; + bit-index = <31>; + clock-output-names = "gate_vo_hdmi_iesmclk"; + }; + gate_vo_pixel_clk: vo-pixel-clk-gate@1b8 { + compatible = "eswin,gate-clock"; + reg = <0x1b8>; + #clock-cells = <0>; + clocks = <&divider_vo_pixel_div>; + bit-index = <31>; + clock-output-names = "gate_vo_pixel_clk"; + }; + gate_vo_i2s_mclk: vo-i2s-mclk-gate@1bc { + compatible = "eswin,gate-clock"; + reg = <0x1bc>; + #clock-cells = <0>; + clocks = <&mux_vo_mclk_2mux_ext_mclk>; + bit-index = <31>; + clock-output-names = "gate_vo_i2s_mclk"; + }; + gate_vo_cr_clk: vo-cr-clk-gate@1c0 { + compatible = "eswin,gate-clock"; + reg = <0x1c0>; + #clock-cells = <0>; + clocks = <&fixed_factor_mipi_txesc_div10>; + bit-index = <1>; + clock-output-names = "gate_vo_cr_clk"; + }; + gate_vc_aclk: vc-aclk-gate@1c4 { + compatible = "eswin,gate-clock"; + reg = <0x1c4>; + #clock-cells = <0>; + clocks = <&divider_vc_aclk_div>; + bit-index = <31>; + clock-output-names = "gate_vc_aclk"; + }; + gate_g2d_aclk: g2d-aclk-gate@1cc { + compatible = "eswin,gate-clock"; + reg = <0x1cc>; + #clock-cells = <0>; + clocks = <&divider_g2d_div>; + bit-index = <31>; + clock-output-names = "gate_g2d_aclk"; + }; + gate_g2d_cfg_clk: g2d-cfg-clk-gate@1cc { + compatible = "eswin,gate-clock"; + reg = <0x1cc>; + #clock-cells = <0>; + clocks = <&mux_syscfg_clk_root_2mux1>; + bit-index = <28>; + clock-output-names = "gate_g2d_cfg_clk"; + }; + gate_g2d_clk: g2d-clk-gate@1cc { + compatible = "eswin,gate-clock"; + reg = <0x1cc>; + #clock-cells = <0>; + clocks = <&divider_g2d_div>; + bit-index = <30>; + clock-output-names = "gate_g2d_clk"; + }; + gate_vc_cfg_clk: vc-cfg-clk-gate@1d0 { + compatible = "eswin,gate-clock"; + reg = <0x1d0>; + #clock-cells = <0>; + clocks = <&mux_syscfg_clk_root_2mux1>; + bit-index = <0>; + clock-output-names = "gate_vc_cfg_clk"; + }; + gate_vc_jd_pclk: vc-jd-pclk-gate@1d0 { + compatible = "eswin,gate-clock"; + reg = <0x1d0>; + #clock-cells = <0>; + clocks = <&mux_syscfg_clk_root_2mux1>; + bit-index = <1>; + clock-output-names = "gate_vc_jd_pclk"; + }; + gate_vc_je_pclk: vc-je-pclk-gate@1d0 { + compatible = "eswin,gate-clock"; + reg = <0x1d0>; + #clock-cells = <0>; + clocks = <&mux_syscfg_clk_root_2mux1>; + bit-index = <2>; + clock-output-names = "gate_vc_je_pclk"; + }; + gate_vc_mon_pclk: vc-mon-pclk-gate@1d0 { + compatible = "eswin,gate-clock"; + reg = <0x1d0>; + #clock-cells = <0>; + clocks = <&mux_syscfg_clk_root_2mux1>; + bit-index = <3>; + clock-output-names = "gate_vc_mon_pclk"; + }; + gate_vc_vd_pclk: vc-vd-pclk-gate@1d0 { + compatible = "eswin,gate-clock"; + reg = <0x1d0>; + #clock-cells = <0>; + clocks = <&mux_syscfg_clk_root_2mux1>; + bit-index = <4>; + clock-output-names = "gate_vc_vd_pclk"; + }; + gate_vc_ve_pclk: vc-ve-pclk-gate@1d0 { + compatible = "eswin,gate-clock"; + reg = <0x1d0>; + #clock-cells = <0>; + clocks = <&mux_syscfg_clk_root_2mux1>; + bit-index = <5>; + clock-output-names = "gate_vc_ve_pclk"; + }; + gate_vc_je_clk: vc-je-clk-gate@1d4 { + compatible = "eswin,gate-clock"; + reg = <0x1d4>; + #clock-cells = <0>; + clocks = <&divider_je_div>; + bit-index = <31>; + clock-output-names = "gate_vc_je_clk"; + }; + gate_vc_jd_clk: vc-jd-clk-gate@1d8 { + compatible = "eswin,gate-clock"; + reg = <0x1d8>; + #clock-cells = <0>; + clocks = <&divider_jd_div>; + bit-index = <31>; + clock-output-names = "gate_vc_jd_clk"; + }; + gate_vc_vd_clk: vc-vd-clk-gate@1dc { + compatible = "eswin,gate-clock"; + reg = <0x1dc>; + #clock-cells = <0>; + clocks = <&divider_vd_div>; + bit-index = <31>; + clock-output-names = "gate_vc_vd_clk"; + }; + gate_vc_ve_clk: vc-ve-clk-gate@1e0 { + compatible = "eswin,gate-clock"; + reg = <0x1e0>; + #clock-cells = <0>; + clocks = <&divider_ve_div>; + bit-index = <31>; + clock-output-names = "gate_vc_ve_clk"; + }; + gate_aondma_aclk: aondma-aclk-gate@1e4 { + compatible = "eswin,gate-clock"; + reg = <0x1e4>; + #clock-cells = <0>; + clocks = <&mux_aondma_axi2mux1>; + bit-index = <31>; + clock-output-names = "gate_aondma_aclk"; + }; + gate_aon_aclk: aon-aclk-gate@1e4 { + compatible = "eswin,gate-clock"; + reg = <0x1e4>; + #clock-cells = <0>; + clocks = <&mux_aondma_axi2mux1>; + bit-index = <29>; + clock-output-names = "gate_aon_aclk"; + }; + gate_clk_aondma_cfg: clk-aondma-cfg-gate@1e4 { + compatible = "eswin,gate-clock"; + reg = <0x1e4>; + #clock-cells = <0>; + clocks = <&mux_syscfg_clk_root_2mux1>; + bit-index = <30>; + clock-output-names = "gate_clk_aondma_cfg"; + }; + gate_timer3_clk8: timer3-clk8-gate@1e8 { + compatible = "eswin,gate-clock"; + reg = <0x1e8>; + #clock-cells = <0>; + clocks = <&fixed_rate_clk_vpll_fout3>; + bit-index = <8>; + clock-output-names = "gate_timer3_clk8"; + }; + gate_timer_pclk_0: timer-pclk-0-gate@1e8 { + compatible = "eswin,gate-clock"; + reg = <0x1e8>; + #clock-cells = <0>; + clocks = <&mux_syscfg_clk_root_2mux1>; + bit-index = <4>; + clock-output-names = "gate_timer_pclk_0"; + }; + gate_timer_pclk_1: timer-pclk-1-gate@1e8 { + compatible = "eswin,gate-clock"; + reg = <0x1e8>; + #clock-cells = <0>; + clocks = <&mux_syscfg_clk_root_2mux1>; + bit-index = <5>; + clock-output-names = "gate_timer_pclk_1"; + }; + gate_timer_pclk_2: timer-pclk-2-gate@1e8 { + compatible = "eswin,gate-clock"; + reg = <0x1e8>; + #clock-cells = <0>; + clocks = <&mux_syscfg_clk_root_2mux1>; + bit-index = <6>; + clock-output-names = "gate_timer_pclk_2"; + }; + gate_timer_pclk_3: timer-pclk-3-gate@1e8 { + compatible = "eswin,gate-clock"; + reg = <0x1e8>; + #clock-cells = <0>; + clocks = <&mux_syscfg_clk_root_2mux1>; + bit-index = <7>; + clock-output-names = "gate_timer_pclk_3"; + }; + gate_time_clk_0: time-clk-0-gate@1e8 { + compatible = "eswin,gate-clock"; + reg = <0x1e8>; + #clock-cells = <0>; + clocks = <&fixed_rate_clk_xtal_24m>; + bit-index = <0>; + clock-output-names = "gate_time_clk_0"; + }; + gate_time_clk_1: time-clk-1-gate@1e8 { + compatible = "eswin,gate-clock"; + reg = <0x1e8>; + #clock-cells = <0>; + clocks = <&fixed_rate_clk_xtal_24m>; + bit-index = <1>; + clock-output-names = "gate_time_clk_1"; + }; + gate_time_clk_2: time-clk-2-gate@1e8 { + compatible = "eswin,gate-clock"; + reg = <0x1e8>; + #clock-cells = <0>; + clocks = <&fixed_rate_clk_xtal_24m>; + bit-index = <2>; + clock-output-names = "gate_time_clk_2"; + }; + gate_time_clk_3: time-clk-3-gate@1e8 { + compatible = "eswin,gate-clock"; + reg = <0x1e8>; + #clock-cells = <0>; + clocks = <&fixed_rate_clk_xtal_24m>; + bit-index = <3>; + clock-output-names = "gate_time_clk_3"; + }; + gate_clk_rtc: clk-rtc-gate@1ec { + compatible = "eswin,gate-clock"; + reg = <0x1ec>; + #clock-cells = <0>; + clocks = <&divider_aon_rtc_div>; + bit-index = <1>; + clock-output-names = "gate_clk_rtc"; + }; + gate_clk_rtc_cfg: clk-rtc-cfg-gate@1ec { + compatible = "eswin,gate-clock"; + reg = <0x1ec>; + #clock-cells = <0>; + clocks = <&mux_syscfg_clk_root_2mux1>; + bit-index = <2>; + clock-output-names = "gate_clk_rtc_cfg"; + }; + gate_clk_pka_cfg: clk-pka-cfg-gate@1f0 { + compatible = "eswin,gate-clock"; + reg = <0x1f0>; + #clock-cells = <0>; + clocks = <&mux_syscfg_clk_root_2mux1>; + bit-index = <31>; + clock-output-names = "gate_clk_pka_cfg"; + }; + gate_clk_crypto: clk-crypto-gate@1f4 { + compatible = "eswin,gate-clock"; + reg = <0x1f4>; + #clock-cells = <0>; + clocks = <&divider_crypto_div>; + bit-index = <30>; + clock-output-names = "gate_clk_crypto"; + }; + gate_clk_spacc_cfg: clk-spacc-cfg-gate@1f4 { + compatible = "eswin,gate-clock"; + reg = <0x1f4>; + #clock-cells = <0>; + clocks = <&mux_syscfg_clk_root_2mux1>; + bit-index = <31>; + clock-output-names = "gate_clk_spacc_cfg"; + }; + gate_clk_trng_cfg: clk-trng-cfg-gate@1f8 { + compatible = "eswin,gate-clock"; + reg = <0x1f8>; + #clock-cells = <0>; + clocks = <&mux_syscfg_clk_root_2mux1>; + bit-index = <31>; + clock-output-names = "gate_clk_trng_cfg"; + }; + gate_clk_otp_cfg: clk-otp-cfg-gate@1fc { + compatible = "eswin,gate-clock"; + reg = <0x1fc>; + #clock-cells = <0>; + clocks = <&mux_syscfg_clk_root_2mux1>; + bit-index = <31>; + clock-output-names = "gate_clk_otp_cfg"; + }; + gate_i2c0_pclk: i2c0-pclk-gate@200 { + compatible = "eswin,gate-clock"; + reg = <0x200>; + #clock-cells = <0>; + clocks = <&mux_syscfg_clk_root_2mux1>; + bit-index = <7>; + clock-output-names = "gate_i2c0_pclk"; + }; + gate_i2c1_pclk: i2c1-pclk-gate@200 { + compatible = "eswin,gate-clock"; + reg = <0x200>; + #clock-cells = <0>; + clocks = <&mux_syscfg_clk_root_2mux1>; + bit-index = <8>; + clock-output-names = "gate_i2c1_pclk"; + }; + gate_i2c2_pclk: i2c2-pclk-gate@200 { + compatible = "eswin,gate-clock"; + reg = <0x200>; + #clock-cells = <0>; + clocks = <&mux_syscfg_clk_root_2mux1>; + bit-index = <9>; + clock-output-names = "gate_i2c2_pclk"; + }; + gate_i2c3_pclk: i2c3-pclk-gate@200 { + compatible = "eswin,gate-clock"; + reg = <0x200>; + #clock-cells = <0>; + clocks = <&mux_syscfg_clk_root_2mux1>; + bit-index = <10>; + clock-output-names = "gate_i2c3_pclk"; + }; + gate_i2c4_pclk: i2c4-pclk-gate@200 { + compatible = "eswin,gate-clock"; + reg = <0x200>; + #clock-cells = <0>; + clocks = <&mux_syscfg_clk_root_2mux1>; + bit-index = <11>; + clock-output-names = "gate_i2c4_pclk"; + }; + gate_i2c5_pclk: i2c5-pclk-gate@200 { + compatible = "eswin,gate-clock"; + reg = <0x200>; + #clock-cells = <0>; + clocks = <&mux_syscfg_clk_root_2mux1>; + bit-index = <12>; + clock-output-names = "gate_i2c5_pclk"; + }; + gate_i2c6_pclk: i2c6-pclk-gate@200 { + compatible = "eswin,gate-clock"; + reg = <0x200>; + #clock-cells = <0>; + clocks = <&mux_syscfg_clk_root_2mux1>; + bit-index = <13>; + clock-output-names = "gate_i2c6_pclk"; + }; + gate_i2c7_pclk: i2c7-pclk-gate@200 { + compatible = "eswin,gate-clock"; + reg = <0x200>; + #clock-cells = <0>; + clocks = <&mux_syscfg_clk_root_2mux1>; + bit-index = <14>; + clock-output-names = "gate_i2c7_pclk"; + }; + gate_i2c8_pclk: i2c8-pclk-gate@200 { + compatible = "eswin,gate-clock"; + reg = <0x200>; + #clock-cells = <0>; + clocks = <&mux_syscfg_clk_root_2mux1>; + bit-index = <15>; + clock-output-names = "gate_i2c8_pclk"; + }; + gate_i2c9_pclk: i2c9-pclk-gate@200 { + compatible = "eswin,gate-clock"; + reg = <0x200>; + #clock-cells = <0>; + clocks = <&mux_syscfg_clk_root_2mux1>; + bit-index = <16>; + clock-output-names = "gate_i2c9_pclk"; + }; + gate_lsp_fan_pclk: lsp-fan-pclk-gate@200 { + compatible = "eswin,gate-clock"; + reg = <0x200>; + #clock-cells = <0>; + clocks = <&mux_syscfg_clk_root_2mux1>; + bit-index = <0>; + clock-output-names = "gate_lsp_fan_pclk"; + }; + gate_lsp_pvt_pclk: lsp-pvt-pclk-gate@200 { + compatible = "eswin,gate-clock"; + reg = <0x200>; + #clock-cells = <0>; + clocks = <&mux_syscfg_clk_root_2mux1>; + bit-index = <1>; + clock-output-names = "gate_lsp_pvt_pclk"; + }; + gate_lsp_ssi0_pclk: lsp-ssi0-pclk-gate@200 { + compatible = "eswin,gate-clock"; + reg = <0x200>; + #clock-cells = <0>; + clocks = <&mux_syscfg_clk_root_2mux1>; + bit-index = <26>; + clock-output-names = "gate_lsp_ssi0_pclk"; + }; + gate_lsp_ssi1_pclk: lsp-ssi1-pclk-gate@200 { + compatible = "eswin,gate-clock"; + reg = <0x200>; + #clock-cells = <0>; + clocks = <&mux_syscfg_clk_root_2mux1>; + bit-index = <27>; + clock-output-names = "gate_lsp_ssi1_pclk"; + }; + gate_lsp_timer_pclk: lsp-timer-pclk-gate@200 { + compatible = "eswin,gate-clock"; + reg = <0x200>; + #clock-cells = <0>; + clocks = <&mux_syscfg_clk_root_2mux1>; + bit-index = <25>; + clock-output-names = "gate_lsp_timer_pclk"; + }; + gate_lspart0_pclk: lsp-uart0-pclk-gate@200 { + compatible = "eswin,gate-clock"; + reg = <0x200>; + #clock-cells = <0>; + clocks = <&mux_syscfg_clk_root_2mux1>; + bit-index = <17>; + clock-output-names = "gate_lsp_uart0_pclk"; + }; + gate_lsp_uart1_pclk: lsp-uart1-pclk-gate@200 { + compatible = "eswin,gate-clock"; + reg = <0x200>; + #clock-cells = <0>; + clocks = <&mux_syscfg_clk_root_2mux1>; + bit-index = <18>; + clock-output-names = "gate_lsp_uart1_pclk"; + }; + gate_lsp_uart2_pclk: lsp-uart2-pclk-gate@200 { + compatible = "eswin,gate-clock"; + reg = <0x200>; + #clock-cells = <0>; + clocks = <&mux_syscfg_clk_root_2mux1>; + bit-index = <19>; + clock-output-names = "gate_lsp_uart2_pclk"; + }; + gate_lsp_uart3_pclk: lsp-uart3-pclk-gate@200 { + compatible = "eswin,gate-clock"; + reg = <0x200>; + #clock-cells = <0>; + clocks = <&mux_syscfg_clk_root_2mux1>; + bit-index = <20>; + clock-output-names = "gate_lsp_uart3_pclk"; + }; + gate_lsp_uart4_pclk: lsp-uart4-pclk-gate@200 { + compatible = "eswin,gate-clock"; + reg = <0x200>; + #clock-cells = <0>; + clocks = <&mux_syscfg_clk_root_2mux1>; + bit-index = <21>; + clock-output-names = "gate_lsp_uart4_pclk"; + }; + gate_lsp_wdt0_pclk: lsp-wdt0-pclk-gate@200 { + compatible = "eswin,gate-clock"; + reg = <0x200>; + #clock-cells = <0>; + clocks = <&mux_syscfg_clk_root_2mux1>; + bit-index = <28>; + clock-output-names = "gate_lsp_wdt0_pclk"; + }; + gate_lsp_wdt1_pclk: lsp-wdt1-pclk-gate@200 { + compatible = "eswin,gate-clock"; + reg = <0x200>; + #clock-cells = <0>; + clocks = <&mux_syscfg_clk_root_2mux1>; + bit-index = <29>; + clock-output-names = "gate_lsp_wdt1_pclk"; + }; + gate_lsp_wdt2_pclk: lsp-wdt2-pclk-gate@200 { + compatible = "eswin,gate-clock"; + reg = <0x200>; + #clock-cells = <0>; + clocks = <&mux_syscfg_clk_root_2mux1>; + bit-index = <30>; + clock-output-names = "gate_lsp_wdt2_pclk"; + }; + gate_lsp_wdt3_pclk: lsp-wdt3-pclk-gate@200 { + compatible = "eswin,gate-clock"; + reg = <0x200>; + #clock-cells = <0>; + clocks = <&mux_syscfg_clk_root_2mux1>; + bit-index = <31>; + clock-output-names = "gate_lsp_wdt3_pclk"; + }; + gate_clk_mailbox_0: clk-mailbox-0-gate@204 { + compatible = "eswin,gate-clock"; + reg = <0x204>; + #clock-cells = <0>; + clocks = <&mux_syscfg_clk_root_2mux1>; + bit-index = <0>; + clock-output-names = "gate_clk_mailbox_0"; + }; + gate_clk_mailbox_1: clk-mailbox-1-gate@204 { + compatible = "eswin,gate-clock"; + reg = <0x204>; + #clock-cells = <0>; + clocks = <&mux_syscfg_clk_root_2mux1>; + bit-index = <1>; + clock-output-names = "gate_clk_mailbox_1"; + }; + gate_clk_mailbox_2: clk-mailbox-2-gate@204 { + compatible = "eswin,gate-clock"; + reg = <0x204>; + #clock-cells = <0>; + clocks = <&mux_syscfg_clk_root_2mux1>; + bit-index = <2>; + clock-output-names = "gate_clk_mailbox_2"; + }; + gate_clk_mailbox_3: clk-mailbox-3-gate@204 { + compatible = "eswin,gate-clock"; + reg = <0x204>; + #clock-cells = <0>; + clocks = <&mux_syscfg_clk_root_2mux1>; + bit-index = <3>; + clock-output-names = "gate_clk_mailbox_3"; + }; + gate_clk_mailbox_4: clk-mailbox-4-gate@204 { + compatible = "eswin,gate-clock"; + reg = <0x204>; + #clock-cells = <0>; + clocks = <&mux_syscfg_clk_root_2mux1>; + bit-index = <4>; + clock-output-names = "gate_clk_mailbox_4"; + }; + gate_clk_mailbox_5: clk-mailbox-5-gate@204 { + compatible = "eswin,gate-clock"; + reg = <0x204>; + #clock-cells = <0>; + clocks = <&mux_syscfg_clk_root_2mux1>; + bit-index = <5>; + clock-output-names = "gate_clk_mailbox_5"; + }; + gate_clk_mailbox_6: clk-mailbox-6-gate@204 { + compatible = "eswin,gate-clock"; + reg = <0x204>; + #clock-cells = <0>; + clocks = <&mux_syscfg_clk_root_2mux1>; + bit-index = <6>; + clock-output-names = "gate_clk_mailbox_6"; + }; + gate_clk_mailbox_7: clk-mailbox-7-gate@204 { + compatible = "eswin,gate-clock"; + reg = <0x204>; + #clock-cells = <0>; + clocks = <&mux_syscfg_clk_root_2mux1>; + bit-index = <7>; + clock-output-names = "gate_clk_mailbox_7"; + }; + gate_clk_mailbox_8: clk-mailbox-8-gate@204 { + compatible = "eswin,gate-clock"; + reg = <0x204>; + #clock-cells = <0>; + clocks = <&mux_syscfg_clk_root_2mux1>; + bit-index = <8>; + clock-output-names = "gate_clk_mailbox_8"; + }; + gate_clk_mailbox_9: clk-mailbox-9-gate@204 { + compatible = "eswin,gate-clock"; + reg = <0x204>; + #clock-cells = <0>; + clocks = <&mux_syscfg_clk_root_2mux1>; + bit-index = <9>; + clock-output-names = "gate_clk_mailbox_9"; + }; + gate_clk_mailbox_10: clk-mailbox-10-gate@204 { + compatible = "eswin,gate-clock"; + reg = <0x204>; + #clock-cells = <0>; + clocks = <&mux_syscfg_clk_root_2mux1>; + bit-index = <10>; + clock-output-names = "gate_clk_mailbox_10"; + }; + gate_clk_mailbox_11: clk-mailbox-11-gate@204 { + compatible = "eswin,gate-clock"; + reg = <0x204>; + #clock-cells = <0>; + clocks = <&mux_syscfg_clk_root_2mux1>; + bit-index = <11>; + clock-output-names = "gate_clk_mailbox_11"; + }; + gate_clk_mailbox_12: clk-mailbox-12-gate@204 { + compatible = "eswin,gate-clock"; + reg = <0x204>; + #clock-cells = <0>; + clocks = <&mux_syscfg_clk_root_2mux1>; + bit-index = <12>; + clock-output-names = "gate_clk_mailbox_12"; + }; + gate_clk_mailbox_13: clk-mailbox-13-gate@204 { + compatible = "eswin,gate-clock"; + reg = <0x204>; + #clock-cells = <0>; + clocks = <&mux_syscfg_clk_root_2mux1>; + bit-index = <13>; + clock-output-names = "gate_clk_mailbox_13"; + }; + gate_clk_mailbox_14: clk-mailbox-14-gate@204 { + compatible = "eswin,gate-clock"; + reg = <0x204>; + #clock-cells = <0>; + clocks = <&mux_syscfg_clk_root_2mux1>; + bit-index = <14>; + clock-output-names = "gate_clk_mailbox_14"; + }; + gate_clk_mailbox_15: clk-mailbox-15-gate@204 { + compatible = "eswin,gate-clock"; + reg = <0x204>; + #clock-cells = <0>; + clocks = <&mux_syscfg_clk_root_2mux1>; + bit-index = <15>; + clock-output-names = "gate_clk_mailbox_15"; + }; + gate_pvt0_clk: pvt0-clk-gate@204 { + compatible = "eswin,gate-clock"; + reg = <0x204>; + #clock-cells = <0>; + clocks = <&fixed_factor_pvt_div20>; + bit-index = <16>; + clock-output-names = "gate_pvt0_clk"; + }; + gate_pvt1_clk: pvt1-clk-gate@204 { + compatible = "eswin,gate-clock"; + reg = <0x204>; + #clock-cells = <0>; + clocks = <&fixed_factor_pvt_div20>; + bit-index = <17>; + clock-output-names = "gate_pvt1_clk"; + }; + gate_cpu_ext_src_core_0: cpu-ext-src-core-0-gate@208 { + compatible = "eswin,gate-clock"; + reg = <0x208>; + #clock-cells = <0>; + clocks = <&mux_cpu_root_3mux1>; + bit-index = <28>; + clock-output-names = "gate_cpu_ext_src_core_0"; + }; + gate_cpu_ext_src_core_1: cpu-ext-src-core-1-gate@208 { + compatible = "eswin,gate-clock"; + reg = <0x208>; + #clock-cells = <0>; + clocks = <&mux_cpu_root_3mux1>; + bit-index = <29>; + clock-output-names = "gate_cpu_ext_src_core_1"; + }; + gate_cpu_ext_src_core_2: cpu-ext-src-core-2-gate@208 { + compatible = "eswin,gate-clock"; + reg = <0x208>; + #clock-cells = <0>; + clocks = <&mux_cpu_root_3mux1>; + bit-index = <30>; + clock-output-names = "gate_cpu_ext_src_core_2"; + }; + gate_cpu_ext_src_core_3: cpu-ext-src-core-3-gate@208 { + compatible = "eswin,gate-clock"; + reg = <0x208>; + #clock-cells = <0>; + clocks = <&mux_cpu_root_3mux1>; + bit-index = <31>; + clock-output-names = "gate_cpu_ext_src_core_3"; + }; + gate_clk_cpu_trace_clk_0: clk-cpu-trace-clk-0-gate@208 { + compatible = "eswin,gate-clock"; + reg = <0x208>; + #clock-cells = <0>; + clocks = <&mux_cpu_root_3mux1>; + bit-index = <24>; + clock-output-names = "gate_clk_cpu_trace_clk_0"; + }; + gate_clk_cpu_trace_clk_1: clk-cpu-trace-clk-1-gate@208 { + compatible = "eswin,gate-clock"; + reg = <0x208>; + #clock-cells = <0>; + clocks = <&mux_cpu_root_3mux1>; + bit-index = <25>; + clock-output-names = "gate_clk_cpu_trace_clk_1"; + }; + gate_clk_cpu_trace_clk_2: clk-cpu-trace-clk-2-gate@208 { + compatible = "eswin,gate-clock"; + reg = <0x208>; + #clock-cells = <0>; + clocks = <&mux_cpu_root_3mux1>; + bit-index = <26>; + clock-output-names = "gate_clk_cpu_trace_clk_2"; + }; + gate_clk_cpu_trace_clk_3: clk-cpu-trace-clk-3-gate@208 { + compatible = "eswin,gate-clock"; + reg = <0x208>; + #clock-cells = <0>; + clocks = <&mux_cpu_root_3mux1>; + bit-index = <27>; + clock-output-names = "gate_clk_cpu_trace_clk_3"; + }; + gate_clk_cpu_trace_com_clk: clk-cpu-trace-com-clk-gate@208 { + compatible = "eswin,gate-clock"; + reg = <0x208>; + #clock-cells = <0>; + clocks = <&mux_cpu_aclk_2mux1>; + bit-index = <23>; + clock-output-names = "gate_clk_cpu_trace_com_clk"; + }; + gate_aon_i2c0_pclk: aon-i2c0-pclk-gate@210 { + compatible = "eswin,gate-clock"; + reg = <0x210>; + #clock-cells = <0>; + clocks = <&mux_syscfg_clk_root_2mux1>; + bit-index = <31>; + clock-output-names = "gate_aon_i2c0_pclk"; + }; + gate_aon_i2c1_pclk: aon-i2c1-pclk-gate@214 { + compatible = "eswin,gate-clock"; + reg = <0x214>; + #clock-cells = <0>; + clocks = <&mux_syscfg_clk_root_2mux1>; + bit-index = <31>; + clock-output-names = "gate_aon_i2c1_pclk"; + }; + }; +}; -- 2.17.1 From: Xuyang Dong <dongxuyang@eswincomputing.com> The link [1] provides the official documentation for the EIC7700. Section 3.2 covers the clock subsystem. [1] https://www.sifive.com/document-file/eic7700x-datasheet Updates: Changes in v8: - Added clock-tree link in cover-letter. - Updated YAML file - Added "Acked-by: Troy Mitchell <troy.mitchell@linux.dev>" for bindings. - Updated driver file - Changed Kconfig symbol type from bool to tristate to build this driver as module. - Updated MAINTAINERS file - Added entry "ESWIN EIC7700 CLOCK DRIVER". - Link to v7: https://lore.kernel.org/all/20251023071658.455-1-dongxuyang@eswincomputing.com/ Changes in v7: - Updated YAML file - Added "Acked-by: Conor Dooley <conor.dooley@microchip.com>" for bindings. - Updated driver file - Added description for clk of eswin_calc_pll(). - Added macro EIC7700_MUX_TBL to manage mux clock-tree. - Added eswin_clk_register_mux_tbl() to register mux clocks with discontinuous parent indexes. - Link to v6: https://lore.kernel.org/all/20251009092029.140-1-dongxuyang@eswincomputing.com/ Changes in v6: - Removed config option patch dependency from cover letter, because the patch was applied. - Updated YAML file - Added an oscillator as the clock input, named xtal24m. - Added clocks property. - Updated driver file - Replaced fixed_rate_clk_xtal_24m with xtal24m. - Dropped fixed_rate_clk_xtal_24m from driver. Because clock xtal24m was registered by fixed-clock as oscillator. - Link to v5: https://lore.kernel.org/all/20250923084637.1223-1-dongxuyang@eswincomputing.com/ Changes in v5: - Removed vendor prefix patch dependency from cover letter, because the patch was applied. - Updated YAML file - Placed the required after all properties. - Removed patternProperties. Also removed compatible of eswin,pll-clock, eswin,mux-clock, eswin,divider-clock and eswin,gate-clock as we have moved clock tree from DTS to Linux driver. - Removed the clock tree from DTS. Used clock-controller to manage all clock. Removed all child nodes in clock-controller. - Removed '#address-cells' and '#size-cells' properties, because the clock controller did not need to define these properties. - Removed eic7700-clocks.dtsi. - Added dt-bindings header for clock IDs. Because used the IDs to register clocks. - Updated driver file - Modified the commit for clock driver. Dropped indentation in commit. - Removed CLK_OF_DECLARE(). Used *clk_hw_register* to register clocks. Used devm_of_clk_add_hw_provider. - Dropped singletons. - Checked the value right after obtaining it. - Removed the definitions of macro frequency in clk.h like CLK_FREQ_24M. - Modified description of help in Kconfig. - Added COMPILE_TEST. Added COMMON_CLK_ESWIN for clk.o. And added "select COMMON_CLK_ESWIN" for clk-eic7700.c. Without COMMON_CLK_EIC7700, clk.c could not be compiled. - Used .determined_rate. - Added macro definitions of EIC7700_DIV, EIC7700_FIXED, EIC7700_FACTOR, EIC7700_MUX and EIC7700_PLL to manage clock tree. - Added clk-eic7700.h to place eic7700 SoC clock registers. - Removed refdiv_val and postdiv1_val from clk_pll_recalc_rate(). Because these values were unused. - Link to v4: https://lore.kernel.org/all/20250815093539.975-1-dongxuyang@eswincomputing.com/ Changes in v4: - Updated YAML file - Changed name from cpu-default-frequency to cpu-default-freq-hz. - Dropped $ref of cpu-default-frequency. - Added cpu-default-frequency for required. - Removed cpu-default-frequency in updated file, because there was no need to add cpu-default-frequency. - Moved DIVIDER to DIV. - Arranged the IDs in order. - Dropped EIC7700_NR_CLKS. - Removed dt-bindings eswin,eic7700-clock.h. Because IDs was not used, and used clock device nodes. - According to the updated driver codes, the YAML has been updated. - Updated driver file - Remove undocumented parameters "cpu_no_boost_1_6ghz" and "cpu-default-frequency". - Modified the comment and used the correct Linux coding style. - Removed codes of voltage, because it was not the clock driver. - Updated the formula of clock frequency calculation. Removed the logic that only used register selection. - Used CLK_OF_DECLARE() to register clocks. Registered pll-clock, mux-clock, divider-clock, and gate-clock in clk-eic7700.c. The specific implementation of clock registration was in clk.c. - Added eic7700-clocks.dtsi. - Moved device information to DTS. Put all clocks' node in the eic7700-clocks.dtsi. - Link to v3: https://lore.kernel.org/all/20250624103212.287-1-dongxuyang@eswincomputing.com/ Changes in v3: - Update example, drop child node and add '#clock-cells' to the parent node. - Change parent node from sys-crg to clock-controller for this yaml. - Drop "syscon", "simple-mfd" to clear warnings/errors by using "make dt_binding_check". And these are not necessary. - Add "cpu-default-frequency" definition in yaml for "undocumented ABI". - Drop Reviewed-by, this is misunderstanding. We have not received such an email. - Link to v2: https://lore.kernel.org/all/20250523090747.1830-1-dongxuyang@eswincomputing.com/ Changes in v2: - Update example, drop child node. - Clear warnings/errors for using "make dt_binding_check". - Change to the correct format. - Drop some non-stanard code. - Use dev_err_probe() in probe functions. - Link to v1: https://lore.kernel.org/all/20250514002233.187-1-dongxuyang@eswincomputing.com/ Xuyang Dong (3): dt-bindings: clock: eswin: Documentation for eic7700 SoC clock: eswin: Add eic7700 clock driver MAINTAINERS: Add entry for ESWIN EIC7700 clock driver .../bindings/clock/eswin,eic7700-clock.yaml | 46 + MAINTAINERS | 8 + drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/eswin/Kconfig | 15 + drivers/clk/eswin/Makefile | 8 + drivers/clk/eswin/clk-eic7700.c | 1033 +++++++++++++++++ drivers/clk/eswin/clk-eic7700.h | 122 ++ drivers/clk/eswin/clk.c | 481 ++++++++ drivers/clk/eswin/clk.h | 256 ++++ .../dt-bindings/clock/eswin,eic7700-clock.h | 280 +++++ 11 files changed, 2251 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/eswin,eic7700-clock.yaml create mode 100644 drivers/clk/eswin/Kconfig create mode 100644 drivers/clk/eswin/Makefile create mode 100644 drivers/clk/eswin/clk-eic7700.c create mode 100644 drivers/clk/eswin/clk-eic7700.h create mode 100644 drivers/clk/eswin/clk.c create mode 100644 drivers/clk/eswin/clk.h create mode 100644 include/dt-bindings/clock/eswin,eic7700-clock.h -- 2.43.0 From: Xuyang Dong <dongxuyang@eswincomputing.com> Add device tree binding documentation for the ESWIN eic7700 clock controller module. Signed-off-by: Yifeng Huang <huangyifeng@eswincomputing.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Troy Mitchell <troy.mitchell@linux.dev> Signed-off-by: Xuyang Dong <dongxuyang@eswincomputing.com> --- .../bindings/clock/eswin,eic7700-clock.yaml | 46 +++ .../dt-bindings/clock/eswin,eic7700-clock.h | 280 ++++++++++++++++++ 2 files changed, 326 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/eswin,eic7700-clock.yaml create mode 100644 include/dt-bindings/clock/eswin,eic7700-clock.h diff --git a/Documentation/devicetree/bindings/clock/eswin,eic7700-clock.yaml b/Documentation/devicetree/bindings/clock/eswin,eic7700-clock.yaml new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/Documentation/devicetree/bindings/clock/eswin,eic7700-clock.yaml @@ -XXX,XX +XXX,XX @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/eswin,eic7700-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Eswin EIC7700 SoC clock controller + +maintainers: + - Yifeng Huang <huangyifeng@eswincomputing.com> + - Xuyang Dong <dongxuyang@eswincomputing.com> + +description: + The clock controller generates and supplies clock to all the modules + for eic7700 SoC. + +properties: + compatible: + const: eswin,eic7700-clock + + reg: + maxItems: 1 + + clocks: + items: + - description: External 24MHz oscillator clock + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - clocks + - '#clock-cells' + +additionalProperties: false + +examples: + - | + clock-controller@51828000 { + compatible = "eswin,eic7700-clock"; + reg = <0x51828000 0x300>; + clocks = <&xtal24m>; + #clock-cells = <1>; + }; diff --git a/include/dt-bindings/clock/eswin,eic7700-clock.h b/include/dt-bindings/clock/eswin,eic7700-clock.h new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/include/dt-bindings/clock/eswin,eic7700-clock.h @@ -XXX,XX +XXX,XX @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright 2025, Beijing ESWIN Computing Technology Co., Ltd.. + * All rights reserved. + * + * Device Tree binding constants for EIC7700 clock controller. + * + * Authors: + * Yifeng Huang <huangyifeng@eswincomputing.com> + * Xuyang Dong <dongxuyang@eswincomputing.com> + */ + +#ifndef _DT_BINDINGS_ESWIN_EIC7700_CLOCK_H_ +#define _DT_BINDINGS_ESWIN_EIC7700_CLOCK_H_ + +#define EIC7700_CLK_XTAL_32K 0 +#define EIC7700_CLK_PLL_CPU 1 +#define EIC7700_CLK_SPLL0_FOUT1 2 +#define EIC7700_CLK_SPLL0_FOUT2 3 +#define EIC7700_CLK_SPLL0_FOUT3 4 +#define EIC7700_CLK_SPLL1_FOUT1 5 +#define EIC7700_CLK_SPLL1_FOUT2 6 +#define EIC7700_CLK_SPLL1_FOUT3 7 +#define EIC7700_CLK_SPLL2_FOUT1 8 +#define EIC7700_CLK_SPLL2_FOUT2 9 +#define EIC7700_CLK_SPLL2_FOUT3 10 +#define EIC7700_CLK_VPLL_FOUT1 11 +#define EIC7700_CLK_VPLL_FOUT2 12 +#define EIC7700_CLK_VPLL_FOUT3 13 +#define EIC7700_CLK_APLL_FOUT1 14 +#define EIC7700_CLK_APLL_FOUT2 15 +#define EIC7700_CLK_APLL_FOUT3 16 +#define EIC7700_CLK_EXT_MCLK 17 +#define EIC7700_CLK_LPDDR_REF_BAK 18 +#define EIC7700_CLK_MUX_CPU_ROOT_3MUX1_GFREE 19 +#define EIC7700_CLK_MUX_CPU_ACLK_2MUX1_GFREE 20 +#define EIC7700_CLK_MUX_DSP_ACLK_ROOT_2MUX1_GFREE 21 +#define EIC7700_CLK_MUX_D2D_ACLK_ROOT_2MUX1_GFREE 22 +#define EIC7700_CLK_MUX_MSHCORE_ROOT_3MUX1_0 23 +#define EIC7700_CLK_MUX_MSHCORE_ROOT_3MUX1_1 24 +#define EIC7700_CLK_MUX_MSHCORE_ROOT_3MUX1_2 25 +#define EIC7700_CLK_MUX_NPU_LLCLK_3MUX1_GFREE 26 +#define EIC7700_CLK_MUX_NPU_CORE_3MUX1_GFREE 27 +#define EIC7700_CLK_MUX_VI_ACLK_ROOT_2MUX1_GFREE 28 +#define EIC7700_CLK_MUX_VI_DVP_ROOT_2MUX1_GFREE 29 +#define EIC7700_CLK_MUX_VI_DIG_ISP_ROOT_2MUX1_GFREE 30 +#define EIC7700_CLK_MUX_VO_ACLK_ROOT_2MUX1_GFREE 31 +#define EIC7700_CLK_MUX_VO_PIXEL_ROOT_2MUX1 32 +#define EIC7700_CLK_MUX_VCDEC_ROOT_2MUX1_GFREE 33 +#define EIC7700_CLK_MUX_VCACLK_ROOT_2MUX1_GFREE 34 +#define EIC7700_CLK_MUX_SATA_PHY_2MUX1 35 +#define EIC7700_CLK_MUX_BOOTSPI_CLK_2MUX1_GFREE 36 +#define EIC7700_CLK_MUX_SCPU_CORE_CLK_2MUX1_GFREE 37 +#define EIC7700_CLK_MUX_LPCPU_CORE_CLK_2MUX1_GFREE 38 +#define EIC7700_CLK_MUX_VO_MCLK_2MUX_EXT_MCLK 39 +#define EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE 40 +#define EIC7700_CLK_MUX_AONDMA_AXI2MUX1_GFREE 41 +#define EIC7700_CLK_MUX_RMII_REF_2MUX 42 +#define EIC7700_CLK_MUX_ETH_CORE_2MUX1 43 +#define EIC7700_CLK_MUX_VI_DW_ROOT_2MUX1 44 +#define EIC7700_CLK_MUX_NPU_E31_3MUX1_GFREE 45 +#define EIC7700_CLK_MUX_DDR_ACLK_ROOT_2MUX1_GFREE 46 +#define EIC7700_CLK_DIV_SYS_CFG_DYNM 47 +#define EIC7700_CLK_DIV_NOC_NSP_DYNM 48 +#define EIC7700_CLK_DIV_BOOTSPI_DYNM 49 +#define EIC7700_CLK_DIV_SCPU_CORE_DYNM 50 +#define EIC7700_CLK_DIV_LPCPU_CORE_DYNM 51 +#define EIC7700_CLK_DIV_GPU_ACLK_DYNM 52 +#define EIC7700_CLK_DIV_DSP_ACLK_DYNM 53 +#define EIC7700_CLK_DIV_D2D_ACLK_DYNM 54 +#define EIC7700_CLK_DIV_HSP_ACLK_DYNM 55 +#define EIC7700_CLK_DIV_ETH_TXCLK_DYNM_0 56 +#define EIC7700_CLK_DIV_ETH_TXCLK_DYNM_1 57 +#define EIC7700_CLK_DIV_MSHC_CORE_DYNM_0 58 +#define EIC7700_CLK_DIV_MSHC_CORE_DYNM_1 59 +#define EIC7700_CLK_DIV_MSHC_CORE_DYNM_2 60 +#define EIC7700_CLK_DIV_PCIE_ACLK_DYNM 61 +#define EIC7700_CLK_DIV_NPU_ACLK_DYNM 62 +#define EIC7700_CLK_DIV_NPU_LLC_SRC0_DYNM 63 +#define EIC7700_CLK_DIV_NPU_LLC_SRC1_DYNM 64 +#define EIC7700_CLK_DIV_NPU_CORECLK_DYNM 65 +#define EIC7700_CLK_DIV_VI_ACLK_DYNM 66 +#define EIC7700_CLK_DIV_VI_DVP_DYNM 67 +#define EIC7700_CLK_DIV_VI_DIG_ISP_DYNM 68 +#define EIC7700_CLK_DIV_VI_SHUTTER_DYNM_0 69 +#define EIC7700_CLK_DIV_VI_SHUTTER_DYNM_1 70 +#define EIC7700_CLK_DIV_VI_SHUTTER_DYNM_2 71 +#define EIC7700_CLK_DIV_VI_SHUTTER_DYNM_3 72 +#define EIC7700_CLK_DIV_VI_SHUTTER_DYNM_4 73 +#define EIC7700_CLK_DIV_VI_SHUTTER_DYNM_5 74 +#define EIC7700_CLK_DIV_VO_ACLK_DYNM 75 +#define EIC7700_CLK_DIV_IESMCLK_DYNM 76 +#define EIC7700_CLK_DIV_VO_PIXEL_DYNM 77 +#define EIC7700_CLK_DIV_VO_MCLK_DYNM 78 +#define EIC7700_CLK_DIV_VC_ACLK_DYNM 79 +#define EIC7700_CLK_DIV_JD_DYNM 80 +#define EIC7700_CLK_DIV_JE_DYNM 81 +#define EIC7700_CLK_DIV_VE_DYNM 82 +#define EIC7700_CLK_DIV_VD_DYNM 83 +#define EIC7700_CLK_DIV_G2D_DYNM 84 +#define EIC7700_CLK_DIV_AONDMA_AXI_DYNM 85 +#define EIC7700_CLK_DIV_CRYPTO_DYNM 86 +#define EIC7700_CLK_DIV_VI_DW_DYNM 87 +#define EIC7700_CLK_DIV_NPU_E31_DYNM 88 +#define EIC7700_CLK_DIV_SATA_PHY_REF_DYNM 89 +#define EIC7700_CLK_DIV_DSP_0_ACLK_DYNM 90 +#define EIC7700_CLK_DIV_DSP_1_ACLK_DYNM 91 +#define EIC7700_CLK_DIV_DSP_2_ACLK_DYNM 92 +#define EIC7700_CLK_DIV_DSP_3_ACLK_DYNM 93 +#define EIC7700_CLK_DIV_DDR_ACLK_DYNM 94 +#define EIC7700_CLK_DIV_AON_RTC_DYNM 95 +#define EIC7700_CLK_DIV_U84_RTC_TOGGLE_DYNM 96 +#define EIC7700_CLK_DIV_VO_CEC_DYNM 97 +#define EIC7700_CLK_GATE_CPU_EXT_SRC_CORE_CLK_0 98 +#define EIC7700_CLK_GATE_CPU_EXT_SRC_CORE_CLK_1 99 +#define EIC7700_CLK_GATE_CPU_EXT_SRC_CORE_CLK_2 100 +#define EIC7700_CLK_GATE_CPU_EXT_SRC_CORE_CLK_3 101 +#define EIC7700_CLK_GATE_CPU_TRACE_CLK_0 102 +#define EIC7700_CLK_GATE_CPU_TRACE_CLK_1 103 +#define EIC7700_CLK_GATE_CPU_TRACE_CLK_2 104 +#define EIC7700_CLK_GATE_CPU_TRACE_CLK_3 105 +#define EIC7700_CLK_GATE_CPU_TRACE_COM_CLK 106 +#define EIC7700_CLK_GATE_SPLL0_FOUT2 107 +#define EIC7700_CLK_GATE_NOC_NSP_CLK 108 +#define EIC7700_CLK_GATE_BOOTSPI 109 +#define EIC7700_CLK_GATE_BOOTSPI_CFG 110 +#define EIC7700_CLK_GATE_SCPU_CORE 111 +#define EIC7700_CLK_GATE_SCPU_BUS 112 +#define EIC7700_CLK_GATE_LPCPU_CORE 113 +#define EIC7700_CLK_GATE_LPCPU_BUS 114 +#define EIC7700_CLK_GATE_GPU_ACLK 115 +#define EIC7700_CLK_GATE_GPU_GRAY_CLK 116 +#define EIC7700_CLK_GATE_GPU_CFG_CLK 117 +#define EIC7700_CLK_GATE_DSPT_ACLK 118 +#define EIC7700_CLK_GATE_DSPT_CFG_CLK 119 +#define EIC7700_CLK_GATE_D2D_ACLK 120 +#define EIC7700_CLK_GATE_D2D_CFG_CLK 121 +#define EIC7700_CLK_GATE_TCU_ACLK 122 +#define EIC7700_CLK_GATE_TCU_CFG_CLK 123 +#define EIC7700_CLK_GATE_DDRT_CFG_CLK 124 +#define EIC7700_CLK_GATE_DDRT0_P0_ACLK 125 +#define EIC7700_CLK_GATE_DDRT0_P1_ACLK 126 +#define EIC7700_CLK_GATE_DDRT0_P2_ACLK 127 +#define EIC7700_CLK_GATE_DDRT0_P3_ACLK 128 +#define EIC7700_CLK_GATE_DDRT0_P4_ACLK 129 +#define EIC7700_CLK_GATE_DDRT1_P0_ACLK 130 +#define EIC7700_CLK_GATE_DDRT1_P1_ACLK 131 +#define EIC7700_CLK_GATE_DDRT1_P2_ACLK 132 +#define EIC7700_CLK_GATE_DDRT1_P3_ACLK 133 +#define EIC7700_CLK_GATE_DDRT1_P4_ACLK 134 +#define EIC7700_CLK_GATE_TIMER_CLK_0 135 +#define EIC7700_CLK_GATE_TIMER_CLK_1 136 +#define EIC7700_CLK_GATE_TIMER_CLK_2 137 +#define EIC7700_CLK_GATE_TIMER_CLK_3 138 +#define EIC7700_CLK_GATE_TIMER_PCLK_0 139 +#define EIC7700_CLK_GATE_TIMER_PCLK_1 140 +#define EIC7700_CLK_GATE_TIMER_PCLK_2 141 +#define EIC7700_CLK_GATE_TIMER_PCLK_3 142 +#define EIC7700_CLK_GATE_TIMER3_CLK8 143 +#define EIC7700_CLK_GATE_PCIET_ACLK 144 +#define EIC7700_CLK_GATE_PCIET_CFG_CLK 145 +#define EIC7700_CLK_GATE_PCIET_CR_CLK 146 +#define EIC7700_CLK_GATE_PCIET_AUX_CLK 147 +#define EIC7700_CLK_GATE_NPU_ACLK 148 +#define EIC7700_CLK_GATE_NPU_CFG_CLK 149 +#define EIC7700_CLK_GATE_NPU_LLC_ACLK 150 +#define EIC7700_CLK_GATE_NPU_CLK 151 +#define EIC7700_CLK_GATE_NPU_E31_CLK 152 +#define EIC7700_CLK_GATE_VI_ACLK 153 +#define EIC7700_CLK_GATE_VI_DVP_CLK 154 +#define EIC7700_CLK_GATE_VI_CFG_CLK 155 +#define EIC7700_CLK_GATE_VI_DIG_DW_CLK 156 +#define EIC7700_CLK_GATE_VI_DIG_ISP_CLK 157 +#define EIC7700_CLK_GATE_VI_SHUTTER_0 158 +#define EIC7700_CLK_GATE_VI_SHUTTER_1 159 +#define EIC7700_CLK_GATE_VI_SHUTTER_2 160 +#define EIC7700_CLK_GATE_VI_SHUTTER_3 161 +#define EIC7700_CLK_GATE_VI_SHUTTER_4 162 +#define EIC7700_CLK_GATE_VI_SHUTTER_5 163 +#define EIC7700_CLK_GATE_VI_PHY_TXCLKESC 164 +#define EIC7700_CLK_GATE_VI_PHY_CFG 165 +#define EIC7700_CLK_GATE_VO_ACLK 166 +#define EIC7700_CLK_GATE_VO_CFG_CLK 167 +#define EIC7700_CLK_GATE_VO_HDMI_IESMCLK 168 +#define EIC7700_CLK_GATE_VO_PIXEL_CLK 169 +#define EIC7700_CLK_GATE_VO_I2S_MCLK 170 +#define EIC7700_CLK_GATE_HSP_CFG_CLK 171 +#define EIC7700_CLK_GATE_VC_ACLK 172 +#define EIC7700_CLK_GATE_VC_CFG_CLK 173 +#define EIC7700_CLK_GATE_VC_JE_CLK 174 +#define EIC7700_CLK_GATE_VC_JD_CLK 175 +#define EIC7700_CLK_GATE_VC_VE_CLK 176 +#define EIC7700_CLK_GATE_VC_VD_CLK 177 +#define EIC7700_CLK_GATE_G2D_CFG_CLK 178 +#define EIC7700_CLK_GATE_G2D_CLK 179 +#define EIC7700_CLK_GATE_G2D_ACLK 180 +#define EIC7700_CLK_GATE_AONDMA_CFG 181 +#define EIC7700_CLK_GATE_AONDMA_ACLK 182 +#define EIC7700_CLK_GATE_AON_ACLK 183 +#define EIC7700_CLK_GATE_HSP_SATA_RBC_CLK 184 +#define EIC7700_CLK_GATE_VO_CR_CLK 185 +#define EIC7700_CLK_GATE_HSP_ACLK 186 +#define EIC7700_CLK_GATE_HSP_SATA_OOB_CLK 187 +#define EIC7700_CLK_GATE_RTC_CFG 188 +#define EIC7700_CLK_GATE_RTC 189 +#define EIC7700_CLK_GATE_HSP_MSHC0_CORE_CLK 190 +#define EIC7700_CLK_GATE_HSP_MSHC1_CORE_CLK 191 +#define EIC7700_CLK_GATE_HSP_MSHC2_CORE_CLK 192 +#define EIC7700_CLK_GATE_HSP_ETH0_CORE_CLK 193 +#define EIC7700_CLK_GATE_HSP_ETH1_CORE_CLK 194 +#define EIC7700_CLK_GATE_HSP_RMII_REF_0 195 +#define EIC7700_CLK_GATE_HSP_RMII_REF_1 196 +#define EIC7700_CLK_GATE_PKA_CFG 197 +#define EIC7700_CLK_GATE_SPACC_CFG 198 +#define EIC7700_CLK_GATE_CRYPTO 199 +#define EIC7700_CLK_GATE_TRNG_CFG 200 +#define EIC7700_CLK_GATE_OTP_CFG 201 +#define EIC7700_CLK_GATE_MAILBOX_0 202 +#define EIC7700_CLK_GATE_MAILBOX_1 203 +#define EIC7700_CLK_GATE_MAILBOX_2 204 +#define EIC7700_CLK_GATE_MAILBOX_3 205 +#define EIC7700_CLK_GATE_MAILBOX_4 206 +#define EIC7700_CLK_GATE_MAILBOX_5 207 +#define EIC7700_CLK_GATE_MAILBOX_6 208 +#define EIC7700_CLK_GATE_MAILBOX_7 209 +#define EIC7700_CLK_GATE_MAILBOX_8 210 +#define EIC7700_CLK_GATE_MAILBOX_9 211 +#define EIC7700_CLK_GATE_MAILBOX_10 212 +#define EIC7700_CLK_GATE_MAILBOX_11 213 +#define EIC7700_CLK_GATE_MAILBOX_12 214 +#define EIC7700_CLK_GATE_MAILBOX_13 215 +#define EIC7700_CLK_GATE_MAILBOX_14 216 +#define EIC7700_CLK_GATE_MAILBOX_15 217 +#define EIC7700_CLK_GATE_LSP_I2C0_PCLK 218 +#define EIC7700_CLK_GATE_LSP_I2C1_PCLK 219 +#define EIC7700_CLK_GATE_LSP_I2C2_PCLK 220 +#define EIC7700_CLK_GATE_LSP_I2C3_PCLK 221 +#define EIC7700_CLK_GATE_LSP_I2C4_PCLK 222 +#define EIC7700_CLK_GATE_LSP_I2C5_PCLK 223 +#define EIC7700_CLK_GATE_LSP_I2C6_PCLK 224 +#define EIC7700_CLK_GATE_LSP_I2C7_PCLK 225 +#define EIC7700_CLK_GATE_LSP_I2C8_PCLK 226 +#define EIC7700_CLK_GATE_LSP_I2C9_PCLK 227 +#define EIC7700_CLK_GATE_LSP_WDT0_PCLK 228 +#define EIC7700_CLK_GATE_LSP_WDT1_PCLK 229 +#define EIC7700_CLK_GATE_LSP_WDT2_PCLK 230 +#define EIC7700_CLK_GATE_LSP_WDT3_PCLK 231 +#define EIC7700_CLK_GATE_LSP_SSI0_PCLK 232 +#define EIC7700_CLK_GATE_LSP_SSI1_PCLK 233 +#define EIC7700_CLK_GATE_LSP_PVT_PCLK 234 +#define EIC7700_CLK_GATE_AON_I2C0_PCLK 235 +#define EIC7700_CLK_GATE_AON_I2C1_PCLK 236 +#define EIC7700_CLK_GATE_LSP_UART0_PCLK 237 +#define EIC7700_CLK_GATE_LSP_UART1_PCLK 238 +#define EIC7700_CLK_GATE_LSP_UART2_PCLK 239 +#define EIC7700_CLK_GATE_LSP_UART3_PCLK 240 +#define EIC7700_CLK_GATE_LSP_UART4_PCLK 241 +#define EIC7700_CLK_GATE_LSP_TIMER_PCLK 242 +#define EIC7700_CLK_GATE_LSP_FAN_PCLK 243 +#define EIC7700_CLK_GATE_LSP_PVT0_CLK 244 +#define EIC7700_CLK_GATE_LSP_PVT1_CLK 245 +#define EIC7700_CLK_GATE_VC_JE_PCLK 246 +#define EIC7700_CLK_GATE_VC_JD_PCLK 247 +#define EIC7700_CLK_GATE_VC_VE_PCLK 248 +#define EIC7700_CLK_GATE_VC_VD_PCLK 249 +#define EIC7700_CLK_GATE_VC_MON_PCLK 250 +#define EIC7700_CLK_GATE_HSP_DMA0_CLK 251 +#define EIC7700_CLK_GATE_HSP_DMA0_CLK_TEST 252 +#define EIC7700_CLK_FIXED_FACTOR_CPU_DIV2 253 +#define EIC7700_CLK_FIXED_FACTOR_CLK_1M_DIV24 254 +#define EIC7700_CLK_FIXED_FACTOR_MIPI_TXESC_DIV10 255 +#define EIC7700_CLK_FIXED_FACTOR_U84_CORE_LP_DIV2 256 +#define EIC7700_CLK_FIXED_FACTOR_SCPU_BUS_DIV2 257 +#define EIC7700_CLK_FIXED_FACTOR_LPCPU_BUS_DIV2 258 +#define EIC7700_CLK_FIXED_FACTOR_PCIE_CR_DIV2 259 +#define EIC7700_CLK_FIXED_FACTOR_PCIE_AUX_DIV4 260 +#define EIC7700_CLK_FIXED_FACTOR_PVT_DIV20 261 +#define EIC7700_CLK_FIXED_FACTOR_HSP_RMII_REF_DIV6 262 + +#endif /* _DT_BINDINGS_ESWIN_EIC7700_CLOCK_H_ */ -- 2.43.0 From: Xuyang Dong <dongxuyang@eswincomputing.com> Add clock drivers for the EIC7700 SoC. The clock controller on the ESWIN EIC7700 provides various clocks to different IP blocks within the SoC. Signed-off-by: Yifeng Huang <huangyifeng@eswincomputing.com> Signed-off-by: Xuyang Dong <dongxuyang@eswincomputing.com> --- drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/eswin/Kconfig | 15 + drivers/clk/eswin/Makefile | 8 + drivers/clk/eswin/clk-eic7700.c | 1033 +++++++++++++++++++++++++++++++ drivers/clk/eswin/clk-eic7700.h | 122 ++++ drivers/clk/eswin/clk.c | 481 ++++++++++++++ drivers/clk/eswin/clk.h | 256 ++++++++ 8 files changed, 1917 insertions(+) create mode 100644 drivers/clk/eswin/Kconfig create mode 100644 drivers/clk/eswin/Makefile create mode 100644 drivers/clk/eswin/clk-eic7700.c create mode 100644 drivers/clk/eswin/clk-eic7700.h create mode 100644 drivers/clk/eswin/clk.c create mode 100644 drivers/clk/eswin/clk.h diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index XXXXXXX..XXXXXXX 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -XXX,XX +XXX,XX @@ source "drivers/clk/actions/Kconfig" source "drivers/clk/analogbits/Kconfig" source "drivers/clk/baikal-t1/Kconfig" source "drivers/clk/bcm/Kconfig" +source "drivers/clk/eswin/Kconfig" source "drivers/clk/hisilicon/Kconfig" source "drivers/clk/imgtec/Kconfig" source "drivers/clk/imx/Kconfig" diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index XXXXXXX..XXXXXXX 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_CLK_BAIKAL_T1) += baikal-t1/ obj-y += bcm/ obj-$(CONFIG_ARCH_BERLIN) += berlin/ obj-$(CONFIG_ARCH_DAVINCI) += davinci/ +obj-$(CONFIG_ARCH_ESWIN) += eswin/ obj-$(CONFIG_ARCH_HISI) += hisilicon/ obj-y += imgtec/ obj-y += imx/ diff --git a/drivers/clk/eswin/Kconfig b/drivers/clk/eswin/Kconfig new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/drivers/clk/eswin/Kconfig @@ -XXX,XX +XXX,XX @@ +# SPDX-License-Identifier: GPL-2.0 + +config COMMON_CLK_ESWIN + bool + +config COMMON_CLK_EIC7700 + tristate "EIC7700 Clock Driver" + depends on ARCH_ESWIN || COMPILE_TEST + select COMMON_CLK_ESWIN + default ARCH_ESWIN + help + This driver provides support for clock controller on ESWIN EIC7700 + SoC. The clock controller can generates and supplies clock to various + peripherals within the SoC. + Say yes here to support the clock controller on the EIC7700 SoC. diff --git a/drivers/clk/eswin/Makefile b/drivers/clk/eswin/Makefile new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/drivers/clk/eswin/Makefile @@ -XXX,XX +XXX,XX @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Eswin Clock specific Makefile +# + +obj-$(CONFIG_COMMON_CLK_ESWIN) += clk.o + +obj-$(CONFIG_COMMON_CLK_EIC7700) += clk-eic7700.o diff --git a/drivers/clk/eswin/clk-eic7700.c b/drivers/clk/eswin/clk-eic7700.c new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/drivers/clk/eswin/clk-eic7700.c @@ -XXX,XX +XXX,XX @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2025, Beijing ESWIN Computing Technology Co., Ltd.. + * All rights reserved. + * + * ESWIN EIC7700 Clk Provider Driver + * + * Authors: + * Yifeng Huang <huangyifeng@eswincomputing.com> + * Xuyang Dong <dongxuyang@eswincomputing.com> + */ + +#include <linux/clk.h> +#include <linux/clk-provider.h> +#include <linux/kernel.h> + +#include <dt-bindings/clock/eswin,eic7700-clock.h> + +#include "clk.h" +#include "clk-eic7700.h" + +#define EIC7700_NR_CLKS (EIC7700_CLK_FIXED_FACTOR_HSP_RMII_REF_DIV6 + 1) + +/* clock parent list */ +PNAME(mux_cpu_root_3mux1_gfree_p) = { "clk_pll_cpu", + "fixed_factor_u84_core_lp_div2", + "xtal24m" }; +PNAME(mux_cpu_aclk_2mux1_gfree_p) = { "fixed_factor_cpu_div2", + "mux_cpu_root_3mux1_gfree" }; +PNAME(dsp_aclk_root_2mux1_gfree_mux_p) = { "fixed_rate_clk_spll2_fout1", + "fixed_rate_clk_spll0_fout1" }; +PNAME(d2d_aclk_root_2mux1_gfree_mux_p) = { "fixed_rate_clk_spll2_fout1", + "fixed_rate_clk_spll0_fout1" }; +PNAME(ddr_aclk_root_2mux1_gfree_mux_p) = { "fixed_rate_clk_spll2_fout1", + "fixed_rate_clk_spll0_fout1" }; +PNAME(mshcore_root_3mux1_0_mux_p) = { "fixed_rate_clk_spll0_fout3", + "fixed_rate_clk_spll2_fout3" }; +PNAME(mshcore_root_3mux1_1_mux_p) = { "fixed_rate_clk_spll0_fout3", + "fixed_rate_clk_spll2_fout3" }; +PNAME(mshcore_root_3mux1_2_mux_p) = { "fixed_rate_clk_spll0_fout3", + "fixed_rate_clk_spll2_fout3" }; +PNAME(npu_llclk_3mux1_gfree_mux_p) = { "divider_npu_llc_src0_div_dynm", + "divider_npu_llc_src1_div_dynm", + "fixed_rate_clk_vpll_fout1" }; +PNAME(npu_core_3mux1_gfree_mux_p) = { "fixed_rate_clk_spll1_fout1", + "fixed_rate_clk_vpll_fout1", + "fixed_rate_clk_spll2_fout2" }; +PNAME(npu_e31_3mux1_gfree_mux_p) = { "fixed_rate_clk_spll1_fout1", + "fixed_rate_clk_vpll_fout1", + "fixed_rate_clk_spll2_fout2" }; +PNAME(vi_aclk_root_2mux1_gfree_mux_p) = { "fixed_rate_clk_spll0_fout1", + "fixed_rate_clk_spll2_fout1" }; +PNAME(mux_vi_dw_root_2mux1_p) = { "fixed_rate_clk_vpll_fout1", + "fixed_rate_clk_spll0_fout1" }; +PNAME(mux_vi_dvp_root_2mux1_gfree_p) = { "fixed_rate_clk_vpll_fout1", + "fixed_rate_clk_spll0_fout1" }; +PNAME(mux_vi_dig_isp_root_2mux1_gfree_p) = { "fixed_rate_clk_vpll_fout1", + "fixed_rate_clk_spll0_fout1" }; +PNAME(mux_vo_aclk_root_2mux1_gfree_p) = { "fixed_rate_clk_spll0_fout1", + "fixed_rate_clk_spll2_fout1" }; +PNAME(mux_vo_pixel_root_2mux1_p) = { "fixed_rate_clk_vpll_fout1", + "fixed_rate_clk_spll2_fout2" }; +PNAME(mux_vcdec_root_2mux1_gfree_p) = { "fixed_rate_clk_spll0_fout1", + "fixed_rate_clk_spll2_fout1" }; +PNAME(mux_vcaclk_root_2mux1_gfree_p) = { "fixed_rate_clk_spll0_fout1", + "fixed_rate_clk_spll2_fout1" }; +PNAME(mux_syscfg_clk_root_2mux1_gfree_p) = { "divider_sys_cfg_div_dynm", + "xtal24m" }; +PNAME(mux_bootspi_clk_2mux1_gfree_p) = { "divider_bootspi_div_dynm", + "xtal24m" }; +PNAME(mux_scpu_core_clk_2mux1_gfree_p) = { "divider_scpu_core_div_dynm", + "xtal24m" }; +PNAME(mux_lpcpu_core_clk_2mux1_gfree_p) = { "divider_lpcpu_core_div_dynm", + "xtal24m" }; +PNAME(mux_vo_mclk_2mux_ext_mclk_p) = { "divider_vo_mclk_div_dynm", + "fixed_rate_ext_mclk" }; +PNAME(mux_aondma_axi2mux1_gfree_p) = { "divider_aondma_axi_div_dynm", + "xtal24m" }; +PNAME(mux_rmii_ref_2mux1_p) = { "fixed_factor_hsp_rmii_ref_div6", + "fixed_rate_lpddr_ref_bak" }; +PNAME(mux_eth_core_2mux1_p) = { "fixed_rate_clk_spll1_fout3", + "fixed_rate_lpddr_ref_bak" }; +PNAME(mux_sata_phy_2mux1_p) = { "divider_sata_phy_ref_div_dynm", + "fixed_rate_lpddr_ref_bak" }; + +/* fixed rate clocks */ +static struct eswin_fixed_rate_clock eic7700_fixed_rate_clks[] = { + EIC7700_FIXED(EIC7700_CLK_XTAL_32K, "fixed_rate_clk_xtal_32k", NULL, 0, + 32768), + EIC7700_FIXED(EIC7700_CLK_SPLL0_FOUT1, "fixed_rate_clk_spll0_fout1", + NULL, 0, 1600000000), + EIC7700_FIXED(EIC7700_CLK_SPLL0_FOUT2, "fixed_rate_clk_spll0_fout2", + NULL, 0, 800000000), + EIC7700_FIXED(EIC7700_CLK_SPLL0_FOUT3, "fixed_rate_clk_spll0_fout3", + NULL, 0, 400000000), + EIC7700_FIXED(EIC7700_CLK_SPLL1_FOUT1, "fixed_rate_clk_spll1_fout1", + NULL, 0, 1500000000), + EIC7700_FIXED(EIC7700_CLK_SPLL1_FOUT2, "fixed_rate_clk_spll1_fout2", + NULL, 0, 300000000), + EIC7700_FIXED(EIC7700_CLK_SPLL1_FOUT3, "fixed_rate_clk_spll1_fout3", + NULL, 0, 250000000), + EIC7700_FIXED(EIC7700_CLK_SPLL2_FOUT1, "fixed_rate_clk_spll2_fout1", + NULL, 0, 2080000000), + EIC7700_FIXED(EIC7700_CLK_SPLL2_FOUT2, "fixed_rate_clk_spll2_fout2", + NULL, 0, 1040000000), + EIC7700_FIXED(EIC7700_CLK_SPLL2_FOUT3, "fixed_rate_clk_spll2_fout3", + NULL, 0, 416000000), + EIC7700_FIXED(EIC7700_CLK_VPLL_FOUT1, "fixed_rate_clk_vpll_fout1", + NULL, 0, 1188000000), + EIC7700_FIXED(EIC7700_CLK_VPLL_FOUT2, "fixed_rate_clk_vpll_fout2", + NULL, 0, 594000000), + EIC7700_FIXED(EIC7700_CLK_VPLL_FOUT3, "fixed_rate_clk_vpll_fout3", + NULL, 0, 49500000), + EIC7700_FIXED(EIC7700_CLK_APLL_FOUT2, "fixed_rate_clk_apll_fout2", + NULL, 0, 0), + EIC7700_FIXED(EIC7700_CLK_APLL_FOUT3, "fixed_rate_clk_apll_fout3", + NULL, 0, 0), + EIC7700_FIXED(EIC7700_CLK_EXT_MCLK, "fixed_rate_ext_mclk", NULL, 0, 0), + EIC7700_FIXED(EIC7700_CLK_LPDDR_REF_BAK, "fixed_rate_lpddr_ref_bak", + NULL, 0, 50000000), +}; + +/* pll clocks */ +static struct eswin_pll_clock eic7700_pll_clks[] = { + EIC7700_PLL(EIC7700_CLK_APLL_FOUT1, "clk_apll_fout1", NULL, + EIC7700_REG_OFFSET_APLL_CFG_0, 0, 1, 12, 6, 20, 12, + EIC7700_REG_OFFSET_APLL_CFG_1, 4, 24, + EIC7700_REG_OFFSET_APLL_CFG_2, 1, 3, 16, 3, + EIC7700_REG_OFFSET_PLL_STATUS, 4, 1), + EIC7700_PLL(EIC7700_CLK_PLL_CPU, "clk_pll_cpu", NULL, + EIC7700_REG_OFFSET_MCPUT_PLL_CFG_0, 0, 1, 12, 6, 20, 12, + EIC7700_REG_OFFSET_MCPUT_PLL_CFG_1, 4, 24, + EIC7700_REG_OFFSET_MCPUT_PLL_CFG_2, 1, 3, 16, 3, + EIC7700_REG_OFFSET_PLL_STATUS, 5, 1), +}; + +/* fixed factor clocks */ +static struct eswin_fixed_factor_clock eic7700_fixed_factor_clks[] = { + EIC7700_FACTOR(EIC7700_CLK_FIXED_FACTOR_CPU_DIV2, + "fixed_factor_cpu_div2", "mux_cpu_root_3mux1_gfree", 1, + 2, 0), + EIC7700_FACTOR(EIC7700_CLK_FIXED_FACTOR_CLK_1M_DIV24, + "fixed_factor_clk_1m_div24", "xtal24m", 1, 24, 0), + EIC7700_FACTOR(EIC7700_CLK_FIXED_FACTOR_MIPI_TXESC_DIV10, + "fixed_factor_mipi_txesc_div10", + "mux_syscfg_clk_root_2mux1_gfree", 1, 10, 0), + EIC7700_FACTOR(EIC7700_CLK_FIXED_FACTOR_U84_CORE_LP_DIV2, + "fixed_factor_u84_core_lp_div2", "gate_clk_spll0_fout2", + 1, 2, 0), + EIC7700_FACTOR(EIC7700_CLK_FIXED_FACTOR_SCPU_BUS_DIV2, + "fixed_factor_scpu_bus_div2", + "mux_scpu_core_clk_2mux1_gfree", 1, 2, 0), + EIC7700_FACTOR(EIC7700_CLK_FIXED_FACTOR_LPCPU_BUS_DIV2, + "fixed_factor_lpcpu_bus_div2", + "mux_lpcpu_core_clk_2mux1_gfree", 1, 2, 0), + EIC7700_FACTOR(EIC7700_CLK_FIXED_FACTOR_PCIE_CR_DIV2, + "fixed_factor_pcie_cr_div2", + "mux_syscfg_clk_root_2mux1_gfree", 1, 2, 0), + EIC7700_FACTOR(EIC7700_CLK_FIXED_FACTOR_PCIE_AUX_DIV4, + "fixed_factor_pcie_aux_div4", + "mux_syscfg_clk_root_2mux1_gfree", 1, 4, 0), + EIC7700_FACTOR(EIC7700_CLK_FIXED_FACTOR_PVT_DIV20, + "fixed_factor_pvt_div20", "xtal24m", 1, 20, 0), + EIC7700_FACTOR(EIC7700_CLK_FIXED_FACTOR_HSP_RMII_REF_DIV6, + "fixed_factor_hsp_rmii_ref_div6", + "fixed_rate_clk_spll1_fout2", 1, 6, 0), +}; + +/* mux clocks */ +static struct eswin_mux_clock eic7700_mux_clks[] = { + EIC7700_MUX(EIC7700_CLK_MUX_CPU_ROOT_3MUX1_GFREE, + "mux_cpu_root_3mux1_gfree", mux_cpu_root_3mux1_gfree_p, + ARRAY_SIZE(mux_cpu_root_3mux1_gfree_p), + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_U84_CTRL, 0, 2, 0), + EIC7700_MUX(EIC7700_CLK_MUX_CPU_ACLK_2MUX1_GFREE, + "mux_cpu_aclk_2mux1_gfree", mux_cpu_aclk_2mux1_gfree_p, + ARRAY_SIZE(mux_cpu_aclk_2mux1_gfree_p), + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_U84_CTRL, 20, 1, 0), + EIC7700_MUX(EIC7700_CLK_MUX_DSP_ACLK_ROOT_2MUX1_GFREE, + "mux_dsp_aclk_root_2mux1_gfree", + dsp_aclk_root_2mux1_gfree_mux_p, + ARRAY_SIZE(dsp_aclk_root_2mux1_gfree_mux_p), + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_DSP_ACLK_CTRL, 0, 1, + 0), + EIC7700_MUX(EIC7700_CLK_MUX_D2D_ACLK_ROOT_2MUX1_GFREE, + "mux_d2d_aclk_root_2mux1_gfree", + d2d_aclk_root_2mux1_gfree_mux_p, + ARRAY_SIZE(d2d_aclk_root_2mux1_gfree_mux_p), + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_D2D_ACLK_CTRL, 0, + 1, 0), + EIC7700_MUX(EIC7700_CLK_MUX_DDR_ACLK_ROOT_2MUX1_GFREE, + "mux_ddr_aclk_root_2mux1_gfree", + ddr_aclk_root_2mux1_gfree_mux_p, + ARRAY_SIZE(ddr_aclk_root_2mux1_gfree_mux_p), + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_DDR_CTRL, 16, 1, 0), + EIC7700_MUX(EIC7700_CLK_MUX_MSHCORE_ROOT_3MUX1_0, + "mux_mshcore_root_3mux1_0", mshcore_root_3mux1_0_mux_p, + ARRAY_SIZE(mshcore_root_3mux1_0_mux_p), CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_MSHC0_CORE_CTRL, 0, 1, 0), + EIC7700_MUX(EIC7700_CLK_MUX_MSHCORE_ROOT_3MUX1_1, + "mux_mshcore_root_3mux1_1", mshcore_root_3mux1_1_mux_p, + ARRAY_SIZE(mshcore_root_3mux1_1_mux_p), CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_MSHC1_CORE_CTRL, 0, 1, 0), + EIC7700_MUX(EIC7700_CLK_MUX_MSHCORE_ROOT_3MUX1_2, + "mux_mshcore_root_3mux1_2", mshcore_root_3mux1_2_mux_p, + ARRAY_SIZE(mshcore_root_3mux1_2_mux_p), CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_MSHC2_CORE_CTRL, 0, 1, 0), + EIC7700_MUX(EIC7700_CLK_MUX_NPU_LLCLK_3MUX1_GFREE, + "mux_npu_llclk_3mux1_gfree", npu_llclk_3mux1_gfree_mux_p, + ARRAY_SIZE(npu_llclk_3mux1_gfree_mux_p), + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_NPU_LLC_CTRL, 0, 2, + 0), + EIC7700_MUX(EIC7700_CLK_MUX_NPU_CORE_3MUX1_GFREE, + "mux_npu_core_3mux1_gfree", npu_core_3mux1_gfree_mux_p, + ARRAY_SIZE(npu_core_3mux1_gfree_mux_p), CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_NPU_CORE_CTRL, 0, 2, 0), + EIC7700_MUX(EIC7700_CLK_MUX_NPU_E31_3MUX1_GFREE, + "mux_npu_e31_3mux1_gfree", npu_e31_3mux1_gfree_mux_p, + ARRAY_SIZE(npu_e31_3mux1_gfree_mux_p), CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_NPU_CORE_CTRL, 8, 2, 0), + EIC7700_MUX(EIC7700_CLK_MUX_VI_ACLK_ROOT_2MUX1_GFREE, + "mux_vi_aclk_root_2mux1_gfree", + vi_aclk_root_2mux1_gfree_mux_p, + ARRAY_SIZE(vi_aclk_root_2mux1_gfree_mux_p), + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VI_ACLK_CTRL, 0, 1, + 0), + EIC7700_MUX(EIC7700_CLK_MUX_VI_DW_ROOT_2MUX1, "mux_vi_dw_root_2mux1", + mux_vi_dw_root_2mux1_p, ARRAY_SIZE(mux_vi_dw_root_2mux1_p), + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VI_DWCLK_CTRL, 0, + 1, 0), + EIC7700_MUX(EIC7700_CLK_MUX_VI_DVP_ROOT_2MUX1_GFREE, + "mux_vi_dvp_root_2mux1_gfree", + mux_vi_dvp_root_2mux1_gfree_p, + ARRAY_SIZE(mux_vi_dvp_root_2mux1_gfree_p), + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VI_DVP_CTRL, 0, 1, + 0), + EIC7700_MUX(EIC7700_CLK_MUX_VI_DIG_ISP_ROOT_2MUX1_GFREE, + "mux_vi_dig_isp_root_2mux1_gfree", + mux_vi_dig_isp_root_2mux1_gfree_p, + ARRAY_SIZE(mux_vi_dig_isp_root_2mux1_gfree_p), + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VI_DIG_ISP_CTRL, 0, + 1, 0), + EIC7700_MUX(EIC7700_CLK_MUX_VO_ACLK_ROOT_2MUX1_GFREE, + "mux_vo_aclk_root_2mux1_gfree", + mux_vo_aclk_root_2mux1_gfree_p, + ARRAY_SIZE(mux_vo_aclk_root_2mux1_gfree_p), + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VO_ACLK_CTRL, 0, 1, + 0), + EIC7700_MUX(EIC7700_CLK_MUX_VO_PIXEL_ROOT_2MUX1, + "mux_vo_pixel_root_2mux1", mux_vo_pixel_root_2mux1_p, + ARRAY_SIZE(mux_vo_pixel_root_2mux1_p), CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_VO_PIXEL_CTRL, 0, 1, 0), + EIC7700_MUX(EIC7700_CLK_MUX_VCDEC_ROOT_2MUX1_GFREE, + "mux_vcdec_root_2mux1_gfree", mux_vcdec_root_2mux1_gfree_p, + ARRAY_SIZE(mux_vcdec_root_2mux1_gfree_p), + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VCDEC_ROOT_CTRL, 0, + 1, 0), + EIC7700_MUX(EIC7700_CLK_MUX_VCACLK_ROOT_2MUX1_GFREE, + "mux_vcaclk_root_2mux1_gfree", + mux_vcaclk_root_2mux1_gfree_p, + ARRAY_SIZE(mux_vcaclk_root_2mux1_gfree_p), + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VC_ACLK_CTRL, 0, 1, + 0), + EIC7700_MUX(EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, + "mux_syscfg_clk_root_2mux1_gfree", + mux_syscfg_clk_root_2mux1_gfree_p, + ARRAY_SIZE(mux_syscfg_clk_root_2mux1_gfree_p), + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_SYSCFG_CTRL, 0, 1, + 0), + EIC7700_MUX(EIC7700_CLK_MUX_BOOTSPI_CLK_2MUX1_GFREE, + "mux_bootspi_clk_2mux1_gfree", + mux_bootspi_clk_2mux1_gfree_p, + ARRAY_SIZE(mux_bootspi_clk_2mux1_gfree_p), + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_BOOTSPI_CTRL, 0, 1, + 0), + EIC7700_MUX(EIC7700_CLK_MUX_SCPU_CORE_CLK_2MUX1_GFREE, + "mux_scpu_core_clk_2mux1_gfree", + mux_scpu_core_clk_2mux1_gfree_p, + ARRAY_SIZE(mux_scpu_core_clk_2mux1_gfree_p), + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_SCPU_CORE_CTRL, 0, + 1, 0), + EIC7700_MUX(EIC7700_CLK_MUX_LPCPU_CORE_CLK_2MUX1_GFREE, + "mux_lpcpu_core_clk_2mux1_gfree", + mux_lpcpu_core_clk_2mux1_gfree_p, + ARRAY_SIZE(mux_lpcpu_core_clk_2mux1_gfree_p), + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LPCPU_CORE_CTRL, 0, + 1, 0), + EIC7700_MUX(EIC7700_CLK_MUX_VO_MCLK_2MUX_EXT_MCLK, + "mux_vo_mclk_2mux_ext_mclk", mux_vo_mclk_2mux_ext_mclk_p, + ARRAY_SIZE(mux_vo_mclk_2mux_ext_mclk_p), + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VO_MCLK_CTRL, 0, 1, + 0), + EIC7700_MUX(EIC7700_CLK_MUX_AONDMA_AXI2MUX1_GFREE, + "mux_aondma_axi2mux1_gfree", mux_aondma_axi2mux1_gfree_p, + ARRAY_SIZE(mux_aondma_axi2mux1_gfree_p), + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_AON_DMA_CTRL, 20, + 1, 0), + EIC7700_MUX(EIC7700_CLK_MUX_RMII_REF_2MUX, "mux_rmii_ref_2mux1", + mux_rmii_ref_2mux1_p, ARRAY_SIZE(mux_rmii_ref_2mux1_p), + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_ETH0_CTRL, 2, 1, 0), + EIC7700_MUX(EIC7700_CLK_MUX_ETH_CORE_2MUX1, "mux_eth_core_2mux1", + mux_eth_core_2mux1_p, ARRAY_SIZE(mux_eth_core_2mux1_p), + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_ETH0_CTRL, 1, 1, 0), + EIC7700_MUX(EIC7700_CLK_MUX_SATA_PHY_2MUX1, "mux_sata_phy_2mux1", + mux_sata_phy_2mux1_p, ARRAY_SIZE(mux_sata_phy_2mux1_p), + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_SATA_OOB_CTRL, 9, + 1, 0), +}; + +/* divider clocks */ +static struct eswin_divider_clock eic7700_div_clks[] = { + EIC7700_DIV(EIC7700_CLK_DIV_SYS_CFG_DYNM, "divider_sys_cfg_div_dynm", + "fixed_rate_clk_spll0_fout3", 0, + EIC7700_REG_OFFSET_SYSCFG_CTRL, 4, 3, + CLK_DIVIDER_ONE_BASED), + EIC7700_DIV(EIC7700_CLK_DIV_NOC_NSP_DYNM, "divider_noc_nsp_div_dynm", + "fixed_rate_clk_spll2_fout1", 0, + EIC7700_REG_OFFSET_NOC_CTRL, 0, 3, CLK_DIVIDER_ONE_BASED), + EIC7700_DIV(EIC7700_CLK_DIV_BOOTSPI_DYNM, "divider_bootspi_div_dynm", + "gate_clk_spll0_fout2", 0, EIC7700_REG_OFFSET_BOOTSPI_CTRL, + 4, 6, CLK_DIVIDER_ONE_BASED), + EIC7700_DIV(EIC7700_CLK_DIV_SCPU_CORE_DYNM, + "divider_scpu_core_div_dynm", "fixed_rate_clk_spll0_fout1", + 0, EIC7700_REG_OFFSET_SCPU_CORE_CTRL, 4, 4, + CLK_DIVIDER_ONE_BASED), + EIC7700_DIV(EIC7700_CLK_DIV_LPCPU_CORE_DYNM, + "divider_lpcpu_core_div_dynm", "fixed_rate_clk_spll0_fout1", + 0, EIC7700_REG_OFFSET_LPCPU_CORE_CTRL, 4, 4, + CLK_DIVIDER_ONE_BASED), + EIC7700_DIV(EIC7700_CLK_DIV_GPU_ACLK_DYNM, "divider_gpu_aclk_div_dynm", + "fixed_rate_clk_spll0_fout1", 0, + EIC7700_REG_OFFSET_GPU_ACLK_CTRL, 4, 4, + CLK_DIVIDER_ONE_BASED), + EIC7700_DIV(EIC7700_CLK_DIV_D2D_ACLK_DYNM, "divider_d2d_aclk_div_dynm", + "mux_d2d_aclk_root_2mux1_gfree", 0, + EIC7700_REG_OFFSET_D2D_ACLK_CTRL, 4, 4, + CLK_DIVIDER_ONE_BASED), + EIC7700_DIV(EIC7700_CLK_DIV_DSP_ACLK_DYNM, "divider_dsp_aclk_div_dynm", + "mux_d2d_aclk_root_2mux1_gfree", 0, + EIC7700_REG_OFFSET_D2D_ACLK_CTRL, 4, 4, + CLK_DIVIDER_ONE_BASED), + EIC7700_DIV(EIC7700_CLK_DIV_DDR_ACLK_DYNM, "divider_ddr_aclk_div_dynm", + "mux_ddr_aclk_root_2mux1_gfree", 0, + EIC7700_REG_OFFSET_DDR_CTRL, 20, 4, CLK_DIVIDER_ONE_BASED), + EIC7700_DIV(EIC7700_CLK_DIV_HSP_ACLK_DYNM, "divider_hsp_aclk_div_dynm", + "fixed_rate_clk_spll0_fout1", 0, + EIC7700_REG_OFFSET_HSP_ACLK_CTRL, 4, 4, + CLK_DIVIDER_ONE_BASED), + EIC7700_DIV(EIC7700_CLK_DIV_ETH_TXCLK_DYNM_0, + "divider_eth_txclk_div_dynm_0", "mux_eth_core_2mux1", 0, + EIC7700_REG_OFFSET_ETH0_CTRL, 4, 7, CLK_DIVIDER_ONE_BASED), + EIC7700_DIV(EIC7700_CLK_DIV_ETH_TXCLK_DYNM_1, + "divider_eth_txclk_div_dynm_1", "mux_eth_core_2mux1", 0, + EIC7700_REG_OFFSET_ETH1_CTRL, 4, 7, CLK_DIVIDER_ONE_BASED), + EIC7700_DIV(EIC7700_CLK_DIV_MSHC_CORE_DYNM_0, + "divider_mshc_core_div_dynm_0", "mux_mshcore_root_3mux1_0", + 0, EIC7700_REG_OFFSET_MSHC0_CORE_CTRL, 4, 12, + CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ROUND_CLOSEST), + EIC7700_DIV(EIC7700_CLK_DIV_MSHC_CORE_DYNM_1, + "divider_mshc_core_div_dynm_1", "mux_mshcore_root_3mux1_1", + 0, EIC7700_REG_OFFSET_MSHC1_CORE_CTRL, 4, 12, + CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ROUND_CLOSEST), + EIC7700_DIV(EIC7700_CLK_DIV_MSHC_CORE_DYNM_2, + "divider_mshc_core_div_dynm_2", "mux_mshcore_root_3mux1_2", + 0, EIC7700_REG_OFFSET_MSHC2_CORE_CTRL, 4, 12, + CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ROUND_CLOSEST), + EIC7700_DIV(EIC7700_CLK_DIV_PCIE_ACLK_DYNM, + "divider_pcie_aclk_div_dynm", "fixed_rate_clk_spll2_fout2", + 0, EIC7700_REG_OFFSET_PCIE_ACLK_CTRL, 4, 4, + CLK_DIVIDER_ONE_BASED), + EIC7700_DIV(EIC7700_CLK_DIV_NPU_ACLK_DYNM, "divider_npu_aclk_div_dynm", + "fixed_rate_clk_spll0_fout1", 0, + EIC7700_REG_OFFSET_NPU_ACLK_CTRL, 4, 4, + CLK_DIVIDER_ONE_BASED), + EIC7700_DIV(EIC7700_CLK_DIV_NPU_LLC_SRC0_DYNM, + "divider_npu_llc_src0_div_dynm", + "fixed_rate_clk_spll0_fout1", 0, + EIC7700_REG_OFFSET_NPU_LLC_CTRL, 4, 4, + CLK_DIVIDER_ONE_BASED), + EIC7700_DIV(EIC7700_CLK_DIV_NPU_LLC_SRC1_DYNM, + "divider_npu_llc_src1_div_dynm", + "fixed_rate_clk_spll2_fout1", 0, + EIC7700_REG_OFFSET_NPU_LLC_CTRL, 8, 4, + CLK_DIVIDER_ONE_BASED), + EIC7700_DIV(EIC7700_CLK_DIV_NPU_CORECLK_DYNM, + "divider_npu_coreclk_div_dynm", "mux_npu_core_3mux1_gfree", + 0, EIC7700_REG_OFFSET_NPU_CORE_CTRL, 4, 4, + CLK_DIVIDER_ONE_BASED), + EIC7700_DIV(EIC7700_CLK_DIV_NPU_E31_DYNM, "divider_npu_e31_div_dynm", + "mux_npu_e31_3mux1_gfree", 0, + EIC7700_REG_OFFSET_NPU_CORE_CTRL, 12, 4, + CLK_DIVIDER_ONE_BASED), + EIC7700_DIV(EIC7700_CLK_DIV_VI_ACLK_DYNM, "divider_vi_aclk_div_dynm", + "mux_vi_aclk_root_2mux1_gfree", 0, + EIC7700_REG_OFFSET_VI_ACLK_CTRL, 4, 4, + CLK_DIVIDER_ONE_BASED), + EIC7700_DIV(EIC7700_CLK_DIV_VI_DW_DYNM, "divider_vi_dw_div_dynm", + "mux_vi_dw_root_2mux1", 0, + EIC7700_REG_OFFSET_VI_DWCLK_CTRL, 4, 4, + CLK_DIVIDER_ONE_BASED), + EIC7700_DIV(EIC7700_CLK_DIV_VI_DVP_DYNM, "divider_vi_dvp_div_dynm", + "mux_vi_dvp_root_2mux1_gfree", 0, + EIC7700_REG_OFFSET_VI_DVP_CTRL, 4, 4, + CLK_DIVIDER_ONE_BASED), + EIC7700_DIV(EIC7700_CLK_DIV_VI_DIG_ISP_DYNM, + "divider_vi_dig_isp_div_dynm", + "mux_vi_dig_isp_root_2mux1_gfree", 0, + EIC7700_REG_OFFSET_VI_DIG_ISP_CTRL, 4, 4, + CLK_DIVIDER_ONE_BASED), + EIC7700_DIV(EIC7700_CLK_DIV_VI_SHUTTER_DYNM_0, + "divider_vi_shutter_div_dynm_0", + "fixed_rate_clk_vpll_fout2", 0, + EIC7700_REG_OFFSET_VI_SHUTTER0, 4, 7, + CLK_DIVIDER_ONE_BASED), + EIC7700_DIV(EIC7700_CLK_DIV_VI_SHUTTER_DYNM_1, + "divider_vi_shutter_div_dynm_1", + "fixed_rate_clk_vpll_fout2", 0, + EIC7700_REG_OFFSET_VI_SHUTTER1, 4, 7, + CLK_DIVIDER_ONE_BASED), + EIC7700_DIV(EIC7700_CLK_DIV_VI_SHUTTER_DYNM_2, + "divider_vi_shutter_div_dynm_2", + "fixed_rate_clk_vpll_fout2", 0, + EIC7700_REG_OFFSET_VI_SHUTTER2, 4, 7, + CLK_DIVIDER_ONE_BASED), + EIC7700_DIV(EIC7700_CLK_DIV_VI_SHUTTER_DYNM_3, + "divider_vi_shutter_div_dynm_3", + "fixed_rate_clk_vpll_fout2", 0, + EIC7700_REG_OFFSET_VI_SHUTTER3, 4, 7, + CLK_DIVIDER_ONE_BASED), + EIC7700_DIV(EIC7700_CLK_DIV_VI_SHUTTER_DYNM_4, + "divider_vi_shutter_div_dynm_4", + "fixed_rate_clk_vpll_fout2", 0, + EIC7700_REG_OFFSET_VI_SHUTTER4, 4, 7, + CLK_DIVIDER_ONE_BASED), + EIC7700_DIV(EIC7700_CLK_DIV_VI_SHUTTER_DYNM_5, + "divider_vi_shutter_div_dynm_5", + "fixed_rate_clk_vpll_fout2", 0, + EIC7700_REG_OFFSET_VI_SHUTTER5, 4, 7, + CLK_DIVIDER_ONE_BASED), + EIC7700_DIV(EIC7700_CLK_DIV_VO_ACLK_DYNM, "divider_vo_aclk_div_dynm", + "mux_vo_aclk_root_2mux1_gfree", 0, + EIC7700_REG_OFFSET_VO_ACLK_CTRL, 4, 4, + CLK_DIVIDER_ONE_BASED), + EIC7700_DIV(EIC7700_CLK_DIV_IESMCLK_DYNM, "divider_iesmclk_div_dynm", + "fixed_rate_clk_spll0_fout3", 0, + EIC7700_REG_OFFSET_VO_IESMCLK_CTRL, 4, 4, + CLK_DIVIDER_ONE_BASED), + EIC7700_DIV(EIC7700_CLK_DIV_VO_PIXEL_DYNM, "divider_vo_pixel_div_dynm", + "mux_vo_pixel_root_2mux1", 0, + EIC7700_REG_OFFSET_VO_PIXEL_CTRL, 4, 6, + CLK_DIVIDER_ONE_BASED), + EIC7700_DIV(EIC7700_CLK_DIV_VO_MCLK_DYNM, "divider_vo_mclk_div_dynm", + "clk_apll_fout1", 0, EIC7700_REG_OFFSET_VO_MCLK_CTRL, 4, 8, + CLK_DIVIDER_ONE_BASED), + EIC7700_DIV(EIC7700_CLK_DIV_VO_CEC_DYNM, "divider_vo_cec_div_dynm", + "fixed_rate_clk_vpll_fout2", 0, + EIC7700_REG_OFFSET_VO_PHY_CLKCTRL, 16, 16, + CLK_DIVIDER_ROUND_CLOSEST), + EIC7700_DIV(EIC7700_CLK_DIV_VC_ACLK_DYNM, "divider_vc_aclk_div_dynm", + "mux_vcaclk_root_2mux1_gfree", 0, + EIC7700_REG_OFFSET_VC_ACLK_CTRL, 4, 4, + CLK_DIVIDER_ONE_BASED), + EIC7700_DIV(EIC7700_CLK_DIV_JD_DYNM, "divider_jd_div_dynm", + "mux_vcdec_root_2mux1_gfree", 0, EIC7700_REG_OFFSET_JD_CTRL, + 4, 4, CLK_DIVIDER_ONE_BASED), + EIC7700_DIV(EIC7700_CLK_DIV_JE_DYNM, "divider_je_div_dynm", + "mux_vcdec_root_2mux1_gfree", 0, EIC7700_REG_OFFSET_JE_CTRL, + 4, 4, CLK_DIVIDER_ONE_BASED), + EIC7700_DIV(EIC7700_CLK_DIV_VE_DYNM, "divider_ve_div_dynm", + "mux_vcdec_root_2mux1_gfree", 0, EIC7700_REG_OFFSET_VE_CTRL, + 4, 4, CLK_DIVIDER_ONE_BASED), + EIC7700_DIV(EIC7700_CLK_DIV_VD_DYNM, "divider_vd_div_dynm", + "mux_vcdec_root_2mux1_gfree", 0, EIC7700_REG_OFFSET_VD_CTRL, + 4, 4, CLK_DIVIDER_ONE_BASED), + EIC7700_DIV(EIC7700_CLK_DIV_G2D_DYNM, "divider_g2d_div_dynm", + "mux_dsp_aclk_root_2mux1_gfree", 0, + EIC7700_REG_OFFSET_G2D_CTRL, 4, 4, CLK_DIVIDER_ONE_BASED), + EIC7700_DIV(EIC7700_CLK_DIV_AONDMA_AXI_DYNM, + "divider_aondma_axi_div_dynm", "fixed_rate_clk_spll0_fout1", + 0, EIC7700_REG_OFFSET_AON_DMA_CTRL, 4, 4, + CLK_DIVIDER_ONE_BASED), + EIC7700_DIV(EIC7700_CLK_DIV_CRYPTO_DYNM, "divider_crypto_div_dynm", + "fixed_rate_clk_spll0_fout1", 0, + EIC7700_REG_OFFSET_SPACC_CTRL, 4, 4, CLK_DIVIDER_ONE_BASED), + EIC7700_DIV(EIC7700_CLK_DIV_SATA_PHY_REF_DYNM, + "divider_sata_phy_ref_div_dynm", + "fixed_rate_clk_spll1_fout2", 0, + EIC7700_REG_OFFSET_SATA_OOB_CTRL, 0, 4, + CLK_DIVIDER_ONE_BASED), + EIC7700_DIV(EIC7700_CLK_DIV_DSP_0_ACLK_DYNM, + "divider_dsp_0_aclk_div_dynm", "gate_dspt_aclk", 0, + EIC7700_REG_OFFSET_DSP_CFG_CTRL, 19, 1, 0), + EIC7700_DIV(EIC7700_CLK_DIV_DSP_1_ACLK_DYNM, + "divider_dsp_1_aclk_div_dynm", "gate_dspt_aclk", 0, + EIC7700_REG_OFFSET_DSP_CFG_CTRL, 20, 1, 0), + EIC7700_DIV(EIC7700_CLK_DIV_DSP_2_ACLK_DYNM, + "divider_dsp_2_aclk_div_dynm", "gate_dspt_aclk", 0, + EIC7700_REG_OFFSET_DSP_CFG_CTRL, 21, 1, 0), + EIC7700_DIV(EIC7700_CLK_DIV_DSP_3_ACLK_DYNM, + "divider_dsp_3_aclk_div_dynm", "gate_dspt_aclk", 0, + EIC7700_REG_OFFSET_DSP_CFG_CTRL, 22, 1, 0), + EIC7700_DIV(EIC7700_CLK_DIV_AON_RTC_DYNM, "divider_aon_rtc_div_dynm", + "fixed_factor_clk_1m_div24", 0, EIC7700_REG_OFFSET_RTC_CTRL, + 21, 11, CLK_DIVIDER_ONE_BASED), + EIC7700_DIV(EIC7700_CLK_DIV_U84_RTC_TOGGLE_DYNM, + "divider_u84_rtc_toggle_dynm", "xtal24m", 0, + EIC7700_REG_OFFSET_RTC_CTRL, 16, 5, + CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ROUND_CLOSEST), +}; + +/* gate clocks */ +static struct eswin_gate_clock eic7700_gate_clks[] = { + EIC7700_GATE(EIC7700_CLK_GATE_CPU_EXT_SRC_CORE_CLK_0, + "gate_clk_cpu_ext_src_core_clk_0", + "mux_cpu_root_3mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_U84_CTRL, 28, 0), + EIC7700_GATE(EIC7700_CLK_GATE_CPU_EXT_SRC_CORE_CLK_1, + "gate_clk_cpu_ext_src_core_clk_1", + "mux_cpu_root_3mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_U84_CTRL, 29, 0), + EIC7700_GATE(EIC7700_CLK_GATE_CPU_EXT_SRC_CORE_CLK_2, + "gate_clk_cpu_ext_src_core_clk_2", + "mux_cpu_root_3mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_U84_CTRL, 30, 0), + EIC7700_GATE(EIC7700_CLK_GATE_CPU_EXT_SRC_CORE_CLK_3, + "gate_clk_cpu_ext_src_core_clk_3", + "mux_cpu_root_3mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_U84_CTRL, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_CPU_TRACE_CLK_0, + "gate_clk_cpu_trace_clk_0", "mux_cpu_root_3mux1_gfree", + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_U84_CTRL, 24, 0), + EIC7700_GATE(EIC7700_CLK_GATE_CPU_TRACE_CLK_1, + "gate_clk_cpu_trace_clk_1", "mux_cpu_root_3mux1_gfree", + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_U84_CTRL, 25, 0), + EIC7700_GATE(EIC7700_CLK_GATE_CPU_TRACE_CLK_2, + "gate_clk_cpu_trace_clk_2", "mux_cpu_root_3mux1_gfree", + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_U84_CTRL, 26, 0), + EIC7700_GATE(EIC7700_CLK_GATE_CPU_TRACE_CLK_3, + "gate_clk_cpu_trace_clk_3", "mux_cpu_root_3mux1_gfree", + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_U84_CTRL, 27, 0), + EIC7700_GATE(EIC7700_CLK_GATE_CPU_TRACE_COM_CLK, + "gate_clk_cpu_trace_com_clk", "mux_cpu_aclk_2mux1_gfree", + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_U84_CTRL, 23, 0), + EIC7700_GATE(EIC7700_CLK_GATE_SPLL0_FOUT2, "gate_clk_spll0_fout2", + "fixed_rate_clk_spll0_fout2", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_SPLL0_CFG_2, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_NOC_NSP_CLK, "gate_noc_nsp_clk", + "divider_noc_nsp_div_dynm", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_NOC_CTRL, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_BOOTSPI, "gate_clk_bootspi", + "mux_bootspi_clk_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_BOOTSPI_CTRL, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_BOOTSPI_CFG, "gate_clk_bootspi_cfg", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_BOOTSPI_CFGCLK_CTRL, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_SCPU_CORE, "gate_clk_scpu_core", + "mux_scpu_core_clk_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_SCPU_CORE_CTRL, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_SCPU_BUS, "gate_clk_scpu_bus", + "fixed_factor_scpu_bus_div2", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_SCPU_BUSCLK_CTRL, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_LPCPU_CORE, "gate_clk_lpcpu_core", + "mux_lpcpu_core_clk_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_LPCPU_CORE_CTRL, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_LPCPU_BUS, "gate_clk_lpcpu_bus", + "fixed_factor_lpcpu_bus_div2", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_LPCPU_BUSCLK_CTRL, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_GPU_ACLK, "gate_gpu_aclk", + "divider_gpu_aclk_div_dynm", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_GPU_ACLK_CTRL, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_GPU_GRAY_CLK, "gate_gpu_gray_clk", + "xtal24m", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_GPU_GRAY_CTRL, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_GPU_CFG_CLK, "gate_gpu_cfg_clk", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_GPU_CFG_CTRL, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_DSPT_ACLK, "gate_dspt_aclk", + "divider_dsp_aclk_div_dynm", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_DSP_ACLK_CTRL, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_DSPT_CFG_CLK, "gate_dspt_cfg_clk", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_DSP_CFG_CTRL, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_D2D_ACLK, "gate_d2d_aclk", + "divider_d2d_aclk_div_dynm", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_D2D_ACLK_CTRL, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_D2D_CFG_CLK, "gate_d2d_cfg_clk", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_D2D_CFG_CTRL, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_TCU_ACLK, "gate_tcu_aclk", + "divider_ddr_aclk_div_dynm", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_TCU_ACLK_CTRL, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_TCU_CFG_CLK, "gate_tcu_cfg_clk", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_TCU_CFG_CTRL, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_DDRT_CFG_CLK, "gate_ddrt_cfg_clk", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_DDR_CTRL, 9, 0), + EIC7700_GATE(EIC7700_CLK_GATE_DDRT0_P0_ACLK, "gate_ddrt0_p0_aclk", + "divider_ddr_aclk_div_dynm", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_DDR_CTRL, 4, 0), + EIC7700_GATE(EIC7700_CLK_GATE_DDRT0_P1_ACLK, "gate_ddrt0_p1_aclk", + "divider_ddr_aclk_div_dynm", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_DDR_CTRL, 5, 0), + EIC7700_GATE(EIC7700_CLK_GATE_DDRT0_P2_ACLK, "gate_ddrt0_p2_aclk", + "divider_ddr_aclk_div_dynm", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_DDR_CTRL, 6, 0), + EIC7700_GATE(EIC7700_CLK_GATE_DDRT0_P3_ACLK, "gate_ddrt0_p3_aclk", + "divider_ddr_aclk_div_dynm", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_DDR_CTRL, 7, 0), + EIC7700_GATE(EIC7700_CLK_GATE_DDRT0_P4_ACLK, "gate_ddrt0_p4_aclk", + "divider_ddr_aclk_div_dynm", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_DDR_CTRL, 8, 0), + EIC7700_GATE(EIC7700_CLK_GATE_DDRT1_P0_ACLK, "gate_ddrt1_p0_aclk", + "divider_ddr_aclk_div_dynm", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_DDR1_CTRL, 4, 0), + EIC7700_GATE(EIC7700_CLK_GATE_DDRT1_P1_ACLK, "gate_ddrt1_p1_aclk", + "divider_ddr_aclk_div_dynm", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_DDR1_CTRL, 5, 0), + EIC7700_GATE(EIC7700_CLK_GATE_DDRT1_P2_ACLK, "gate_ddrt1_p2_aclk", + "divider_ddr_aclk_div_dynm", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_DDR1_CTRL, 6, 0), + EIC7700_GATE(EIC7700_CLK_GATE_DDRT1_P3_ACLK, "gate_ddrt1_p3_aclk", + "divider_ddr_aclk_div_dynm", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_DDR1_CTRL, 7, 0), + EIC7700_GATE(EIC7700_CLK_GATE_DDRT1_P4_ACLK, "gate_ddrt1_p4_aclk", + "divider_ddr_aclk_div_dynm", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_DDR1_CTRL, 8, 0), + EIC7700_GATE(EIC7700_CLK_GATE_HSP_ACLK, "gate_clk_hsp_aclk", + "divider_hsp_aclk_div_dynm", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_HSP_ACLK_CTRL, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_HSP_CFG_CLK, "gate_clk_hsp_cfg_clk", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_HSP_CFG_CTRL, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_PCIET_ACLK, "gate_pciet_aclk", + "divider_pcie_aclk_div_dynm", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_PCIE_ACLK_CTRL, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_PCIET_CFG_CLK, "gate_pciet_cfg_clk", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_PCIE_CFG_CTRL, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_PCIET_CR_CLK, "gate_pciet_cr_clk", + "fixed_factor_pcie_cr_div2", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_PCIE_CFG_CTRL, 0, 0), + EIC7700_GATE(EIC7700_CLK_GATE_PCIET_AUX_CLK, "gate_pciet_aux_clk", + "fixed_factor_pcie_aux_div4", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_PCIE_CFG_CTRL, 1, 0), + EIC7700_GATE(EIC7700_CLK_GATE_NPU_ACLK, "gate_npu_aclk", + "divider_npu_aclk_div_dynm", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_NPU_ACLK_CTRL, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_NPU_CFG_CLK, "gate_npu_cfg_clk", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_NPU_ACLK_CTRL, 30, 0), + EIC7700_GATE(EIC7700_CLK_GATE_NPU_LLC_ACLK, "gate_npu_llc_aclk", + "mux_npu_llclk_3mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_NPU_LLC_CTRL, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_NPU_CLK, "gate_npu_clk", + "divider_npu_coreclk_div_dynm", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_NPU_CORE_CTRL, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_NPU_E31_CLK, "gate_npu_e31_clk", + "divider_npu_e31_div_dynm", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_NPU_CORE_CTRL, 30, 0), + EIC7700_GATE(EIC7700_CLK_GATE_VI_ACLK, "gate_vi_aclk", + "divider_vi_aclk_div_dynm", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_VI_ACLK_CTRL, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_VI_CFG_CLK, "gate_vi_cfg_clk", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_VI_ACLK_CTRL, 30, 0), + EIC7700_GATE(EIC7700_CLK_GATE_VI_DIG_DW_CLK, "gate_vi_dig_dw_clk", + "divider_vi_dw_div_dynm", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_VI_DWCLK_CTRL, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_VI_DVP_CLK, "gate_vi_dvp_clk", + "divider_vi_dvp_div_dynm", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_VI_DVP_CTRL, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_VI_DIG_ISP_CLK, "gate_vi_dig_isp_clk", + "divider_vi_dig_isp_div_dynm", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_VI_DIG_ISP_CTRL, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_VI_SHUTTER_0, "gate_vi_shutter_0", + "divider_vi_shutter_div_dynm_0", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_VI_SHUTTER0, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_VI_SHUTTER_1, "gate_vi_shutter_1", + "divider_vi_shutter_div_dynm_1", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_VI_SHUTTER1, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_VI_SHUTTER_2, "gate_vi_shutter_2", + "divider_vi_shutter_div_dynm_2", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_VI_SHUTTER2, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_VI_SHUTTER_3, "gate_vi_shutter_3", + "divider_vi_shutter_div_dynm_3", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_VI_SHUTTER3, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_VI_SHUTTER_4, "gate_vi_shutter_4", + "divider_vi_shutter_div_dynm_4", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_VI_SHUTTER4, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_VI_SHUTTER_5, "gate_vi_shutter_5", + "divider_vi_shutter_div_dynm_5", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_VI_SHUTTER5, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_VI_PHY_TXCLKESC, "gate_vi_phy_txclkesc", + "fixed_factor_mipi_txesc_div10", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_VI_PHY_CTRL, 0, 0), + EIC7700_GATE(EIC7700_CLK_GATE_VI_PHY_CFG, "gate_vi_phy_cfg", "xtal24m", + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VI_PHY_CTRL, 1, 0), + EIC7700_GATE(EIC7700_CLK_GATE_VO_ACLK, "gate_vo_aclk", + "divider_vo_aclk_div_dynm", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_VO_ACLK_CTRL, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_VO_CFG_CLK, "gate_vo_cfg_clk", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_VO_ACLK_CTRL, 30, 0), + EIC7700_GATE(EIC7700_CLK_GATE_VO_HDMI_IESMCLK, "gate_vo_hdmi_iesmclk", + "divider_iesmclk_div_dynm", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_VO_IESMCLK_CTRL, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_VO_PIXEL_CLK, "gate_vo_pixel_clk", + "divider_vo_pixel_div_dynm", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_VO_PIXEL_CTRL, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_VO_I2S_MCLK, "gate_vo_i2s_mclk", + "mux_vo_mclk_2mux_ext_mclk", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_VO_MCLK_CTRL, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_VO_CR_CLK, "gate_vo_cr_clk", + "fixed_factor_mipi_txesc_div10", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_VO_PHY_CLKCTRL, 1, 0), + EIC7700_GATE(EIC7700_CLK_GATE_VC_ACLK, "gate_vc_aclk", + "divider_vc_aclk_div_dynm", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_VC_ACLK_CTRL, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_VC_CFG_CLK, "gate_vc_cfg_clk", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_VC_CLKEN_CTRL, 0, 0), + EIC7700_GATE(EIC7700_CLK_GATE_VC_JE_CLK, "gate_vc_je_clk", + "divider_je_div_dynm", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_JE_CTRL, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_VC_JD_CLK, "gate_vc_jd_clk", + "divider_jd_div_dynm", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_JD_CTRL, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_VC_VE_CLK, "gate_vc_ve_clk", + "divider_ve_div_dynm", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_VE_CTRL, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_VC_VD_CLK, "gate_vc_vd_clk", + "divider_vd_div_dynm", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_VD_CTRL, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_G2D_CFG_CLK, "gate_g2d_cfg_clk", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_G2D_CTRL, 28, 0), + EIC7700_GATE(EIC7700_CLK_GATE_G2D_CLK, "gate_g2d_clk", + "divider_g2d_div_dynm", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_G2D_CTRL, 30, 0), + EIC7700_GATE(EIC7700_CLK_GATE_G2D_ACLK, "gate_g2d_aclk", + "divider_g2d_div_dynm", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_G2D_CTRL, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_AONDMA_CFG, "gate_clk_aondma_cfg", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_AON_DMA_CTRL, 30, 0), + EIC7700_GATE(EIC7700_CLK_GATE_AONDMA_ACLK, "gate_aondma_aclk", + "mux_aondma_axi2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_AON_DMA_CTRL, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_AON_ACLK, "gate_aon_aclk", + "mux_aondma_axi2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_AON_DMA_CTRL, 29, 0), + EIC7700_GATE(EIC7700_CLK_GATE_TIMER_CLK_0, "gate_time_clk_0", "xtal24m", + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_TIMER_CTRL, 0, 0), + EIC7700_GATE(EIC7700_CLK_GATE_TIMER_CLK_1, "gate_time_clk_1", "xtal24m", + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_TIMER_CTRL, 1, 0), + EIC7700_GATE(EIC7700_CLK_GATE_TIMER_CLK_2, "gate_time_clk_2", "xtal24m", + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_TIMER_CTRL, 2, 0), + EIC7700_GATE(EIC7700_CLK_GATE_TIMER_CLK_3, "gate_time_clk_3", "xtal24m", + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_TIMER_CTRL, 3, 0), + EIC7700_GATE(EIC7700_CLK_GATE_TIMER_PCLK_0, "gate_timer_pclk_0", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_TIMER_CTRL, 4, 0), + EIC7700_GATE(EIC7700_CLK_GATE_TIMER_PCLK_1, "gate_timer_pclk_1", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_TIMER_CTRL, 5, 0), + EIC7700_GATE(EIC7700_CLK_GATE_TIMER_PCLK_2, "gate_timer_pclk_2", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_TIMER_CTRL, 6, 0), + EIC7700_GATE(EIC7700_CLK_GATE_TIMER_PCLK_3, "gate_timer_pclk_3", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_TIMER_CTRL, 7, 0), + EIC7700_GATE(EIC7700_CLK_GATE_TIMER3_CLK8, "gate_timer3_clk8", + "fixed_rate_clk_vpll_fout3", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_TIMER_CTRL, 8, 0), + EIC7700_GATE(EIC7700_CLK_GATE_RTC_CFG, "gate_clk_rtc_cfg", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_RTC_CTRL, 2, 0), + EIC7700_GATE(EIC7700_CLK_GATE_RTC, "gate_clk_rtc", + "divider_aon_rtc_div_dynm", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_RTC_CTRL, 1, 0), + EIC7700_GATE(EIC7700_CLK_GATE_PKA_CFG, "gate_clk_pka_cfg", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_PKA_CTRL, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_SPACC_CFG, "gate_clk_spacc_cfg", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_SPACC_CTRL, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_CRYPTO, "gate_clk_crypto", + "divider_crypto_div_dynm", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_SPACC_CTRL, 30, 0), + EIC7700_GATE(EIC7700_CLK_GATE_TRNG_CFG, "gate_clk_trng_cfg", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_TRNG_CTRL, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_OTP_CFG, "gate_clk_otp_cfg", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_OTP_CTRL, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_MAILBOX_0, "gate_clk_mailbox_0", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_LSP_EN1, 0, 0), + EIC7700_GATE(EIC7700_CLK_GATE_MAILBOX_1, "gate_clk_mailbox_1", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_LSP_EN1, 1, 0), + EIC7700_GATE(EIC7700_CLK_GATE_MAILBOX_2, "gate_clk_mailbox_2", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_LSP_EN1, 2, 0), + EIC7700_GATE(EIC7700_CLK_GATE_MAILBOX_3, "gate_clk_mailbox_3", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_LSP_EN1, 3, 0), + EIC7700_GATE(EIC7700_CLK_GATE_MAILBOX_4, "gate_clk_mailbox_4", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_LSP_EN1, 4, 0), + EIC7700_GATE(EIC7700_CLK_GATE_MAILBOX_5, "gate_clk_mailbox_5", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_LSP_EN1, 5, 0), + EIC7700_GATE(EIC7700_CLK_GATE_MAILBOX_6, "gate_clk_mailbox_6", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_LSP_EN1, 6, 0), + EIC7700_GATE(EIC7700_CLK_GATE_MAILBOX_7, "gate_clk_mailbox_7", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_LSP_EN1, 7, 0), + EIC7700_GATE(EIC7700_CLK_GATE_MAILBOX_8, "gate_clk_mailbox_8", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_LSP_EN1, 8, 0), + EIC7700_GATE(EIC7700_CLK_GATE_MAILBOX_9, "gate_clk_mailbox_9", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_LSP_EN1, 9, 0), + EIC7700_GATE(EIC7700_CLK_GATE_MAILBOX_10, "gate_clk_mailbox_10", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_LSP_EN1, 10, 0), + EIC7700_GATE(EIC7700_CLK_GATE_MAILBOX_11, "gate_clk_mailbox_11", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_LSP_EN1, 11, 0), + EIC7700_GATE(EIC7700_CLK_GATE_MAILBOX_12, "gate_clk_mailbox_12", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_LSP_EN1, 12, 0), + EIC7700_GATE(EIC7700_CLK_GATE_MAILBOX_13, "gate_clk_mailbox_13", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_LSP_EN1, 13, 0), + EIC7700_GATE(EIC7700_CLK_GATE_MAILBOX_14, "gate_clk_mailbox_14", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_LSP_EN1, 14, 0), + EIC7700_GATE(EIC7700_CLK_GATE_MAILBOX_15, "gate_clk_mailbox_15", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_LSP_EN1, 15, 0), + EIC7700_GATE(EIC7700_CLK_GATE_LSP_I2C0_PCLK, "gate_i2c0_pclk", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_LSP_EN0, 7, 0), + EIC7700_GATE(EIC7700_CLK_GATE_LSP_I2C1_PCLK, "gate_i2c1_pclk", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_LSP_EN0, 8, 0), + EIC7700_GATE(EIC7700_CLK_GATE_LSP_I2C2_PCLK, "gate_i2c2_pclk", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_LSP_EN0, 9, 0), + EIC7700_GATE(EIC7700_CLK_GATE_LSP_I2C3_PCLK, "gate_i2c3_pclk", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_LSP_EN0, 10, 0), + EIC7700_GATE(EIC7700_CLK_GATE_LSP_I2C4_PCLK, "gate_i2c4_pclk", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_LSP_EN0, 11, 0), + EIC7700_GATE(EIC7700_CLK_GATE_LSP_I2C5_PCLK, "gate_i2c5_pclk", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_LSP_EN0, 12, 0), + EIC7700_GATE(EIC7700_CLK_GATE_LSP_I2C6_PCLK, "gate_i2c6_pclk", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_LSP_EN0, 13, 0), + EIC7700_GATE(EIC7700_CLK_GATE_LSP_I2C7_PCLK, "gate_i2c7_pclk", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_LSP_EN0, 14, 0), + EIC7700_GATE(EIC7700_CLK_GATE_LSP_I2C8_PCLK, "gate_i2c8_pclk", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_LSP_EN0, 15, 0), + EIC7700_GATE(EIC7700_CLK_GATE_LSP_I2C9_PCLK, "gate_i2c9_pclk", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_LSP_EN0, 16, 0), + EIC7700_GATE(EIC7700_CLK_GATE_LSP_WDT0_PCLK, "gate_lsp_wdt0_pclk", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_LSP_EN0, 28, 0), + EIC7700_GATE(EIC7700_CLK_GATE_LSP_WDT1_PCLK, "gate_lsp_wdt1_pclk", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_LSP_EN0, 29, 0), + EIC7700_GATE(EIC7700_CLK_GATE_LSP_WDT2_PCLK, "gate_lsp_wdt2_pclk", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_LSP_EN0, 30, 0), + EIC7700_GATE(EIC7700_CLK_GATE_LSP_WDT3_PCLK, "gate_lsp_wdt3_pclk", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_LSP_EN0, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_LSP_SSI0_PCLK, "gate_lsp_ssi0_pclk", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_LSP_EN0, 26, 0), + EIC7700_GATE(EIC7700_CLK_GATE_LSP_SSI1_PCLK, "gate_lsp_ssi1_pclk", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_LSP_EN0, 27, 0), + EIC7700_GATE(EIC7700_CLK_GATE_LSP_UART0_PCLK, "gate_lsp_uart0_pclk", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_LSP_EN0, 17, 0), + EIC7700_GATE(EIC7700_CLK_GATE_LSP_UART1_PCLK, "gate_lsp_uart1_pclk", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_LSP_EN0, 18, 0), + EIC7700_GATE(EIC7700_CLK_GATE_LSP_UART2_PCLK, "gate_lsp_uart2_pclk", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_LSP_EN0, 19, 0), + EIC7700_GATE(EIC7700_CLK_GATE_LSP_UART3_PCLK, "gate_lsp_uart3_pclk", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_LSP_EN0, 20, 0), + EIC7700_GATE(EIC7700_CLK_GATE_LSP_UART4_PCLK, "gate_lsp_uart4_pclk", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_LSP_EN0, 21, 0), + EIC7700_GATE(EIC7700_CLK_GATE_LSP_TIMER_PCLK, "gate_lsp_timer_pclk", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_LSP_EN0, 25, 0), + EIC7700_GATE(EIC7700_CLK_GATE_LSP_FAN_PCLK, "gate_lsp_fan_pclk", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_LSP_EN0, 0, 0), + EIC7700_GATE(EIC7700_CLK_GATE_LSP_PVT_PCLK, "gate_lsp_pvt_pclk", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_LSP_EN0, 1, 0), + EIC7700_GATE(EIC7700_CLK_GATE_LSP_PVT0_CLK, "gate_pvt0_clk", + "fixed_factor_pvt_div20", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_LSP_EN1, 16, 0), + EIC7700_GATE(EIC7700_CLK_GATE_LSP_PVT1_CLK, "gate_pvt1_clk", + "fixed_factor_pvt_div20", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_LSP_EN1, 17, 0), + EIC7700_GATE(EIC7700_CLK_GATE_VC_JE_PCLK, "gate_vc_je_pclk", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_VC_CLKEN_CTRL, 2, 0), + EIC7700_GATE(EIC7700_CLK_GATE_VC_JD_PCLK, "gate_vc_jd_pclk", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_VC_CLKEN_CTRL, 1, 0), + EIC7700_GATE(EIC7700_CLK_GATE_VC_VE_PCLK, "gate_vc_ve_pclk", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_VC_CLKEN_CTRL, 5, 0), + EIC7700_GATE(EIC7700_CLK_GATE_VC_VD_PCLK, "gate_vc_vd_pclk", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_VC_CLKEN_CTRL, 4, 0), + EIC7700_GATE(EIC7700_CLK_GATE_VC_MON_PCLK, "gate_vc_mon_pclk", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_VC_CLKEN_CTRL, 3, 0), + EIC7700_GATE(EIC7700_CLK_GATE_HSP_MSHC0_CORE_CLK, + "gate_hsp_mshc0_core_clk", "divider_mshc_core_div_dynm_0", + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_MSHC0_CORE_CTRL, + 16, 0), + EIC7700_GATE(EIC7700_CLK_GATE_HSP_MSHC1_CORE_CLK, + "gate_hsp_mshc1_core_clk", "divider_mshc_core_div_dynm_1", + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_MSHC1_CORE_CTRL, + 16, 0), + EIC7700_GATE(EIC7700_CLK_GATE_HSP_MSHC2_CORE_CLK, + "gate_hsp_mshc2_core_clk", "divider_mshc_core_div_dynm_2", + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_MSHC2_CORE_CTRL, + 16, 0), + EIC7700_GATE(EIC7700_CLK_GATE_HSP_SATA_RBC_CLK, "gate_hsp_sata_rbc_clk", + "fixed_rate_clk_spll1_fout2", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_SATA_RBC_CTRL, 0, 0), + EIC7700_GATE(EIC7700_CLK_GATE_HSP_SATA_OOB_CLK, "gate_hsp_sata_oob_clk", + "mux_sata_phy_2mux1", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_SATA_OOB_CTRL, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_HSP_DMA0_CLK_TEST, + "gate_hsp_dma0_clk_test", "gate_clk_hsp_aclk", + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_HSP_ACLK_CTRL, 1, + 0), + EIC7700_GATE(EIC7700_CLK_GATE_HSP_DMA0_CLK, "gate_hsp_dma0_clk", + "gate_clk_hsp_aclk", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_HSP_ACLK_CTRL, 0, 0), + EIC7700_GATE(EIC7700_CLK_GATE_HSP_ETH0_CORE_CLK, + "gate_hsp_eth0_core_clk", "divider_eth_txclk_div_dynm_0", + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_ETH0_CTRL, 0, 0), + EIC7700_GATE(EIC7700_CLK_GATE_HSP_ETH1_CORE_CLK, + "gate_hsp_eth1_core_clk", "divider_eth_txclk_div_dynm_1", + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_ETH1_CTRL, 0, 0), + EIC7700_GATE(EIC7700_CLK_GATE_HSP_RMII_REF_0, "gate_hsp_rmii_ref_0", + "mux_rmii_ref_2mux1", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_ETH0_CTRL, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_HSP_RMII_REF_1, "gate_hsp_rmii_ref_1", + "mux_rmii_ref_2mux1", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_ETH1_CTRL, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_AON_I2C0_PCLK, "gate_aon_i2c0_pclk", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_I2C0_CTRL, 31, 0), + EIC7700_GATE(EIC7700_CLK_GATE_AON_I2C1_PCLK, "gate_aon_i2c1_pclk", + "mux_syscfg_clk_root_2mux1_gfree", CLK_SET_RATE_PARENT, + EIC7700_REG_OFFSET_I2C1_CTRL, 31, 0), +}; + +static int eic7700_clk_probe(struct platform_device *pdev) +{ + struct eswin_clock_data *clk_data; + struct device *dev = &pdev->dev; + + clk_data = eswin_clk_init(dev, EIC7700_NR_CLKS); + if (!clk_data) + return dev_err_probe(dev, -EAGAIN, "failed to get clk data!\n"); + + eswin_clk_register_fixed_rate(eic7700_fixed_rate_clks, + ARRAY_SIZE(eic7700_fixed_rate_clks), + clk_data, dev); + + eswin_clk_register_pll(eic7700_pll_clks, ARRAY_SIZE(eic7700_pll_clks), + clk_data, dev); + + eswin_clk_register_fixed_factor(eic7700_fixed_factor_clks, + ARRAY_SIZE(eic7700_fixed_factor_clks), + clk_data, dev); + + eswin_clk_register_mux(eic7700_mux_clks, ARRAY_SIZE(eic7700_mux_clks), + clk_data, dev); + + eswin_clk_register_divider(eic7700_div_clks, + ARRAY_SIZE(eic7700_div_clks), clk_data, dev); + + eswin_clk_register_gate(eic7700_gate_clks, + ARRAY_SIZE(eic7700_gate_clks), clk_data, dev); + + return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, + &clk_data->clk_data); +} + +static const struct of_device_id eic7700_clock_dt_ids[] = { + { .compatible = "eswin,eic7700-clock", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, eic7700_clock_dt_ids); + +static struct platform_driver eic7700_clock_driver = { + .probe = eic7700_clk_probe, + .driver = { + .name = "eic7700-clock", + .of_match_table = eic7700_clock_dt_ids, + }, +}; +module_platform_driver(eic7700_clock_driver); +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Yifeng Huang<huangyifeng@eswincomputing.com>"); +MODULE_AUTHOR("Xuyang Dong<dongxuyang@eswincomputing.com>"); +MODULE_DESCRIPTION("ESWIN EIC7700 clock controller driver"); diff --git a/drivers/clk/eswin/clk-eic7700.h b/drivers/clk/eswin/clk-eic7700.h new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/drivers/clk/eswin/clk-eic7700.h @@ -XXX,XX +XXX,XX @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2025, Beijing ESWIN Computing Technology Co., Ltd.. + * All rights reserved. + * + * Authors: + * Yifeng Huang <huangyifeng@eswincomputing.com> + * xuyang Dong <dongxuyang@eswincomputing.com> + */ + +#ifndef __CLK_EIC7700_H__ +#define __CLK_EIC7700_H__ + +/* REG OFFSET OF SYS-CRG */ +#define EIC7700_REG_OFFSET_SPLL0_CFG_0 0x0 +#define EIC7700_REG_OFFSET_SPLL0_CFG_1 0x4 +#define EIC7700_REG_OFFSET_SPLL0_CFG_2 0x8 +#define EIC7700_REG_OFFSET_SPLL0_DSKEWCAL 0xC +#define EIC7700_REG_OFFSET_SPLL0_SSC 0x10 +#define EIC7700_REG_OFFSET_SPLL1_CFG_0 0x14 +#define EIC7700_REG_OFFSET_SPLL1_CFG_1 0x18 +#define EIC7700_REG_OFFSET_SPLL1_CFG_2 0x1C +#define EIC7700_REG_OFFSET_SPLL1_DSKEWCAL 0x20 +#define EIC7700_REG_OFFSET_SPLL1_SSC 0x24 +#define EIC7700_REG_OFFSET_SPLL2_CFG_0 0x28 +#define EIC7700_REG_OFFSET_SPLL2_CFG_1 0x2C +#define EIC7700_REG_OFFSET_SPLL2_CFG_2 0x30 +#define EIC7700_REG_OFFSET_SPLL2_DSKEWCAL 0x34 +#define EIC7700_REG_OFFSET_SPLL2_SSC 0x38 +#define EIC7700_REG_OFFSET_VPLL_CFG_0 0x3C +#define EIC7700_REG_OFFSET_VPLL_CFG_1 0x40 +#define EIC7700_REG_OFFSET_VPLL_CFG_2 0x44 +#define EIC7700_REG_OFFSET_VPLL_DSKEWCAL 0x48 +#define EIC7700_REG_OFFSET_VPLL_SSC 0x4C +#define EIC7700_REG_OFFSET_APLL_CFG_0 0x50 +#define EIC7700_REG_OFFSET_APLL_CFG_1 0x54 +#define EIC7700_REG_OFFSET_APLL_CFG_2 0x58 +#define EIC7700_REG_OFFSET_APLL_DSKEWCAL 0x5C +#define EIC7700_REG_OFFSET_APLL_SSC 0x60 +#define EIC7700_REG_OFFSET_MCPUT_PLL_CFG_0 0x64 +#define EIC7700_REG_OFFSET_MCPUT_PLL_CFG_1 0x68 +#define EIC7700_REG_OFFSET_MCPUT_PLL_CFG_2 0x6C +#define EIC7700_REG_OFFSET_MCPUT_PLL_DSKEWCAL 0x70 +#define EIC7700_REG_OFFSET_MCPUT_PLL_SSC 0x74 +#define EIC7700_REG_OFFSET_DDRT_PLL_CFG_0 0x78 +#define EIC7700_REG_OFFSET_DDRT_PLL_CFG_1 0x7C +#define EIC7700_REG_OFFSET_DDRT_PLL_CFG_2 0x80 +#define EIC7700_REG_OFFSET_DDRT_PLL_DSKEWCAL 0x84 +#define EIC7700_REG_OFFSET_DDRT_PLL_SSC 0x88 +#define EIC7700_REG_OFFSET_PLL_STATUS 0xA4 +#define EIC7700_REG_OFFSET_NOC_CTRL 0x100 +#define EIC7700_REG_OFFSET_BOOTSPI_CTRL 0x104 +#define EIC7700_REG_OFFSET_BOOTSPI_CFGCLK_CTRL 0x108 +#define EIC7700_REG_OFFSET_SCPU_CORE_CTRL 0x10C +#define EIC7700_REG_OFFSET_SCPU_BUSCLK_CTRL 0x110 +#define EIC7700_REG_OFFSET_LPCPU_CORE_CTRL 0x114 +#define EIC7700_REG_OFFSET_LPCPU_BUSCLK_CTRL 0x118 +#define EIC7700_REG_OFFSET_TCU_ACLK_CTRL 0x11C +#define EIC7700_REG_OFFSET_TCU_CFG_CTRL 0x120 +#define EIC7700_REG_OFFSET_DDR_CTRL 0x124 +#define EIC7700_REG_OFFSET_DDR1_CTRL 0x128 +#define EIC7700_REG_OFFSET_GPU_ACLK_CTRL 0x12C +#define EIC7700_REG_OFFSET_GPU_CFG_CTRL 0x130 +#define EIC7700_REG_OFFSET_GPU_GRAY_CTRL 0x134 +#define EIC7700_REG_OFFSET_DSP_ACLK_CTRL 0x138 +#define EIC7700_REG_OFFSET_DSP_CFG_CTRL 0x13C +#define EIC7700_REG_OFFSET_D2D_ACLK_CTRL 0x140 +#define EIC7700_REG_OFFSET_D2D_CFG_CTRL 0x144 +#define EIC7700_REG_OFFSET_HSP_ACLK_CTRL 0x148 +#define EIC7700_REG_OFFSET_HSP_CFG_CTRL 0x14C +#define EIC7700_REG_OFFSET_SATA_RBC_CTRL 0x150 +#define EIC7700_REG_OFFSET_SATA_OOB_CTRL 0x154 +#define EIC7700_REG_OFFSET_ETH0_CTRL 0x158 +#define EIC7700_REG_OFFSET_ETH1_CTRL 0x15C +#define EIC7700_REG_OFFSET_MSHC0_CORE_CTRL 0x160 +#define EIC7700_REG_OFFSET_MSHC1_CORE_CTRL 0x164 +#define EIC7700_REG_OFFSET_MSHC2_CORE_CTRL 0x168 +#define EIC7700_REG_OFFSET_MSHC_USB_SLWCLK 0x16C +#define EIC7700_REG_OFFSET_PCIE_ACLK_CTRL 0x170 +#define EIC7700_REG_OFFSET_PCIE_CFG_CTRL 0x174 +#define EIC7700_REG_OFFSET_NPU_ACLK_CTRL 0x178 +#define EIC7700_REG_OFFSET_NPU_LLC_CTRL 0x17C +#define EIC7700_REG_OFFSET_NPU_CORE_CTRL 0x180 +#define EIC7700_REG_OFFSET_VI_DWCLK_CTRL 0x184 +#define EIC7700_REG_OFFSET_VI_ACLK_CTRL 0x188 +#define EIC7700_REG_OFFSET_VI_DIG_ISP_CTRL 0x18C +#define EIC7700_REG_OFFSET_VI_DVP_CTRL 0x190 +#define EIC7700_REG_OFFSET_VI_SHUTTER0 0x194 +#define EIC7700_REG_OFFSET_VI_SHUTTER1 0x198 +#define EIC7700_REG_OFFSET_VI_SHUTTER2 0x19C +#define EIC7700_REG_OFFSET_VI_SHUTTER3 0x1A0 +#define EIC7700_REG_OFFSET_VI_SHUTTER4 0x1A4 +#define EIC7700_REG_OFFSET_VI_SHUTTER5 0x1A8 +#define EIC7700_REG_OFFSET_VI_PHY_CTRL 0x1AC +#define EIC7700_REG_OFFSET_VO_ACLK_CTRL 0x1B0 +#define EIC7700_REG_OFFSET_VO_IESMCLK_CTRL 0x1B4 +#define EIC7700_REG_OFFSET_VO_PIXEL_CTRL 0x1B8 +#define EIC7700_REG_OFFSET_VO_MCLK_CTRL 0x1BC +#define EIC7700_REG_OFFSET_VO_PHY_CLKCTRL 0x1C0 +#define EIC7700_REG_OFFSET_VC_ACLK_CTRL 0x1C4 +#define EIC7700_REG_OFFSET_VCDEC_ROOT_CTRL 0x1C8 +#define EIC7700_REG_OFFSET_G2D_CTRL 0x1CC +#define EIC7700_REG_OFFSET_VC_CLKEN_CTRL 0x1D0 +#define EIC7700_REG_OFFSET_JE_CTRL 0x1D4 +#define EIC7700_REG_OFFSET_JD_CTRL 0x1D8 +#define EIC7700_REG_OFFSET_VD_CTRL 0x1DC +#define EIC7700_REG_OFFSET_VE_CTRL 0x1E0 +#define EIC7700_REG_OFFSET_AON_DMA_CTRL 0x1E4 +#define EIC7700_REG_OFFSET_TIMER_CTRL 0x1E8 +#define EIC7700_REG_OFFSET_RTC_CTRL 0x1EC +#define EIC7700_REG_OFFSET_PKA_CTRL 0x1F0 +#define EIC7700_REG_OFFSET_SPACC_CTRL 0x1F4 +#define EIC7700_REG_OFFSET_TRNG_CTRL 0x1F8 +#define EIC7700_REG_OFFSET_OTP_CTRL 0x1FC +#define EIC7700_REG_OFFSET_LSP_EN0 0x200 +#define EIC7700_REG_OFFSET_LSP_EN1 0x204 +#define EIC7700_REG_OFFSET_U84_CTRL 0x208 +#define EIC7700_REG_OFFSET_SYSCFG_CTRL 0x20C +#define EIC7700_REG_OFFSET_I2C0_CTRL 0x210 +#define EIC7700_REG_OFFSET_I2C1_CTRL 0x214 + +#endif /* __CLK_EIC7700_H__ */ diff --git a/drivers/clk/eswin/clk.c b/drivers/clk/eswin/clk.c new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/drivers/clk/eswin/clk.c @@ -XXX,XX +XXX,XX @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2025, Beijing ESWIN Computing Technology Co., Ltd.. + * All rights reserved. + * + * Authors: + * Yifeng Huang <huangyifeng@eswincomputing.com> + * Xuyang Dong <dongxuyang@eswincomputing.com> + */ + +#include <linux/clk.h> +#include <linux/clk-provider.h> +#include <linux/delay.h> +#include <linux/io.h> +#include <linux/math.h> +#include <linux/slab.h> + +#include <dt-bindings/clock/eswin,eic7700-clock.h> + +#include "clk.h" + +struct eswin_clock_data *eswin_clk_init(struct device *dev, + int nr_clks) +{ + struct eswin_clock_data *eclk_data; + + eclk_data = devm_kzalloc(dev, struct_size(eclk_data, clk_data.hws, + nr_clks), GFP_KERNEL); + if (!eclk_data) + return NULL; + + eclk_data->base = devm_of_iomap(dev, dev->of_node, 0, NULL); + if (IS_ERR(eclk_data->base)) { + dev_err(dev, "failed to map clock registers\n"); + return NULL; + } + + eclk_data->clk_data.num = nr_clks; + /* Avoid returning NULL for unused id */ + memset_p((void **)eclk_data->clk_data.hws, ERR_PTR(-ENOENT), nr_clks); + spin_lock_init(&eclk_data->lock); + + return eclk_data; +} + +/** + * eswin_calc_pll - calculate PLL values + * @frac_val: fractional divider + * @fbdiv_val: feedback divider + * @rate: reference rate + * @clk: PLL clock + * + * Calculate PLL values for frac and fbdiv + */ +static int eswin_calc_pll(u32 *frac_val, u32 *fbdiv_val, u64 rate, + const struct eswin_clk_pll *clk) +{ + u64 rem = 0; + u32 tmp1 = 0, tmp2 = 0; + + if (clk->id == EIC7700_CLK_APLL_FOUT1 || + clk->id == EIC7700_CLK_PLL_CPU) { + rate = rate * 4; + rem = do_div(rate, 1000); + if (rem) + tmp1 = rem; + + rem = do_div(rate, 1000); + if (rem) + tmp2 = rem; + + rem = do_div(rate, 24); + /* fbdiv = rate * 4 / 24000000 */ + *fbdiv_val = rate; + /* frac = rate * 4 % 24000000 * (2 ^ 24) */ + *frac_val = (u64)((1000 * (1000 * rem + tmp2) + tmp1) << 24) + / 24 / 1000000; + } else { + pr_err("Invalid pll set req, rate %lld, clk id %d\n", rate, + clk->id); + return -EINVAL; + } + + return 0; +} + +static inline struct eswin_clk_pll *to_pll_clk(struct clk_hw *hw) +{ + return container_of(hw, struct eswin_clk_pll, hw); +} + +static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct eswin_clk_pll *clk = to_pll_clk(hw); + struct clk *clk_cpu_lp_pll = NULL; + struct clk *clk_cpu_mux = NULL; + struct clk *clk_cpu_pll = NULL; + u32 postdiv1_val = 0, refdiv_val = 1; + u32 frac_val, fbdiv_val, val; + bool lock_flag = false; + int try_count = 0; + int ret; + + ret = eswin_calc_pll(&frac_val, &fbdiv_val, (u64)rate, clk); + if (ret) + return ret; + + /* Must switch the CPU to other CLK before we change the CPU PLL. */ + if (clk->id == EIC7700_CLK_PLL_CPU) { + clk_cpu_mux = __clk_lookup("mux_cpu_root_3mux1_gfree"); + if (!clk_cpu_mux) { + pr_err("failed to get clk: %s\n", + "mux_cpu_root_3mux1_gfree"); + return -EINVAL; + } + + clk_cpu_lp_pll = __clk_lookup("fixed_factor_u84_core_lp_div2"); + if (!clk_cpu_lp_pll) { + pr_err("failed to get clk: %s\n", + "fixed_factor_u84_core_lp_div2"); + return -EINVAL; + } + + ret = clk_prepare_enable(clk_cpu_lp_pll); + if (ret) { + pr_err("failed to enable clk: %s, ret = %d\n", + "fixed_factor_u84_core_lp_div2", ret); + return ret; + } + + clk_cpu_pll = __clk_lookup("clk_pll_cpu"); + if (!clk_cpu_pll) { + pr_err("failed to get clk: %s\n", "clk_pll_cpu"); + clk_disable_unprepare(clk_cpu_lp_pll); + return -EINVAL; + } + + ret = clk_set_parent(clk_cpu_mux, clk_cpu_lp_pll); + if (ret) { + pr_err("failed to switch %s to %s, ret %d\n", + "mux_cpu_root_3mux1_gfree", + "fixed_factor_u84_core_lp_div2", ret); + clk_disable_unprepare(clk_cpu_lp_pll); + return -EPERM; + } + } + + /* First, disable pll */ + val = readl_relaxed(clk->ctrl_reg0); + val &= ~(((1 << clk->pllen_width) - 1) << clk->pllen_shift); + val |= 0 << clk->pllen_shift; + writel_relaxed(val, clk->ctrl_reg0); + + val = readl_relaxed(clk->ctrl_reg0); + val &= ~(((1 << clk->fbdiv_width) - 1) << clk->fbdiv_shift); + val &= ~(((1 << clk->refdiv_width) - 1) << clk->refdiv_shift); + val |= refdiv_val << clk->refdiv_shift; + val |= fbdiv_val << clk->fbdiv_shift; + writel_relaxed(val, clk->ctrl_reg0); + + val = readl_relaxed(clk->ctrl_reg1); + val &= ~(((1 << clk->frac_width) - 1) << clk->frac_shift); + val |= frac_val << clk->frac_shift; + writel_relaxed(val, clk->ctrl_reg1); + + val = readl_relaxed(clk->ctrl_reg2); + val &= ~(((1 << clk->postdiv1_width) - 1) << clk->postdiv1_shift); + val |= postdiv1_val << clk->postdiv1_shift; + writel_relaxed(val, clk->ctrl_reg2); + + /* Last, enable pll */ + val = readl_relaxed(clk->ctrl_reg0); + val &= ~(((1 << clk->pllen_width) - 1) << clk->pllen_shift); + val |= 1 << clk->pllen_shift; + writel_relaxed(val, clk->ctrl_reg0); + + /* Usually the pll will lock in 50us */ + do { + usleep_range(refdiv_val * 80, refdiv_val * 80 * 2); + val = readl_relaxed(clk->status_reg); + if (val & 1 << clk->lock_shift) { + lock_flag = true; + break; + } + } while (try_count++ < 10); + + if (!lock_flag) { + pr_err("failed to lock the cpu pll!\n"); + return -EBUSY; + } + + if (clk->id == EIC7700_CLK_PLL_CPU) { + ret = clk_set_parent(clk_cpu_mux, clk_cpu_pll); + if (ret) { + pr_err("failed to switch %s to %s, ret %d\n", + "mux_cpu_root_3mux1_gfree", "clk_pll_cpu", ret); + return -EPERM; + } + clk_disable_unprepare(clk_cpu_lp_pll); + } + + return ret; +} + +static unsigned long clk_pll_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct eswin_clk_pll *clk = to_pll_clk(hw); + u64 fbdiv_val, frac_val, rem, tmp; + u32 val; + u64 rate = 0; + + val = readl_relaxed(clk->ctrl_reg0); + val = val >> clk->fbdiv_shift; + val &= ((1 << clk->fbdiv_width) - 1); + fbdiv_val = val; + + val = readl_relaxed(clk->ctrl_reg1); + val = val >> clk->frac_shift; + val &= ((1 << clk->frac_width) - 1); + frac_val = val; + + /* rate = 24000000 * (fbdiv + frac / (2 ^ 24)) / 4 */ + if (clk->id == EIC7700_CLK_APLL_FOUT1 || + clk->id == EIC7700_CLK_PLL_CPU) { + tmp = 1000 * frac_val; + rem = do_div(tmp, BIT(24)); + if (rem) + rate = (u64)(6000 * (1000 * fbdiv_val + tmp) + + ((6000 * rem) >> 24) + 1); + else + rate = (u64)(6000 * 1000 * fbdiv_val); + } else { + pr_err("unknown clk id %d\n", clk->id); + } + + return rate; +} + +static int clk_pll_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + struct eswin_clk_pll *clk = to_pll_clk(hw); + + switch (clk->id) { + case EIC7700_CLK_APLL_FOUT1: + req->rate = clamp(req->rate, APLL_LOW_FREQ, APLL_HIGH_FREQ); + req->min_rate = APLL_LOW_FREQ; + req->max_rate = APLL_HIGH_FREQ; + break; + case EIC7700_CLK_PLL_CPU: + req->rate = clamp(req->rate, PLL_LOW_FREQ, PLL_HIGH_FREQ); + req->min_rate = PLL_LOW_FREQ; + req->max_rate = PLL_HIGH_FREQ; + break; + default: + pr_err("unknown clk id %d\n", clk->id); + break; + } + + return 0; +} + +int eswin_clk_register_fixed_rate(const struct eswin_fixed_rate_clock *clks, + int nums, struct eswin_clock_data *data, + struct device *dev) +{ + struct clk_hw *clk_hw; + int i; + + for (i = 0; i < nums; i++) { + clk_hw = devm_clk_hw_register_fixed_rate(dev, clks[i].name, + clks[i].parent_name, + clks[i].flags, + clks[i].rate); + if (IS_ERR(clk_hw)) + return dev_err_probe(dev, PTR_ERR(clk_hw), + "failed to register clock\n"); + + data->clk_data.hws[clks[i].id] = clk_hw; + } + + return 0; +} + +static const struct clk_ops eswin_clk_pll_ops = { + .set_rate = clk_pll_set_rate, + .recalc_rate = clk_pll_recalc_rate, + .determine_rate = clk_pll_determine_rate, +}; + +void eswin_clk_register_pll(const struct eswin_pll_clock *clks, int nums, + struct eswin_clock_data *data, struct device *dev) +{ + struct eswin_clk_pll *p_clk = NULL; + struct clk_init_data init; + struct clk_hw *clk_hw; + int i, ret; + + p_clk = devm_kzalloc(dev, sizeof(*p_clk) * nums, GFP_KERNEL); + if (!p_clk) + return; + + for (i = 0; i < nums; i++) { + p_clk->id = clks[i].id; + p_clk->ctrl_reg0 = data->base + clks[i].ctrl_reg0; + p_clk->pllen_shift = clks[i].pllen_shift; + p_clk->pllen_width = clks[i].pllen_width; + p_clk->refdiv_shift = clks[i].refdiv_shift; + p_clk->refdiv_width = clks[i].refdiv_width; + p_clk->fbdiv_shift = clks[i].fbdiv_shift; + p_clk->fbdiv_width = clks[i].fbdiv_width; + + p_clk->ctrl_reg1 = data->base + clks[i].ctrl_reg1; + p_clk->frac_shift = clks[i].frac_shift; + p_clk->frac_width = clks[i].frac_width; + + p_clk->ctrl_reg2 = data->base + clks[i].ctrl_reg2; + p_clk->postdiv1_shift = clks[i].postdiv1_shift; + p_clk->postdiv1_width = clks[i].postdiv1_width; + p_clk->postdiv2_shift = clks[i].postdiv2_shift; + p_clk->postdiv2_width = clks[i].postdiv2_width; + + p_clk->status_reg = data->base + clks[i].status_reg; + p_clk->lock_shift = clks[i].lock_shift; + p_clk->lock_width = clks[i].lock_width; + + init.name = clks[i].name; + init.flags = 0; + init.parent_names = clks[i].parent_name ? + &clks[i].parent_name : NULL; + init.num_parents = clks[i].parent_name ? 1 : 0; + init.ops = &eswin_clk_pll_ops; + p_clk->hw.init = &init; + + clk_hw = &p_clk->hw; + ret = devm_clk_hw_register(dev, clk_hw); + if (ret) { + dev_err(dev, "failed to register clock %s\n", + clks[i].name); + continue; + } + + data->clk_data.hws[clks[i].id] = clk_hw; + p_clk++; + } +} + +int eswin_clk_register_fixed_factor(const struct eswin_fixed_factor_clock *clks, + int nums, struct eswin_clock_data *data, + struct device *dev) +{ + struct clk_hw *clk_hw; + int i; + + for (i = 0; i < nums; i++) { + clk_hw = devm_clk_hw_register_fixed_factor(dev, clks[i].name, + clks[i].parent_name, + clks[i].flags, + clks[i].mult, + clks[i].div); + if (IS_ERR(clk_hw)) + return dev_err_probe(dev, PTR_ERR(clk_hw), + "failed to register clock\n"); + + data->clk_data.hws[clks[i].id] = clk_hw; + } + + return 0; +} + +int eswin_clk_register_mux(const struct eswin_mux_clock *clks, int nums, + struct eswin_clock_data *data, struct device *dev) +{ + struct clk_hw *clk_hw; + int i; + + for (i = 0; i < nums; i++) { + clk_hw = devm_clk_hw_register_mux(dev, clks[i].name, + clks[i].parent_names, + clks[i].num_parents, + clks[i].flags, + data->base + clks[i].offset, + clks[i].shift, + clks[i].width, + clks[i].mux_flags, + &data->lock); + if (IS_ERR(clk_hw)) + return dev_err_probe(dev, PTR_ERR(clk_hw), + "failed to register clock\n"); + + data->clk_data.hws[clks[i].id] = clk_hw; + } + + return 0; +} + +int eswin_clk_register_mux_tbl(const struct eswin_mux_clock *clks, + int nums, struct eswin_clock_data *data, + struct device *dev) +{ + struct clk_hw *clk_hw; + int i; + + for (i = 0; i < nums; i++) { + clk_hw = clk_hw_register_mux_table(dev, clks[i].name, + clks[i].parent_names, + clks[i].num_parents, + clks[i].flags, + data->base + clks[i].offset, + clks[i].shift, + BIT(clks[i].width) - 1, + clks[i].mux_flags, + clks[i].table, &data->lock); + + if (IS_ERR(clk_hw)) { + while (i--) + clk_hw_unregister_mux + (data->clk_data.hws[clks[i].id]); + return dev_err_probe(dev, PTR_ERR(clk_hw), + "failed to register clock\n"); + } + + data->clk_data.hws[clks[i].id] = clk_hw; + } + + return 0; +} + +int eswin_clk_register_divider(const struct eswin_divider_clock *clks, + int nums, struct eswin_clock_data *data, + struct device *dev) +{ + struct clk_hw *clk_hw; + int i; + + for (i = 0; i < nums; i++) { + clk_hw = devm_clk_hw_register_divider(dev, clks[i].name, + clks[i].parent_name, + clks[i].flags, + data->base + + clks[i].offset, + clks[i].shift, + clks[i].width, + clks[i].div_flags, + &data->lock); + if (IS_ERR(clk_hw)) + return dev_err_probe(dev, PTR_ERR(clk_hw), + "failed to register clock\n"); + + data->clk_data.hws[clks[i].id] = clk_hw; + } + + return 0; +} + +int eswin_clk_register_gate(const struct eswin_gate_clock *clks, int nums, + struct eswin_clock_data *data, struct device *dev) +{ + struct clk_hw *clk_hw; + int i; + + for (i = 0; i < nums; i++) { + clk_hw = devm_clk_hw_register_gate(dev, clks[i].name, + clks[i].parent_name, + clks[i].flags, + data->base + clks[i].offset, + clks[i].bit_idx, + clks[i].gate_flags, + &data->lock); + + if (IS_ERR(clk_hw)) + return dev_err_probe(dev, PTR_ERR(clk_hw), + "failed to register clock\n"); + + data->clk_data.hws[clks[i].id] = clk_hw; + } + + return 0; +} diff --git a/drivers/clk/eswin/clk.h b/drivers/clk/eswin/clk.h new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/drivers/clk/eswin/clk.h @@ -XXX,XX +XXX,XX @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2025, Beijing ESWIN Computing Technology Co., Ltd.. + * All rights reserved. + * + * Authors: + * Yifeng Huang <huangyifeng@eswincomputing.com> + * Xuyang Dong <dongxuyang@eswincomputing.com> + */ + +#ifndef __ESWIN_CLK_H__ +#define __ESWIN_CLK_H__ + +#include <linux/clk-provider.h> +#include <linux/platform_device.h> +#include <linux/spinlock.h> + +#define APLL_HIGH_FREQ 983040000 +#define APLL_LOW_FREQ 225792000 +#define PLL_HIGH_FREQ 1800000000 +#define PLL_LOW_FREQ 24000000 + +struct eswin_clock_data { + void __iomem *base; + spinlock_t lock; /* protect register read-modify-write cycle */ + struct clk_hw_onecell_data clk_data; +}; + +struct eswin_divider_clock { + unsigned int id; + const char *name; + const char *parent_name; + unsigned long flags; + unsigned long offset; + u8 shift; + u8 width; + u8 div_flags; +}; + +struct eswin_fixed_rate_clock { + unsigned int id; + char *name; + const char *parent_name; + unsigned long flags; + unsigned long rate; +}; + +struct eswin_fixed_factor_clock { + unsigned int id; + char *name; + const char *parent_name; + unsigned long mult; + unsigned long div; + unsigned long flags; +}; + +struct eswin_gate_clock { + unsigned int id; + const char *name; + const char *parent_name; + unsigned long flags; + unsigned long offset; + u8 bit_idx; + u8 gate_flags; +}; + +struct eswin_mux_clock { + unsigned int id; + const char *name; + const char *const *parent_names; + u8 num_parents; + unsigned long flags; + unsigned long offset; + u8 shift; + u8 width; + u8 mux_flags; + u32 *table; +}; + +struct eswin_pll_clock { + u32 id; + const char *name; + const char *parent_name; + const u32 ctrl_reg0; + const u8 pllen_shift; + const u8 pllen_width; + const u8 refdiv_shift; + const u8 refdiv_width; + const u8 fbdiv_shift; + const u8 fbdiv_width; + + const u32 ctrl_reg1; + const u8 frac_shift; + const u8 frac_width; + + const u32 ctrl_reg2; + const u8 postdiv1_shift; + const u8 postdiv1_width; + const u8 postdiv2_shift; + const u8 postdiv2_width; + + const u32 status_reg; + const u8 lock_shift; + const u8 lock_width; +}; + +struct eswin_clk_pll { + struct clk_hw hw; + u32 id; + void __iomem *ctrl_reg0; + u8 pllen_shift; + u8 pllen_width; + u8 refdiv_shift; + u8 refdiv_width; + u8 fbdiv_shift; + u8 fbdiv_width; + + void __iomem *ctrl_reg1; + u8 frac_shift; + u8 frac_width; + + void __iomem *ctrl_reg2; + u8 postdiv1_shift; + u8 postdiv1_width; + u8 postdiv2_shift; + u8 postdiv2_width; + + void __iomem *status_reg; + u8 lock_shift; + u8 lock_width; +}; + +struct eswin_clock_data *eswin_clk_init(struct device *dev, int nr_clks); +int eswin_clk_register_fixed_rate(const struct eswin_fixed_rate_clock *clks, + int nums, struct eswin_clock_data *data, + struct device *dev); +void eswin_clk_register_pll(const struct eswin_pll_clock *clks, int nums, + struct eswin_clock_data *data, struct device *dev); +int eswin_clk_register_fixed_factor(const struct eswin_fixed_factor_clock *clks, + int nums, struct eswin_clock_data *data, + struct device *dev); +int eswin_clk_register_mux(const struct eswin_mux_clock *clks, int nums, + struct eswin_clock_data *data, struct device *dev); +int eswin_clk_register_mux_tbl(const struct eswin_mux_clock *clks, + int nums, struct eswin_clock_data *data, + struct device *dev); +int eswin_clk_register_divider(const struct eswin_divider_clock *clks, + int nums, struct eswin_clock_data *data, + struct device *dev); +int eswin_clk_register_gate(const struct eswin_gate_clock *clks, int nums, + struct eswin_clock_data *data, struct device *dev); + +#define PNAME(x) static const char *const x[] __initconst + +#define EIC7700_DIV(_id, _name, _pname, _flags, _offset, _shift, _width, \ + _dflags) \ + { \ + .id = _id, \ + .name = _name, \ + .parent_name = _pname, \ + .flags = _flags, \ + .offset = _offset, \ + .shift = _shift, \ + .width = _width, \ + .div_flags = _dflags, \ + } + +#define EIC7700_FACTOR(_id, _name, _pname, _mult, _div, _flags) \ + { \ + .id = _id, \ + .name = _name, \ + .parent_name = _pname, \ + .mult = _mult, \ + .div = _div, \ + .flags = _flags, \ + } + +#define EIC7700_FIXED(_id, _name, _pname, _flags, _rate) \ +{ \ + .id = _id, \ + .name = _name, \ + .parent_name = _pname, \ + .flags = _flags, \ + .rate = _rate, \ +} + +#define EIC7700_GATE(_id, _name, _pname, _flags, _offset, _idx, _gflags) \ + { \ + .id = _id, \ + .name = _name, \ + .parent_name = _pname, \ + .flags = _flags, \ + .offset = _offset, \ + .bit_idx = _idx, \ + .gate_flags = _gflags, \ + } + +#define EIC7700_MUX(_id, _name, _pnames, _num_parents, _flags, _offset, \ + _shift, _width, _mflags) \ + { \ + .id = _id, \ + .name = _name, \ + .parent_names = _pnames, \ + .num_parents = _num_parents, \ + .flags = _flags, \ + .offset = _offset, \ + .shift = _shift, \ + .width = _width, \ + .mux_flags = _mflags, \ + } + +#define EIC7700_MUX_TBL(_id, _name, _pnames, _num_parents, _flags, _offset, \ + _shift, _width, _mflags, _table) \ + { \ + .id = _id, \ + .name = _name, \ + .parent_names = _pnames, \ + .num_parents = _num_parents, \ + .flags = _flags, \ + .offset = _offset, \ + .shift = _shift, \ + .width = _width, \ + .mux_flags = _mflags, \ + .table = _table, \ + } + +#define EIC7700_PLL(_id, _name, _pname, _reg0, _en_shift, _en_width, \ + _ref_shift, _ref_width, _fb_shift, _fb_width, _reg1,\ + _frac_shift, _frac_width, _reg2, _post1_shift, \ + _post1_width, _post2_shift, _post2_width, _reg, \ + _lock_shift, _lock_width) \ + { \ + .id = _id, \ + .name = _name, \ + .parent_name = _pname, \ + .ctrl_reg0 = _reg0, \ + .pllen_shift = _en_shift, \ + .pllen_width = _en_width, \ + .refdiv_shift = _ref_shift, \ + .refdiv_width = _ref_width, \ + .fbdiv_shift = _fb_shift, \ + .fbdiv_width = _fb_width, \ + .ctrl_reg1 = _reg1, \ + .frac_shift = _frac_shift, \ + .frac_width = _frac_width, \ + .ctrl_reg2 = _reg2, \ + .postdiv1_shift = _post1_shift, \ + .postdiv1_width = _post1_width, \ + .postdiv2_shift = _post2_shift, \ + .postdiv2_width = _post2_width, \ + .status_reg = _reg, \ + .lock_shift = _lock_shift, \ + .lock_width = _lock_width, \ + } + +#endif /* __ESWIN_CLK_H__ */ -- 2.43.0 From: Xuyang Dong <dongxuyang@eswincomputing.com> Add Yifeng Huang and myself as maintainer of ESWIN EIC7700 clock driver. Signed-off-by: Xuyang Dong <dongxuyang@eswincomputing.com> --- MAINTAINERS | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index XXXXXXX..XXXXXXX 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -XXX,XX +XXX,XX @@ T: git https://github.com/eswincomputing/linux-next.git F: Documentation/devicetree/bindings/riscv/eswin.yaml F: arch/riscv/boot/dts/eswin/ +ESWIN EIC7700 CLOCK DRIVER +M: Xuyang Dong <dongxuyang@eswincomputing.com> +M: Yifeng Huang <huangyifeng@eswincomputing.com> +S: Maintained +F: Documentation/devicetree/bindings/clock/eswin,eic7700-clock.yaml +F: drivers/clk/eswin/ +F: include/dt-bindings/clock/eswin,eic7700-clock.h + ET131X NETWORK DRIVER M: Mark Einon <mark.einon@gmail.com> S: Odd Fixes -- 2.43.0