From nobody Sat Oct 4 16:21:30 2025 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7BCCF2D0C9C; Fri, 15 Aug 2025 08:53:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.61.82.184 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755247986; cv=none; b=SZlRPpnnCr2fXD8rBQqTp6f8gKzAXYQmyTWqhEUQxQ6Jo5CM6PXGgcUdL5gPnwHPiS+XSE9tD4F9PWeTbE0aowxlJRnM7YBH72iGAt97HtZELLCRVCFhNWvfobUAwyr8nRPJ6j3GMcXnBNZhEkA0fks8p4Ak0lrxRTnpsnutMlM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755247986; c=relaxed/simple; bh=LVnfO3MDOnl1v4WARjO1opVQn9Z3fUEK0gV+iT6dyuM=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=L9OWM1JAOU+5NbFwphPP9BGHn02apPwr5GcHG8dgZHjWQKrYGnh0+RhnBo2hW+9QIVmD33z/5wMYoYmouB4ggZwvlUI4fHiWrbOehwV5LK2bimBDbR1W0k1BL+V/uZn18BL7aYNXtStA8MyEHqW/1nFSG++0vUxOhtKkwVI9tYQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=MA1xcOg6; arc=none smtp.client-ip=210.61.82.184 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="MA1xcOg6" X-UUID: 3e2289a479b511f0b33aeb1e7f16c2b6-20250815 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=wc+rlANYiHTM8EUHj6Z9KXH85gzkwP5n7oU6eesBnQM=; b=MA1xcOg6RHn8/qeim8DKRNqYFd7epCuLwwzoJf2kllTFL9p+oD8c6oM2sQppzvxSaeFJY9avxCqtc3dL4J4DDCL7y82sKtMqFtMSD6fhTEacOM2VTVPhgrDqHrVupddHqMeQ5MfTEl68cQp42eyINl6Seyrqki1kqrxEucnCtUE=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.3.3,REQID:4e5d8b6d-0da4-4f78-a6d3-e8b47aae34f5,IP:0,UR L:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION:r elease,TS:0 X-CID-META: VersionHash:f1326cf,CLOUDID:218e2b7a-966c-41bd-96b5-7d0b3c22e782,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102,TC:-5,Content:0|15|50,EDM: -3,IP:nil,URL:0,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0, AV:0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 2,SSN|SDN X-CID-BAS: 2,SSN|SDN,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-CID-RHF: D41D8CD98F00B204E9800998ECF8427E X-UUID: 3e2289a479b511f0b33aeb1e7f16c2b6-20250815 Received: from mtkmbs11n2.mediatek.inc [(172.21.101.187)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 944301316; Fri, 15 Aug 2025 16:52:58 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs13n2.mediatek.inc (172.21.101.108) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.39; Fri, 15 Aug 2025 16:52:56 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.39 via Frontend Transport; Fri, 15 Aug 2025 16:52:55 +0800 From: Yunfei Dong To: =?UTF-8?q?N=C3=ADcolas=20F=20=2E=20R=20=2E=20A=20=2E=20Prado?= , Sebastian Fricke , Nicolas Dufresne , Hans Verkuil , AngeloGioacchino Del Regno , Benjamin Gaignard , Nathan Hebert , Daniel Almeida CC: Hsin-Yi Wang , Fritz Koenig , Daniel Vetter , Steve Cho , Yunfei Dong , , , , , , Subject: [PATCH v2 10/14] media: mediatek: vcodec: clean xpc status Date: Fri, 15 Aug 2025 16:52:23 +0800 Message-ID: <20250815085232.30240-11-yunfei.dong@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20250815085232.30240-1-yunfei.dong@mediatek.com> References: <20250815085232.30240-1-yunfei.dong@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Content-Type: text/plain; charset="utf-8" The driver need to clean xpc status when receive decoder hardware interrupt for mt8196 platform. Signed-off-by: Yunfei Dong --- .../vcodec/decoder/mtk_vcodec_dec_hw.c | 28 +++++++++++++++++++ .../vcodec/decoder/mtk_vcodec_dec_hw.h | 13 +++++++-- 2 files changed, 39 insertions(+), 2 deletions(-) diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_= hw.c b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_hw.c index 881d5de41e05..e4e527fe54dc 100644 --- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_hw.c +++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_hw.c @@ -61,6 +61,31 @@ static int mtk_vdec_hw_prob_done(struct mtk_vcodec_dec_d= ev *vdec_dev) return 0; } =20 +static void mtk_vdec_hw_write_reg_mask(void __iomem *reg_base, u32 reg_off= set, u32 val, u32 mask) +{ + void __iomem *reg_addr =3D reg_base + reg_offset; + u32 reg_val; + + reg_val =3D readl(reg_addr); + reg_val &=3D ~mask; + reg_val |=3D (val & mask); + writel(reg_val, reg_addr); +} + +static void mtk_vdec_hw_clean_xpc(struct mtk_vdec_hw_dev *dev) +{ + u32 val, mask, addr =3D VDEC_XPC_CLEAN_ADDR; + + if (dev->main_dev->chip_name !=3D MTK_VDEC_MT8196) + return; + + val =3D dev->hw_idx =3D=3D MTK_VDEC_LAT0 ? VDEC_XPC_LAT_VAL : VDEC_XPC_CO= RE_VAL; + mask =3D dev->hw_idx =3D=3D MTK_VDEC_LAT0 ? VDEC_XPC_LAT_MASK : VDEC_XPC_= CORE_MASK; + + mtk_vdec_hw_write_reg_mask(dev->reg_base[VDEC_HW_XPC], addr, val, mask); + mtk_vdec_hw_write_reg_mask(dev->reg_base[VDEC_HW_XPC], addr, 0, mask); +} + static irqreturn_t mtk_vdec_hw_irq_handler(int irq, void *priv) { struct mtk_vdec_hw_dev *dev =3D priv; @@ -88,6 +113,8 @@ static irqreturn_t mtk_vdec_hw_irq_handler(int irq, void= *priv) writel(dec_done_status | VDEC_IRQ_CFG, vdec_misc_addr); writel(dec_done_status & ~VDEC_IRQ_CLR, vdec_misc_addr); =20 + mtk_vdec_hw_clean_xpc(dev); + wake_up_dec_ctx(ctx, MTK_INST_IRQ_RECEIVED, dev->hw_idx); =20 mtk_v4l2_vdec_dbg(3, ctx, "wake up ctx %d, dec_done_status=3D%x", @@ -166,6 +193,7 @@ static int mtk_vdec_hw_probe(struct platform_device *pd= ev) subdev_dev->hw_idx =3D hw_idx; subdev_dev->main_dev =3D main_dev; subdev_dev->reg_base[VDEC_HW_SYS] =3D main_dev->reg_base[VDEC_HW_SYS]; + subdev_dev->reg_base[VDEC_HW_XPC] =3D main_dev->reg_base[VDEC_HW_MISC]; set_bit(subdev_dev->hw_idx, main_dev->subdev_bitmap); =20 if (IS_SUPPORT_VDEC_HW_IRQ(hw_idx)) { diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_= hw.h b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_hw.h index 83fe8b9428e6..50ce6c1d25a2 100644 --- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_hw.h +++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_hw.h @@ -18,17 +18,26 @@ #define VDEC_IRQ_CLR 0x10 #define VDEC_IRQ_CFG_REG 0xa4 =20 +#define VDEC_XPC_CLEAN_ADDR 0xc +#define VDEC_XPC_LAT_VAL BIT(0) +#define VDEC_XPC_LAT_MASK BIT(0) + +#define VDEC_XPC_CORE_VAL BIT(4) +#define VDEC_XPC_CORE_MASK BIT(4) + #define IS_SUPPORT_VDEC_HW_IRQ(hw_idx) ((hw_idx) !=3D MTK_VDEC_LAT_SOC) =20 /** * enum mtk_vdec_hw_reg_idx - subdev hardware register base index - * @VDEC_HW_SYS : vdec soc register index + * @VDEC_HW_SYS: vdec soc register index * @VDEC_HW_MISC: vdec misc register index - * @VDEC_HW_MAX : vdec supported max register index + * @VDEC_HW_XPC: vdec xpc register index + * @VDEC_HW_MAX: vdec supported max register index */ enum mtk_vdec_hw_reg_idx { VDEC_HW_SYS, VDEC_HW_MISC, + VDEC_HW_XPC, VDEC_HW_MAX }; =20 --=20 2.45.2