From nobody Sat Oct 4 14:33:07 2025 Received: from freeshell.de (freeshell.de [116.202.128.144]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 044A145948; Fri, 15 Aug 2025 07:46:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=116.202.128.144 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755243995; cv=none; b=MggCmMeMtorjwXldYTFbF/2+wcv7tM4pz+xanfrs/mtVuWNaig6vvXinfq5zejyXI45Q11kTqFzQvXwU/rbrotxBoZUaRyCHcsasy+DzObTKXYLA3uJVq/JW3yLlf5pAP64/rVmvMbMltbdkCsU+9CA01Y8DQAn8o2fuT9mOaLg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755243995; c=relaxed/simple; bh=tI/6+DEAQfH+v5NbvHBDZ16LwXixN0FnGsYGQtwhoeA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=BArFnhYPEtHS+IieMRl/a3PpaXrndpemwiVEW4xkBTUcUb043nxIZChHLgF0NcaLYvvUJc1R9N+pCBf/W5+naiaJ+pUvThTfXhf6HEGOCXegvT92OrHvSslbRp8lswBbXChoaO76+QPhH4slBIhvxd9qDnPB20hcQsxUMTOB92M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=freeshell.de; spf=pass smtp.mailfrom=freeshell.de; arc=none smtp.client-ip=116.202.128.144 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=freeshell.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=freeshell.de Received: from hay.lan (unknown [IPv6:2605:59c0:2078:cf00:6ecf:39ff:fe00:8375]) (Authenticated sender: e) by freeshell.de (Postfix) with ESMTPSA id 4A205B4E0036; Fri, 15 Aug 2025 09:40:04 +0200 (CEST) From: E Shattow To: Krzysztof Kozlowski , Rob Herring , Conor Dooley , E Shattow Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Hal Feng , Minda Chen Subject: [PATCH v2 1/3] dt-bindings: memory-controllers: add StarFive JH7110 SoC DMC Date: Fri, 15 Aug 2025 00:37:21 -0700 Message-ID: <20250815073739.79241-2-e@freeshell.de> X-Mailer: git-send-email 2.50.0 In-Reply-To: <20250815073739.79241-1-e@freeshell.de> References: <20250815073739.79241-1-e@freeshell.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Describe JH7110 SoC DDR external memory interface. Signed-off-by: E Shattow --- .../starfive,jh7110-dmc.yaml | 73 +++++++++++++++++++ 1 file changed, 73 insertions(+) create mode 100644 Documentation/devicetree/bindings/memory-controllers/st= arfive,jh7110-dmc.yaml diff --git a/Documentation/devicetree/bindings/memory-controllers/starfive,= jh7110-dmc.yaml b/Documentation/devicetree/bindings/memory-controllers/star= five,jh7110-dmc.yaml new file mode 100644 index 000000000000..be31d76f01ca --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/starfive,jh7110-= dmc.yaml @@ -0,0 +1,73 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/starfive,jh7110-dmc.= yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH7110 DMC + +maintainers: + - E Shattow + +description: + JH7110 DDR external memory interface LPDDR4/DDR4/DDR3/LPDDR3 32-bit at 2= 133Mbps (up to 2800Mbps). + +properties: + compatible: + items: + - const: starfive,jh7110-dmc + + reg: + items: + - description: controller registers + - description: phy registers + + clocks: + maxItems: 1 + + clock-names: + items: + - const: pll1_out + + resets: + items: + - description: axi + - description: osc + - description: apb + + reset-names: + items: + - const: axi + - const: osc + - const: apb + +required: + - compatible + - reg + - clocks + - clock-names + - resets + - reset-names + +additionalProperties: false + +examples: + - | + #include + #include + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + memory-controller@15700000 { + compatible =3D "starfive,jh7110-dmc"; + reg =3D <0x0 0x15700000 0x0 0x10000>, + <0x0 0x13000000 0x0 0x10000>; + clocks =3D <&syscrg JH7110_PLLCLK_PLL1_OUT>; + clock-names =3D "pll1_out"; + resets =3D <&syscrg JH7110_SYSRST_DDR_AXI>, + <&syscrg JH7110_SYSRST_DDR_OSC>, + <&syscrg JH7110_SYSRST_DDR_APB>; + reset-names =3D "axi", "osc", "apb"; + }; + }; --=20 2.50.0 From nobody Sat Oct 4 14:33:07 2025 Received: from freeshell.de (freeshell.de [116.202.128.144]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 35C8A1B87F0; Fri, 15 Aug 2025 07:40:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=116.202.128.144 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755243619; cv=none; b=lL1N+i6zJVvW+Ln3AETt/SFpc+0nZwuy0/eYFaAHrVTWT/2YgV28lChK8Wav6uV/q9CrLHtLoYrbRBbOQSWGpX88UCdS5vYV0/6FuAgQm4gxh59pBJR8xspllixWhiGPn80OtDmgPz7xAZeBE4st595NYUhOBaY1IR+4QfKGiEw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755243619; c=relaxed/simple; bh=YL1BfSC1z6DZFmxslmEmDKCyRthB4PgFvb9PNlan5jc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Frs2aT0k5I98dHeNzrKb7y+5dUMwg8ris+Y6V3AknkF+F02SLAnX66xKCTE7X9C8iXRisqprRjj2iOOsibu0HHf2Iy/4Yt64VOcQWXCf3bVNNvjLz301tRrpq51E+Y82xAmTOQi+maSqUP3ECRMhLCpLf3P+Zdfv/CWI3E0Ucy4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=freeshell.de; spf=pass smtp.mailfrom=freeshell.de; arc=none smtp.client-ip=116.202.128.144 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=freeshell.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=freeshell.de Received: from hay.lan (unknown [IPv6:2605:59c0:2078:cf00:6ecf:39ff:fe00:8375]) (Authenticated sender: e) by freeshell.de (Postfix) with ESMTPSA id E3717B4E0083; Fri, 15 Aug 2025 09:40:09 +0200 (CEST) From: E Shattow To: Conor Dooley , Emil Renner Berthing , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Hal Feng , Minda Chen , E Shattow , linux-riscv@lists.infradead.org Subject: [PATCH v2 2/3] riscv: dts: starfive: jh7110: add DMC memory controller Date: Fri, 15 Aug 2025 00:37:22 -0700 Message-ID: <20250815073739.79241-3-e@freeshell.de> X-Mailer: git-send-email 2.50.0 In-Reply-To: <20250815073739.79241-1-e@freeshell.de> References: <20250815073739.79241-1-e@freeshell.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add JH7110 SoC DDR external memory controller. Signed-off-by: E Shattow --- arch/riscv/boot/dts/starfive/jh7110.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts= /starfive/jh7110.dtsi index 0ba74ef04679..14df3d062a45 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -372,6 +372,18 @@ ccache: cache-controller@2010000 { cache-unified; }; =20 + memory-controller@15700000 { + compatible =3D "starfive,jh7110-dmc"; + reg =3D <0x0 0x15700000 0x0 0x10000>, + <0x0 0x13000000 0x0 0x10000>; + clocks =3D <&syscrg JH7110_PLLCLK_PLL1_OUT>; + clock-names =3D "pll1_out"; + resets =3D <&syscrg JH7110_SYSRST_DDR_AXI>, + <&syscrg JH7110_SYSRST_DDR_OSC>, + <&syscrg JH7110_SYSRST_DDR_APB>; + reset-names =3D "axi", "osc", "apb"; + }; + plic: interrupt-controller@c000000 { compatible =3D "starfive,jh7110-plic", "sifive,plic-1.0.0"; reg =3D <0x0 0xc000000 0x0 0x4000000>; --=20 2.50.0 From nobody Sat Oct 4 14:33:07 2025 Received: from freeshell.de (freeshell.de [116.202.128.144]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8F2171B87F0; Fri, 15 Aug 2025 07:40:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=116.202.128.144 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755243623; cv=none; b=UEPMdFpYSqUfcqa7Ltc3s5t7iPm5D22SWeC6g8JLVc3C7Z5daT0WOSPcampJgB/BGx7EjbPnU/CAESHZ6J5VMny/FYuho2I9DqNaQHf4lfJ2j8vULK+esg3WljDFFgby9O2bpYB8AvdyRyBUmbaOcrftPGMAltdkK0K9jv3fLB4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755243623; c=relaxed/simple; bh=XeVqOEcOcPty77QUlaMF0zPgFJynZ5xxGmxLTOfAhA4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Eda7iJOyiGrU4F0k2XXDfdtidcBd+QZBm+CF9NQkh7GuMx0TzgLO3/6b0W6idRFRCXQ5rp7Tm5F2vIUPoc1H2toDLE4a71ACTTsd0uf/9+PhwJGgh8xb/tesXHAPrf5bn1DRDdJcl8QG0+mw9x/D4Oo8nEdilhQqDXVCzbtF96s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=freeshell.de; spf=pass smtp.mailfrom=freeshell.de; arc=none smtp.client-ip=116.202.128.144 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=freeshell.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=freeshell.de Received: from hay.lan (unknown [IPv6:2605:59c0:2078:cf00:6ecf:39ff:fe00:8375]) (Authenticated sender: e) by freeshell.de (Postfix) with ESMTPSA id 18F0BB4E0001; Fri, 15 Aug 2025 09:40:16 +0200 (CEST) From: E Shattow To: Conor Dooley , Emil Renner Berthing , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Hal Feng , Minda Chen , E Shattow , linux-riscv@lists.infradead.org Subject: [PATCH v2 3/3] riscv: dts: starfive: jh7110: bootph-pre-ram hinting needed by boot loader Date: Fri, 15 Aug 2025 00:37:23 -0700 Message-ID: <20250815073739.79241-4-e@freeshell.de> X-Mailer: git-send-email 2.50.0 In-Reply-To: <20250815073739.79241-1-e@freeshell.de> References: <20250815073739.79241-1-e@freeshell.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add bootph-pre-ram hinting to jh7110.dtsi: - CPU interrupt controller(s) - core local interrupt timer - DDR memory controller - oscillator - syscrg clock-controller Signed-off-by: E Shattow --- arch/riscv/boot/dts/starfive/jh7110.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts= /starfive/jh7110.dtsi index 14df3d062a45..884a3526cb0f 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -35,6 +35,7 @@ S7_0: cpu@0 { =20 cpu0_intc: interrupt-controller { compatible =3D "riscv,cpu-intc"; + bootph-pre-ram; interrupt-controller; #interrupt-cells =3D <1>; }; @@ -68,6 +69,7 @@ U74_1: cpu@1 { =20 cpu1_intc: interrupt-controller { compatible =3D "riscv,cpu-intc"; + bootph-pre-ram; interrupt-controller; #interrupt-cells =3D <1>; }; @@ -101,6 +103,7 @@ U74_2: cpu@2 { =20 cpu2_intc: interrupt-controller { compatible =3D "riscv,cpu-intc"; + bootph-pre-ram; interrupt-controller; #interrupt-cells =3D <1>; }; @@ -134,6 +137,7 @@ U74_3: cpu@3 { =20 cpu3_intc: interrupt-controller { compatible =3D "riscv,cpu-intc"; + bootph-pre-ram; interrupt-controller; #interrupt-cells =3D <1>; }; @@ -167,6 +171,7 @@ U74_4: cpu@4 { =20 cpu4_intc: interrupt-controller { compatible =3D "riscv,cpu-intc"; + bootph-pre-ram; interrupt-controller; #interrupt-cells =3D <1>; }; @@ -321,6 +326,7 @@ mclk_ext: mclk-ext-clock { =20 osc: oscillator { compatible =3D "fixed-clock"; + bootph-pre-ram; clock-output-names =3D "osc"; #clock-cells =3D <0>; }; @@ -354,6 +360,7 @@ soc { clint: timer@2000000 { compatible =3D "starfive,jh7110-clint", "sifive,clint0"; reg =3D <0x0 0x2000000 0x0 0x10000>; + bootph-pre-ram; interrupts-extended =3D <&cpu0_intc 3>, <&cpu0_intc 7>, <&cpu1_intc 3>, <&cpu1_intc 7>, <&cpu2_intc 3>, <&cpu2_intc 7>, @@ -376,6 +383,7 @@ memory-controller@15700000 { compatible =3D "starfive,jh7110-dmc"; reg =3D <0x0 0x15700000 0x0 0x10000>, <0x0 0x13000000 0x0 0x10000>; + bootph-pre-ram; clocks =3D <&syscrg JH7110_PLLCLK_PLL1_OUT>; clock-names =3D "pll1_out"; resets =3D <&syscrg JH7110_SYSRST_DDR_AXI>, @@ -892,6 +900,7 @@ qspi: spi@13010000 { syscrg: clock-controller@13020000 { compatible =3D "starfive,jh7110-syscrg"; reg =3D <0x0 0x13020000 0x0 0x10000>; + bootph-pre-ram; clocks =3D <&osc>, <&gmac1_rmii_refin>, <&gmac1_rgmii_rxin>, <&i2stx_bclk_ext>, <&i2stx_lrck_ext>, --=20 2.50.0