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[91.139.201.119]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-afcdcfcb2ddsm74269266b.74.2025.08.15.00.05.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Aug 2025 00:05:17 -0700 (PDT) From: Ivaylo Ivanov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar Cc: linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 3/4] arm64: dts: exynos2200: increase the size of all syscons Date: Fri, 15 Aug 2025 10:04:59 +0300 Message-ID: <20250815070500.3275491-4-ivo.ivanov.ivanov1@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250815070500.3275491-1-ivo.ivanov.ivanov1@gmail.com> References: <20250815070500.3275491-1-ivo.ivanov.ivanov1@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" As IP cores are aligned by 0x10000, increase the size of all system register instances to the maximum (0x10000) to allow using accessing registers over the currently set limit. Suggested-by: Sam Protsenko Signed-off-by: Ivaylo Ivanov Reviewed-by: Sam Protsenko --- Did not add the r-b from Sam, as the patch is pretty much completely reworked, including the description. Please send it again :). --- arch/arm64/boot/dts/exynos/exynos2200.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/exynos/exynos2200.dtsi b/arch/arm64/boot/d= ts/exynos/exynos2200.dtsi index 943e83851..b3a8933a4 100644 --- a/arch/arm64/boot/dts/exynos/exynos2200.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos2200.dtsi @@ -306,7 +306,7 @@ cmu_peric0: clock-controller@10400000 { =20 syscon_peric0: syscon@10420000 { compatible =3D "samsung,exynos2200-peric0-sysreg", "syscon"; - reg =3D <0x10420000 0x2000>; + reg =3D <0x10420000 0x10000>; }; =20 pinctrl_peric0: pinctrl@10430000 { @@ -328,7 +328,7 @@ cmu_peric1: clock-controller@10700000 { =20 syscon_peric1: syscon@10720000 { compatible =3D "samsung,exynos2200-peric1-sysreg", "syscon"; - reg =3D <0x10720000 0x2000>; + reg =3D <0x10720000 0x10000>; }; =20 pinctrl_peric1: pinctrl@10730000 { @@ -418,7 +418,7 @@ cmu_ufs: clock-controller@11000000 { =20 syscon_ufs: syscon@11020000 { compatible =3D "samsung,exynos2200-ufs-sysreg", "syscon"; - reg =3D <0x11020000 0x2000>; + reg =3D <0x11020000 0x10000>; }; =20 pinctrl_ufs: pinctrl@11040000 { @@ -450,7 +450,7 @@ cmu_peric2: clock-controller@11c00000 { =20 syscon_peric2: syscon@11c20000 { compatible =3D "samsung,exynos2200-peric2-sysreg", "syscon"; - reg =3D <0x11c20000 0x4000>; + reg =3D <0x11c20000 0x10000>; }; =20 pinctrl_peric2: pinctrl@11c30000 { @@ -471,7 +471,7 @@ cmu_cmgp: clock-controller@14e00000 { =20 syscon_cmgp: syscon@14e20000 { compatible =3D "samsung,exynos2200-cmgp-sysreg", "syscon"; - reg =3D <0x14e20000 0x2000>; + reg =3D <0x14e20000 0x10000>; }; =20 pinctrl_cmgp: pinctrl@14e30000 { --=20 2.43.0