From nobody Sat Oct 4 14:36:15 2025 Received: from mail-ej1-f48.google.com (mail-ej1-f48.google.com [209.85.218.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6E4812D1900; Fri, 15 Aug 2025 07:05:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755241520; cv=none; b=W1UIZ2/MjmA23XLvxHemPUl9Dk2MQbjBaNrbIqNlbWbF84ixYwIvNtIkXaEwfKrA+7OIXVrjt7kDcB4q7dgApZJklSAzU1zT3Cm+o2/htP8/UqwiQpKL20pGHRbFZjjl36K/U2tHwP1wsx7k8mW+Sasq3tHX1+2/ZfuKsJ4MDEc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755241520; c=relaxed/simple; bh=VbLQDxGquo8ELD1QCg1kIt35ML7KSrvit7i/0YMFppM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=lR4s7RRZ62fYTUfFpiNsAX2TFZVZfTZxQyfRHgN2kulPWBPc+kLv/UZRRkL4OsAiXSxkXNx3SNJQz2g+Yw2e+MvU5hZWcuYlAO+j+DrU/9Ea2mM5unhrPSSmRQTUWr7IO+nqCHw6NwMaM3PTIVDI6D21cBRD1XVTEsDB+OG7Lfw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=fCYyZZn9; arc=none smtp.client-ip=209.85.218.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="fCYyZZn9" Received: by mail-ej1-f48.google.com with SMTP id a640c23a62f3a-afcb7acfde3so213348166b.3; Fri, 15 Aug 2025 00:05:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1755241516; x=1755846316; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=jGNseYWJek5Azr5uNJhZwVkFVh/FoAy6ND+2oSz2dvs=; b=fCYyZZn9Dm3ZiYDuGAUL78DuLNs3CzuXDsVOVuimoWUFEIJDaM1bvblEBRLf8UEfHk 9oC/qJYN488tDUPToQj5jTLjR4ghX0lK2LtQqWWyyZzaLS9eiRsFkdB6UrUQ1K+YRFov 5Ch/Rikf8G98O38cD4UgDX2DFyvTbC1pYaWb4lMrqS9R5SC1lcz4x3wHMqjz0LvvD/RC c2SPmBk+mG6BMCaF0XgqpZOqJPaP4WyAt1q2RY3FXTYIDXDpJEo0XMVLve+rdiyEqiyr YHkwc3Y52UTXqLIhv05NSX6up1EBSCLMcvSMh/Tylsd8ZF28d7vdYCFQQz1iu5PxzipL sGHw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1755241516; x=1755846316; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jGNseYWJek5Azr5uNJhZwVkFVh/FoAy6ND+2oSz2dvs=; b=qcytK3OraN0DWVkzNuAIogcp+qAMbpGUvslp58ZnBID1t7kG+7HgiHUmsbM04kNmnS OtDWlX0CTg6+TJ/ee7Ax48bJXSfAaVeUVeIeEzKkNGxDeTHgoi8839EcnXYYJCvD29Kj lesF6MRhyw45tle6gNt6k/CH4U6NIcCs9ES53naKxInwefSGWBj97Oo16BpBbWcSWIeV /ZWIstNphoP5YG/BHwzY8l8qeOFZaHyIMUGyTECqplLrWbrlXaMXKljCMzlaDlqvkCs6 9AfnXOUoUmoYAzaNVGvdXlioo/5qeWymqzrGpR3kQMihSEX7LkhROAR5nzSl+P+syfy+ f1kg== X-Forwarded-Encrypted: i=1; AJvYcCUy4ErbWzfrYFDX92kIYDU1SGM2/kQn1U/MohcEQ07z90fePcTO+ghXrUM26Tv8xBA2D4ysHmBZxpll@vger.kernel.org, AJvYcCWCO/4mH4kMllsQNyZjRHLVf+XkH+QMMgHZq0J/uKbuXLJbSF76ijCVbnBIScXa7lO1NF8WtS20JvU3a3Hp@vger.kernel.org X-Gm-Message-State: AOJu0Yx7StozTa73hrncTUdqv2JGGZ8Zr5NGHvHV/0cGGAwqTSbbmbhu 1fPrQQFHUsxNKLVCziROqjFohJ4eeJ/xlT5DoMjmhEbo7UtzfpiqgYSr X-Gm-Gg: ASbGncuABvLJRFmnCTbeo2K1T/7hehv7KYC3lz+UI0IagTgZ4c4AUuEscnr4gj7LNk7 jO8GocQWLvQDgK5yaqruIVj3hj69NiOK5eXIpJ74+DRLMV2FcXjAACAjjg7ZriOZyZuTbfZ27hq QpekiLQfZesLsHEHFZBtqQ9Eh5Dn60jBZISzAF2RmyMGiHu1YJY2O9xJwmjIv1wiQvhLegUZ8Dl 1x5j6IMN773/f/6ePiV+Xl1ufuwMQv2nmK/P3eiHvTycbXW8v3OfrE2hLoai5ynZZUXkDFRcGSx lv8lRT0L8zOsQUjWaj/FhWJl/PuWtCnouu0w3wPAJKg0J8klZlmb1aPvMGxLFRuVF45NfKIyBNc yZ6zl8pPcc2j+oI9H21yMauZqnDfIxQN9XBXQKr+TJhCudm9GaJM73fFiT1b6JtUCgpkNO/iP5c 6JlbT5jUtl X-Google-Smtp-Source: AGHT+IGj7vBYUE1quBMaFjbNLwReG7Th8g72pDzSLCH8avdjLFGI6YWDdzOBtuyrxZNJ6yrn4QIfCw== X-Received: by 2002:a17:907:7ea8:b0:af9:38ed:5b49 with SMTP id a640c23a62f3a-afcdc2062c1mr90228266b.5.1755241515430; Fri, 15 Aug 2025 00:05:15 -0700 (PDT) Received: from ivaylo-T580.. (91-139-201-119.stz.ddns.bulsat.com. [91.139.201.119]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-afcdcfcb2ddsm74269266b.74.2025.08.15.00.05.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Aug 2025 00:05:14 -0700 (PDT) From: Ivaylo Ivanov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar Cc: linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 1/4] arm64: dts: exynos2200: fix typo in hsi2c23 bus pins label Date: Fri, 15 Aug 2025 10:04:57 +0300 Message-ID: <20250815070500.3275491-2-ivo.ivanov.ivanov1@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250815070500.3275491-1-ivo.ivanov.ivanov1@gmail.com> References: <20250815070500.3275491-1-ivo.ivanov.ivanov1@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The '2' in 'hsi2c23' was missed while making the device tree. Fix that so we can properly reference the node. Signed-off-by: Ivaylo Ivanov Reviewed-by: Sam Protsenko --- arch/arm64/boot/dts/exynos/exynos2200-pinctrl.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/exynos/exynos2200-pinctrl.dtsi b/arch/arm6= 4/boot/dts/exynos/exynos2200-pinctrl.dtsi index f618ff290..5877da7ba 100644 --- a/arch/arm64/boot/dts/exynos/exynos2200-pinctrl.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos2200-pinctrl.dtsi @@ -1438,7 +1438,7 @@ i3c11_bus: i3c11-bus-pins { samsung,pin-drv =3D ; }; =20 - hsi223_bus: hsi2c23-bus-pins { + hsi2c23_bus: hsi2c23-bus-pins { samsung,pins =3D "gpp11-2", "gpp11-3"; samsung,pin-function =3D ; samsung,pin-pud =3D ; --=20 2.43.0 From nobody Sat Oct 4 14:36:15 2025 Received: from mail-ej1-f44.google.com (mail-ej1-f44.google.com [209.85.218.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 106252D1913; Fri, 15 Aug 2025 07:05:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.44 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755241523; cv=none; b=gm2dtfGdWd0I8oH7Ur46dIFR4GmLQX+jhcVXEDW2/cMUY2r/0q8iN5nQZ71JnjIBAe1mN8u02Tw0KMX/K9S/qcIG/hkVjdi4NNo1My+dUS2Pr8VOwkTBQlqtTi0BzX8RnfBFWT0+Vm+TJGWnuTxFzdQCpai2i6Dx6dt2psJVNn4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755241523; c=relaxed/simple; bh=KFldk5gBYr0jPJAMa2NrdCs2OJ64JIykOPZpaZCB2R8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=uE1pMoxXaIAaDaj4YSLrgcp/XhVYMxTA8BW4dcNEdFl99hHZwB2IJ31LbtGrFtmpbfiHGS4sU3teTF/ZzrZwgZm8DcJKzXpk/Uur+tLlvcr8YiHM60Osnv0bMSZ2L2ykV4kNV/TSqBcMxwVyw1bdExOWch9grMBNM66Ro/wFIr4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=E3gQnh3f; arc=none smtp.client-ip=209.85.218.44 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="E3gQnh3f" Received: by mail-ej1-f44.google.com with SMTP id a640c23a62f3a-afcb732eee6so301996866b.0; Fri, 15 Aug 2025 00:05:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1755241517; x=1755846317; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=y85zsZDQKxK8sD7ttJKCoLuHRw4j4DeYk5X8DxnnGnM=; b=E3gQnh3fSpbJVauDnLokhQMxvEkFGbahhOpEZMGrqSz4zNe7ynynzU44YBS8eoEjfl WFU6BvJbn6lAq2OlmodVEd+h97J+xmpy83UWZ6kTmVhD6HootRuX4Nt8sVCE4MksGujc 6fAFBiRJd+IUCJnFum8di6X8ltoyRlXKl3l/Ng0auV59+J/dINKRb/3bPv73z6qT61rL Z5SzNDdQyU6ZDnCAqRlFGOYle617frC+JU6eUlhSE/KoI1uoU9BLiuJNClcaGjjljq4/ nu/tUiu79U2Gn5DCdLMQPKrGblv0lzcABAkxAjc5hdk8t/1xEC/aLvJS+2HwDqGZNauO pv2w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1755241517; x=1755846317; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=y85zsZDQKxK8sD7ttJKCoLuHRw4j4DeYk5X8DxnnGnM=; b=PkC8u8po3iQjuK/CmydNF0fM4yffEzizCxJJug8EO2s07fze5mdOp6Gup2pFeQadx1 OSGtPK6XyHMGwS1+aJyQTK0MPfmZIH6C9cowO3rZ2zN5xEKsxYZom4EOo/KL2RrdzSzI PirJor6a7/w4HK4zbFOm0qXhhyVbyOIwL+Gd1DERHfnDu5oOFl2rPLVYtAmlG2OEDRzK 0BdXeWIAi4AM0TssXFiilppvDH0JdjFYVycNb2GrPZ2/iIxFj70mNxJmOC7UwLlJ0GH1 +63kJYKlnKBW4cvLxESL5DQkkhwzo5lf2Jcrktp5OHU1plUY4xYRW889PBISjUqCjdje c3Dg== X-Forwarded-Encrypted: i=1; AJvYcCWKLLvjXyNnm9+e9hO1TP2LKEjLfunvwDiES36JN4VopYZsgOcHFDXjkt5Oz9Mrr57Q2zvRxg085KXHmBEy@vger.kernel.org, AJvYcCX/0gIcrP5yXUBmV4eIkSsQx9Ch1wNCMamHF/z1OgQs9cYQ6t4D481zFfGs402ydoAB4ovlURuLabPM@vger.kernel.org X-Gm-Message-State: AOJu0YxZ138yWndmc2D8LaErK7l41P/LezKp5gmGsTsJ48W1rqsK5bm/ OXO1C4abwqdWH7twu3MmwiydIFks8lz80DH6E3zxPScyqQlTuhQFVSNe X-Gm-Gg: ASbGncuJPykPsB/e+23AX711IPQXI+v2uPXG451/RAxKIStECTJRAmMHuRcJr+E7MNU yvSzT7nQ1k4OW2OcqnBQxqcWemXdbR368eBP/JW2R+M1pDiAtywdl2UnFQy/jjmu+biCvLGuzL2 synBeHCeEGeOo10vsGNjFFF0/DPeswcXi6Np/Ir6gjYgMs4YW3Fiwy7hIDWUMb7UY2507kwXG/W +HYixW6qAn+/9JdZiA+Ub/x37+vkZUuEu6QVh+Tl0PgOmxFp+AA7at5eEDzhvAtao5AhqIBdnD7 Ur8w16o5LUATu0B45oi+aukH8rPg5kioEbdopx6/Dhe9Wyg5IWtmr9HyQKht2UVneUEjjZQ54I9 iA0vh5fZ/5Jqku1uPh2/PTfefdcEMCcEe53+R0jhmcMg8pFuPQPkxJXNGUSvVAqaA3ZMqtzX8Iw == X-Google-Smtp-Source: AGHT+IFh//es/9+sWoVhDlPCizn4RkmKiZ2SJp3F9fhVcL4Iza4SCu0VZsuSos1QjjpgbKmXip+6xg== X-Received: by 2002:a17:907:3e1a:b0:ad4:f517:ca3 with SMTP id a640c23a62f3a-afcdc1a3d54mr98349466b.20.1755241516911; Fri, 15 Aug 2025 00:05:16 -0700 (PDT) Received: from ivaylo-T580.. (91-139-201-119.stz.ddns.bulsat.com. [91.139.201.119]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-afcdcfcb2ddsm74269266b.74.2025.08.15.00.05.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Aug 2025 00:05:16 -0700 (PDT) From: Ivaylo Ivanov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar Cc: linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 2/4] arm64: dts: exynos2200: use 32-bit address space for /soc Date: Fri, 15 Aug 2025 10:04:58 +0300 Message-ID: <20250815070500.3275491-3-ivo.ivanov.ivanov1@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250815070500.3275491-1-ivo.ivanov.ivanov1@gmail.com> References: <20250815070500.3275491-1-ivo.ivanov.ivanov1@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" All peripherals on this SoC are mapped under the 32-bit address space (0x0 -> 0x20000000), so enforce that. Suggested-by: Sam Protsenko Signed-off-by: Ivaylo Ivanov Reviewed-by: Sam Protsenko --- This was suggested at [1]. [1] https://lore.kernel.org/all/CAPLW+4kPN65uX0tyG_F-4u5FQpPnwX9y6F1zrobq5U= yVbks+-w@mail.gmail.com --- arch/arm64/boot/dts/exynos/exynos2200.dtsi | 72 +++++++++++----------- 1 file changed, 36 insertions(+), 36 deletions(-) diff --git a/arch/arm64/boot/dts/exynos/exynos2200.dtsi b/arch/arm64/boot/d= ts/exynos/exynos2200.dtsi index 6b5ac02d0..943e83851 100644 --- a/arch/arm64/boot/dts/exynos/exynos2200.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos2200.dtsi @@ -221,22 +221,22 @@ psci { method =3D "smc"; }; =20 - soc { + soc@0 { compatible =3D "simple-bus"; - ranges; + ranges =3D <0x0 0x0 0x0 0x20000000>; =20 - #address-cells =3D <2>; - #size-cells =3D <2>; + #address-cells =3D <1>; + #size-cells =3D <1>; =20 chipid@10000000 { compatible =3D "samsung,exynos2200-chipid", "samsung,exynos850-chipid"; - reg =3D <0x0 0x10000000 0x0 0x24>; + reg =3D <0x10000000 0x24>; }; =20 cmu_peris: clock-controller@10020000 { compatible =3D "samsung,exynos2200-cmu-peris"; - reg =3D <0x0 0x10020000 0x0 0x8000>; + reg =3D <0x10020000 0x8000>; #clock-cells =3D <1>; =20 clocks =3D <&cmu_top CLK_DOUT_TCXO_DIV3>, @@ -250,7 +250,7 @@ cmu_peris: clock-controller@10020000 { mct_peris: timer@10040000 { compatible =3D "samsung,exynos2200-mct-peris", "samsung,exynos4210-mct"; - reg =3D <0x0 0x10040000 0x0 0x800>; + reg =3D <0x10040000 0x800>; clocks =3D <&cmu_top CLK_DOUT_TCXO_DIV3>, <&cmu_peris CLK_MOUT_PERIS_GI= C>; clock-names =3D "fin_pll", "mct"; interrupts =3D , @@ -270,8 +270,8 @@ mct_peris: timer@10040000 { =20 gic: interrupt-controller@10200000 { compatible =3D "arm,gic-v3"; - reg =3D <0x0 0x10200000 0x0 0x10000>, /* GICD */ - <0x0 0x10240000 0x0 0x200000>; /* GICR * 8 */ + reg =3D <0x10200000 0x10000>, /* GICD */ + <0x10240000 0x200000>; /* GICR * 8 */ =20 #interrupt-cells =3D <4>; interrupt-controller; @@ -294,7 +294,7 @@ ppi_cluster2: interrupt-partition-2 { =20 cmu_peric0: clock-controller@10400000 { compatible =3D "samsung,exynos2200-cmu-peric0"; - reg =3D <0x0 0x10400000 0x0 0x8000>; + reg =3D <0x10400000 0x8000>; #clock-cells =3D <1>; =20 clocks =3D <&xtcxo>, @@ -306,17 +306,17 @@ cmu_peric0: clock-controller@10400000 { =20 syscon_peric0: syscon@10420000 { compatible =3D "samsung,exynos2200-peric0-sysreg", "syscon"; - reg =3D <0x0 0x10420000 0x0 0x2000>; + reg =3D <0x10420000 0x2000>; }; =20 pinctrl_peric0: pinctrl@10430000 { compatible =3D "samsung,exynos2200-pinctrl"; - reg =3D <0x0 0x10430000 0x0 0x1000>; + reg =3D <0x10430000 0x1000>; }; =20 cmu_peric1: clock-controller@10700000 { compatible =3D "samsung,exynos2200-cmu-peric1"; - reg =3D <0x0 0x10700000 0x0 0x8000>; + reg =3D <0x10700000 0x8000>; #clock-cells =3D <1>; =20 clocks =3D <&xtcxo>, @@ -328,23 +328,23 @@ cmu_peric1: clock-controller@10700000 { =20 syscon_peric1: syscon@10720000 { compatible =3D "samsung,exynos2200-peric1-sysreg", "syscon"; - reg =3D <0x0 0x10720000 0x0 0x2000>; + reg =3D <0x10720000 0x2000>; }; =20 pinctrl_peric1: pinctrl@10730000 { compatible =3D "samsung,exynos2200-pinctrl"; - reg =3D <0x0 0x10730000 0x0 0x1000>; + reg =3D <0x10730000 0x1000>; }; =20 cmu_hsi0: clock-controller@10a00000 { compatible =3D "samsung,exynos2200-cmu-hsi0"; - reg =3D <0x0 0x10a00000 0x0 0x8000>; + reg =3D <0x10a00000 0x8000>; #clock-cells =3D <1>; }; =20 usb32drd: phy@10aa0000 { compatible =3D "samsung,exynos2200-usb32drd-phy"; - reg =3D <0x0 0x10aa0000 0x0 0x10000>; + reg =3D <0x10aa0000 0x10000>; =20 clocks =3D <&cmu_hsi0 CLK_MOUT_HSI0_NOC>; clock-names =3D "phy"; @@ -360,7 +360,7 @@ usb32drd: phy@10aa0000 { =20 usb_hsphy: phy@10ab0000 { compatible =3D "samsung,exynos2200-eusb2-phy"; - reg =3D <0x0 0x10ab0000 0x0 0x10000>; + reg =3D <0x10ab0000 0x10000>; =20 clocks =3D <&cmu_hsi0 CLK_MOUT_HSI0_USB32DRD>, <&cmu_hsi0 CLK_MOUT_HSI0_NOC>, @@ -374,7 +374,7 @@ usb_hsphy: phy@10ab0000 { =20 usb: usb@10b00000 { compatible =3D "samsung,exynos2200-dwusb3"; - ranges =3D <0x0 0x0 0x10b00000 0x10000>; + ranges =3D <0x0 0x10b00000 0x10000>; =20 clocks =3D <&cmu_hsi0 CLK_MOUT_HSI0_NOC>; clock-names =3D "link_aclk"; @@ -406,7 +406,7 @@ usb_dwc3: usb@0 { =20 cmu_ufs: clock-controller@11000000 { compatible =3D "samsung,exynos2200-cmu-ufs"; - reg =3D <0x0 0x11000000 0x0 0x8000>; + reg =3D <0x11000000 0x8000>; #clock-cells =3D <1>; =20 clocks =3D <&xtcxo>, @@ -418,27 +418,27 @@ cmu_ufs: clock-controller@11000000 { =20 syscon_ufs: syscon@11020000 { compatible =3D "samsung,exynos2200-ufs-sysreg", "syscon"; - reg =3D <0x0 0x11020000 0x0 0x2000>; + reg =3D <0x11020000 0x2000>; }; =20 pinctrl_ufs: pinctrl@11040000 { compatible =3D "samsung,exynos2200-pinctrl"; - reg =3D <0x0 0x11040000 0x0 0x1000>; + reg =3D <0x11040000 0x1000>; }; =20 pinctrl_hsi1ufs: pinctrl@11060000 { compatible =3D "samsung,exynos2200-pinctrl"; - reg =3D <0x0 0x11060000 0x0 0x1000>; + reg =3D <0x11060000 0x1000>; }; =20 pinctrl_hsi1: pinctrl@11240000 { compatible =3D "samsung,exynos2200-pinctrl"; - reg =3D <0x0 0x11240000 0x0 0x1000>; + reg =3D <0x11240000 0x1000>; }; =20 cmu_peric2: clock-controller@11c00000 { compatible =3D "samsung,exynos2200-cmu-peric2"; - reg =3D <0x0 0x11c00000 0x0 0x8000>; + reg =3D <0x11c00000 0x8000>; #clock-cells =3D <1>; =20 clocks =3D <&xtcxo>, @@ -450,17 +450,17 @@ cmu_peric2: clock-controller@11c00000 { =20 syscon_peric2: syscon@11c20000 { compatible =3D "samsung,exynos2200-peric2-sysreg", "syscon"; - reg =3D <0x0 0x11c20000 0x0 0x4000>; + reg =3D <0x11c20000 0x4000>; }; =20 pinctrl_peric2: pinctrl@11c30000 { compatible =3D "samsung,exynos2200-pinctrl"; - reg =3D <0x0 0x11c30000 0x0 0x1000>; + reg =3D <0x11c30000 0x1000>; }; =20 cmu_cmgp: clock-controller@14e00000 { compatible =3D "samsung,exynos2200-cmu-cmgp"; - reg =3D <0x0 0x14e00000 0x0 0x8000>; + reg =3D <0x14e00000 0x8000>; #clock-cells =3D <1>; =20 clocks =3D <&xtcxo>, @@ -471,12 +471,12 @@ cmu_cmgp: clock-controller@14e00000 { =20 syscon_cmgp: syscon@14e20000 { compatible =3D "samsung,exynos2200-cmgp-sysreg", "syscon"; - reg =3D <0x0 0x14e20000 0x0 0x2000>; + reg =3D <0x14e20000 0x2000>; }; =20 pinctrl_cmgp: pinctrl@14e30000 { compatible =3D "samsung,exynos2200-pinctrl"; - reg =3D <0x0 0x14e30000 0x0 0x1000>; + reg =3D <0x14e30000 0x1000>; =20 wakeup-interrupt-controller { compatible =3D "samsung,exynos2200-wakeup-eint", @@ -487,7 +487,7 @@ wakeup-interrupt-controller { =20 cmu_vts: clock-controller@15300000 { compatible =3D "samsung,exynos2200-cmu-vts"; - reg =3D <0x0 0x15300000 0x0 0x8000>; + reg =3D <0x15300000 0x8000>; #clock-cells =3D <1>; =20 clocks =3D <&xtcxo>, @@ -497,12 +497,12 @@ cmu_vts: clock-controller@15300000 { =20 pinctrl_vts: pinctrl@15320000 { compatible =3D "samsung,exynos2200-pinctrl"; - reg =3D <0x0 0x15320000 0x0 0x1000>; + reg =3D <0x15320000 0x1000>; }; =20 cmu_alive: clock-controller@15800000 { compatible =3D "samsung,exynos2200-cmu-alive"; - reg =3D <0x0 0x15800000 0x0 0x8000>; + reg =3D <0x15800000 0x8000>; #clock-cells =3D <1>; =20 clocks =3D <&xtcxo>, @@ -512,7 +512,7 @@ cmu_alive: clock-controller@15800000 { =20 pinctrl_alive: pinctrl@15850000 { compatible =3D "samsung,exynos2200-pinctrl"; - reg =3D <0x0 0x15850000 0x0 0x1000>; + reg =3D <0x15850000 0x1000>; =20 wakeup-interrupt-controller { compatible =3D "samsung,exynos2200-wakeup-eint", @@ -524,7 +524,7 @@ wakeup-interrupt-controller { pmu_system_controller: system-controller@15860000 { compatible =3D "samsung,exynos2200-pmu", "samsung,exynos7-pmu", "syscon"; - reg =3D <0x0 0x15860000 0x0 0x10000>; + reg =3D <0x15860000 0x10000>; =20 reboot: syscon-reboot { compatible =3D "syscon-reboot"; @@ -536,7 +536,7 @@ reboot: syscon-reboot { =20 cmu_top: clock-controller@1a320000 { compatible =3D "samsung,exynos2200-cmu-top"; - reg =3D <0x0 0x1a320000 0x0 0x8000>; + reg =3D <0x1a320000 0x8000>; #clock-cells =3D <1>; =20 clocks =3D <&xtcxo>; --=20 2.43.0 From nobody Sat Oct 4 14:36:15 2025 Received: from mail-ej1-f50.google.com (mail-ej1-f50.google.com [209.85.218.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 571442D2386; Fri, 15 Aug 2025 07:05:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.50 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755241522; cv=none; b=C28ZUP0sxmGxutiwpul3V7PTwUWqH1m0W69uPW4JsckV7KpSnGVZjaL78DhkfDhrZpcVkOAG3N0dmg6F/Sb8mYllKqKGuRT+4n/b7k0FjAhBiuLBcYfxdY3WwcbXoYAJf4uIVNDKQpKzyzWZ8B8FOwthtnYx/e0kZgKWkMMnYLk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755241522; c=relaxed/simple; bh=kyqxVhw64i1pCe19kinwbZPcaIRw9R3a8L53zXGT/dY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=WaoVdybCjNalaw7h+exCxtseZlDjKwgMNQNe71TJ6YYKaG+dpZ63yIivjpkcYYYK3tEgFXd+yqsqxawTefeyXJ3uDd/APoIs+Q8oZgwA9b2a1JvXUI89ksI9GY3fof4y4JtmNNYCE+92jPsYLmvd8qzq22FbrsuhWwVzlFzLzCg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=HRLopZaW; arc=none smtp.client-ip=209.85.218.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="HRLopZaW" Received: by mail-ej1-f50.google.com with SMTP id a640c23a62f3a-afcb78f5df4so286557966b.1; Fri, 15 Aug 2025 00:05:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1755241518; x=1755846318; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Lckrxo0Xz4JT/rW13ucWADdXpEaPkr562+yQE86m8n8=; b=HRLopZaWUDSl2OVd/e9HJ6VQGTa1iRkfSI88dBtZGmdFnrkdpdtKX2PVTtcldeMG2k Gzn0982cu1Z8O0gUpKmVC11cCHJ/QuxzbiGLdjczHG9BwxLKBD2vmKZ3yaAxERHSA0ww 3wo8923nAgVRk2CyEUUvApi50uYInPltB7LznTRq2voCYiB27PEtSy11nR+fuPcdwkLs jVrmltFi2QOQCXORMQZ8bb3UZ3/eq/+Vsylp0gqFmTmUbzrR/iVWkChmfoNBE99u6MHI TXtSslGOrJLq21CJOsmdVdnV9FFUOKFMp/3wcKvoM/nv+96Kazx8BqACPaeXte85/K9g rdog== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1755241518; x=1755846318; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Lckrxo0Xz4JT/rW13ucWADdXpEaPkr562+yQE86m8n8=; b=r0A7m+I0ocTEzXBDHWwEl+W0r9syBz6FAz3je4h0flRGb9wcqf07ExqwZ+1jiHjScw m+MiD6QhGIdGZq99SdH0kUSrpmXJJ/R6NKQTWYHNLTexgZcK+NhUNHSK2znAQxE0bXAO Mh0HxMHKAZ1LMN3zg2L8Gyqz4femeJyVJoXUb2zTgTExsPsgajvquxOBFhN4Oa3G6j19 NbBS7G352cLhZAgBBWqJBFP8IhXszpvZCbxF19OBI7isZXGKQmIvTZs+drr64l30h4Ib sbIS6Po0piG7qW+C8Ba3JtaDjLMaKxaG174Nma5Xj8rCEbdPHCbJ6zT/Nek74+0G9j96 20Eg== X-Forwarded-Encrypted: i=1; AJvYcCWVx1EGgF2uPYUKoEc/xiovG86MiR7wvzmQGH4ID4lVwfqNzZvG/nYgbLBJrrQhmCa3hky6o96xEFSP8N7K@vger.kernel.org, AJvYcCXp2lueO5eG4hcWynHsBLkwJMfKc/wE7bvs7epSC+1P+MmJY6yZh43JMT4qWyzDXMJVtF746LSxWTjD@vger.kernel.org X-Gm-Message-State: AOJu0Yzd//iSUnqKtDMQ0EvbNIePLgWa+ZUnIVD/nM7QNG21Lg8jA44V i+/INSn3wCbTOpp38cJS5g2pBPC4MUeP1YglEMvecH3r2ZdH8mVT2L/M X-Gm-Gg: ASbGncsUV0n+LYLg03wzs0RB9+zyqxvDx2M53ET9EaPcpDCuk+8zqkW/a0hTG1zfxQZ RijWbtCGv4c7fJQNiTT8C9Ffcitd9MrG0dlsy5vpEFvIg9rWhVth/MUqhDvo3OP7IV00sJ1YuMF NkLCx5F0+EDbOexC0X3sCVbvCh5K04SzAA/biGmLjLcoyKnvVNvx0s7IecjQYRTq1hWoxZJF1Bp SWpri1OLTrcvbG+jyZA7EEGrj3vHDmwcBoOl8vcrFuLH7WvYtEKt7kDq5jwCHcUwnyiDOhkz8Nh xteAKoP/5LbR8IFrRVKkzP+4fc2XORLxvEsaILAVXBVBwO4U58qhG4eIo002BjptvrOXjfy4a/z 6z1p17XkumGJwBueyM11xEseJFCT48cx/PBQMbEVJ4QWBdTQQ7og4tmhpfxxzgbvg8jrdeCioSA == X-Google-Smtp-Source: AGHT+IHdoKgbaywXOlXlmdziAkeTbaLLPsoCtUeca2ggfF4bp1BRhAF6fsBWunc30eaw8fVlaGaVxw== X-Received: by 2002:a17:907:c10:b0:ae0:b847:435 with SMTP id a640c23a62f3a-afcdc334505mr80275466b.49.1755241518334; Fri, 15 Aug 2025 00:05:18 -0700 (PDT) Received: from ivaylo-T580.. (91-139-201-119.stz.ddns.bulsat.com. [91.139.201.119]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-afcdcfcb2ddsm74269266b.74.2025.08.15.00.05.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Aug 2025 00:05:17 -0700 (PDT) From: Ivaylo Ivanov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar Cc: linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 3/4] arm64: dts: exynos2200: increase the size of all syscons Date: Fri, 15 Aug 2025 10:04:59 +0300 Message-ID: <20250815070500.3275491-4-ivo.ivanov.ivanov1@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250815070500.3275491-1-ivo.ivanov.ivanov1@gmail.com> References: <20250815070500.3275491-1-ivo.ivanov.ivanov1@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" As IP cores are aligned by 0x10000, increase the size of all system register instances to the maximum (0x10000) to allow using accessing registers over the currently set limit. Suggested-by: Sam Protsenko Signed-off-by: Ivaylo Ivanov Reviewed-by: Sam Protsenko --- Did not add the r-b from Sam, as the patch is pretty much completely reworked, including the description. Please send it again :). --- arch/arm64/boot/dts/exynos/exynos2200.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/exynos/exynos2200.dtsi b/arch/arm64/boot/d= ts/exynos/exynos2200.dtsi index 943e83851..b3a8933a4 100644 --- a/arch/arm64/boot/dts/exynos/exynos2200.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos2200.dtsi @@ -306,7 +306,7 @@ cmu_peric0: clock-controller@10400000 { =20 syscon_peric0: syscon@10420000 { compatible =3D "samsung,exynos2200-peric0-sysreg", "syscon"; - reg =3D <0x10420000 0x2000>; + reg =3D <0x10420000 0x10000>; }; =20 pinctrl_peric0: pinctrl@10430000 { @@ -328,7 +328,7 @@ cmu_peric1: clock-controller@10700000 { =20 syscon_peric1: syscon@10720000 { compatible =3D "samsung,exynos2200-peric1-sysreg", "syscon"; - reg =3D <0x10720000 0x2000>; + reg =3D <0x10720000 0x10000>; }; =20 pinctrl_peric1: pinctrl@10730000 { @@ -418,7 +418,7 @@ cmu_ufs: clock-controller@11000000 { =20 syscon_ufs: syscon@11020000 { compatible =3D "samsung,exynos2200-ufs-sysreg", "syscon"; - reg =3D <0x11020000 0x2000>; + reg =3D <0x11020000 0x10000>; }; =20 pinctrl_ufs: pinctrl@11040000 { @@ -450,7 +450,7 @@ cmu_peric2: clock-controller@11c00000 { =20 syscon_peric2: syscon@11c20000 { compatible =3D "samsung,exynos2200-peric2-sysreg", "syscon"; - reg =3D <0x11c20000 0x4000>; + reg =3D <0x11c20000 0x10000>; }; =20 pinctrl_peric2: pinctrl@11c30000 { @@ -471,7 +471,7 @@ cmu_cmgp: clock-controller@14e00000 { =20 syscon_cmgp: syscon@14e20000 { compatible =3D "samsung,exynos2200-cmgp-sysreg", "syscon"; - reg =3D <0x14e20000 0x2000>; + reg =3D <0x14e20000 0x10000>; }; =20 pinctrl_cmgp: pinctrl@14e30000 { --=20 2.43.0 From nobody Sat Oct 4 14:36:15 2025 Received: from mail-ed1-f43.google.com (mail-ed1-f43.google.com [209.85.208.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 98D3C2D3A80; Fri, 15 Aug 2025 07:05:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.43 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755241526; cv=none; b=X7snx+LN2ktqg0G0QiMp2SKZcAZjGpDCG5WJ5HMnYxesvIImeP5wZaA6r1Xax3zLKXYygc2rBXeE8vzj/xWq5uIjmVjkJ0Ma/DhWtO/TgFuUVRrrW7kV8W17YQ5F72IMta6lqWZj62UElAUdiGj1I5bRS6jUXn4F9+H3wUKwnZI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755241526; c=relaxed/simple; bh=ty9KGqpPFDozc+EeGXeWngOvyf4lX6T4BMYtq8pzpMk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=lq9MMeHjALzVm229lmLs9zr20HarEb1Lh5shYRjr7EEejj+KwpCTO0AoKVjWDBEpyn/AfpkI09WLXwNSuFHCb0r+o/Z9/KMNBjndKYeGEpD4SEAWCcahltFsEg5P32iRZ2dYqBJ0ksFfBVeZt6799K9RbxlsAxpDd2tEUAOC1HA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=KNZe5cBV; arc=none smtp.client-ip=209.85.208.43 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="KNZe5cBV" Received: by mail-ed1-f43.google.com with SMTP id 4fb4d7f45d1cf-6188b7949f6so3397427a12.3; Fri, 15 Aug 2025 00:05:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1755241520; x=1755846320; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=eCesnMus1323R3PUoKpOSIU4416dLvXBkdEmDTNu6E8=; b=KNZe5cBVjnHxkB+w1zN19KSBjaCgqAFpUV+R5gEcLrkulRehu2MMCOuiLfNQMwIS82 PatHK+f4MLP1tPEzPgmg99aRHWyHwwD1BHPhiu14nDy11gECU5COfClKhgLLLTRBpLVE dyCN3u054yWiRyAjcZzww4cpQubTxVLg6NGlkEZJucIdB55JrWrWJUfD/5tmrNC6poxZ Pu87dAzIYPmrUbBJtgRSfsnxw1oHc1HvNHqmguBjs45PcBDE5ush4GoD/NJRhkR8EJES 5mDlQFAI5+5Q3bfkGYccl2jCopeMRR3JqEnY4/5tMk/h1f/w3NC8ab4WtrII1gd/0Wp1 NNOQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1755241520; x=1755846320; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=eCesnMus1323R3PUoKpOSIU4416dLvXBkdEmDTNu6E8=; b=f6SKGNVC3byEawLnrMyJFd+8JaeHlpGV3rdHf3UTJ6M2vsFHfSuqi5yiv1alcAvWbU uyBSnr+2pEDKJbtYF7bO8qOsw8DlXjQh+RoVsm4BKcRUE0rQZlxpB8odX2nMEho3Cvl9 TmJe0Hne5nTbOEUnBCkUsWShGxt5Z2yWybq9O8Fzl2QXEks5Vzt0cxtrRCdbiXyDV+v4 fB9vSy+Tw3vrMuO5Xhfzy7v4Jlqaa1C4uUa0CqQVMEr1gmbdF/XpvZXq1wXxufNRJUrx FedlHl7LwVf7mr3SrqxxT0x2XsAIqs9a1/9d+XAHZLLwSB1oRY/OvAJc9GMahGTfVVmd zRfw== X-Forwarded-Encrypted: i=1; AJvYcCWgPuRMN9gIzxzJqBgD8rmZGxmFDocX971x3zAZazK/0tPWwyulIkj+EZy08NeL5Ux8EC3P4ryuZDjjeHR1@vger.kernel.org, AJvYcCXJtXRJtmbNtu8Kv7SUtdERU3sopQy3ytECyyqnkeUZk3CS93eEL0VWevk301KEHRGChX687FWq2Z1G@vger.kernel.org X-Gm-Message-State: AOJu0YxreSYMjfKLXLn039/ZSCxHIxChVtxsAAvVJUZPuoZMwiBUWrnm yM/DrXsR+/SHO2ULeIkq77Z8LHTutOYuJP43HXs9NChEigz/BTXH6MrfSf5Ilw== X-Gm-Gg: ASbGncuCZP3+Qw8a7JkqV57XTOqmKwvU9aWnsQZ7QZm/oIVxwE6zhy3MMvbdBjDThFO CPvzejZ9XeOFGYYrk6GNN1/JiibuW1BH+JKx+qRDSF3SzeqzN5GqSBh4+rjbmIOHPfEwSmgqbrY DIgysO1DFNHlGCDMhR09JlkD3UxBVqdnalyfemOSlYnHRbx95Pp9OTL4RWx84dV6uSOBSpBnNEv lk+6SBqxvfsEWFCgZhBymwaWOzxES1Z4uVWsGVOItq8NATsAYcQqGhXFwPfPIWDmaV9hUCr/hdP tEZ1Mi+gZh9GVXY7vaQK0qxusY/eaIppBvma5suSTJkItLFSJDTc6q18crSBATUWZrNVpK3WjdT kReOV9Oq/hipgj2/wCkgH8pxGvbFR6bcDf3tB5lNmmSKyZT6lWz7tt07d1oneFXXxKo1A8/k8Pg == X-Google-Smtp-Source: AGHT+IHk6g2BpBNq8WZlKk9li0KaPP25ro3Mpg1rVaQ4fnwPdqCnK3jEMcz0w40+lk585im/Mzwy4A== X-Received: by 2002:a17:907:608b:b0:af9:c400:d6ee with SMTP id a640c23a62f3a-afcdc41a526mr82099266b.61.1755241519628; Fri, 15 Aug 2025 00:05:19 -0700 (PDT) Received: from ivaylo-T580.. (91-139-201-119.stz.ddns.bulsat.com. [91.139.201.119]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-afcdcfcb2ddsm74269266b.74.2025.08.15.00.05.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Aug 2025 00:05:19 -0700 (PDT) From: Ivaylo Ivanov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar Cc: linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 4/4] arm64: dts: exynos2200: define all usi nodes Date: Fri, 15 Aug 2025 10:05:00 +0300 Message-ID: <20250815070500.3275491-5-ivo.ivanov.ivanov1@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250815070500.3275491-1-ivo.ivanov.ivanov1@gmail.com> References: <20250815070500.3275491-1-ivo.ivanov.ivanov1@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Universal Serial Interface (USI) supports three types of serial interfaces - uart, i2c and spi. Each protocol can work independently and configured using external configuration inputs. As each USI instance has access to 4 pins, there are multiple possible configurations: - the first 2 and the last 2 pins can be i2c (sda/scl) or uart (rx/tx) - the 4 pins can be used for 4 pin uart or spi For each group of 4 pins, there is one usi instance that can access all 4 pins, and a second usi instance that can be used to set the last 2 pins in i2c mode. Such configuration can be achieved by setting the mode property of usiX and usiX_i2c nodes correctly - if usiX is set to take up 2 pins, then usiX_i2c can be set to take the other 2. If usiX is set for 4 pins, then usiX_i2c should be left disabled. Define all the USI nodes from peric0 (usi4), peric1 (usi7-10), peric2 (usi0-6, usi11) and cmgp (usi0-6_cmgp, 2 pin usi7_cmgp) blocks, as well as their respective uart and i2c subnodes. Suffix labels for blocks in CMGP instances with _cmgpX, and follow the naming conventions from the vendor kernel to avoid confusion. Spi support will be added later on. Signed-off-by: Ivaylo Ivanov Reviewed-by: Sam Protsenko --- arch/arm64/boot/dts/exynos/exynos2200.dtsi | 1361 ++++++++++++++++++++ 1 file changed, 1361 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos2200.dtsi b/arch/arm64/boot/d= ts/exynos/exynos2200.dtsi index b3a8933a4..933ab7818 100644 --- a/arch/arm64/boot/dts/exynos/exynos2200.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos2200.dtsi @@ -7,6 +7,7 @@ =20 #include #include +#include =20 / { compatible =3D "samsung,exynos2200"; @@ -314,6 +315,76 @@ pinctrl_peric0: pinctrl@10430000 { reg =3D <0x10430000 0x1000>; }; =20 + usi4: usi@105000c0 { + compatible =3D "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg =3D <0x105000c0 0x20>; + ranges; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>, + <&cmu_peric0 CLK_DOUT_PERIC0_USI04>; + clock-names =3D "pclk", "ipclk"; + samsung,sysreg =3D <&syscon_peric0 0x1024>; + status =3D "disabled"; + + hsi2c_8: i2c@10500000 { + compatible =3D "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg =3D <0x10500000 0xc0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&cmu_peric0 CLK_DOUT_PERIC0_USI04>, + <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>; + clock-names =3D "hsi2c", "hsi2c_pclk"; + interrupts =3D ; + pinctrl-0 =3D <&hsi2c8_bus>; + pinctrl-names =3D "default"; + status =3D "disabled"; + }; + + serial_6: serial@10500000 { + compatible =3D "samsung,exynos2200-uart", "google,gs101-uart"; + reg =3D <0x10500000 0xc0>; + clocks =3D <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>, + <&cmu_peric0 CLK_DOUT_PERIC0_USI04>; + clock-names =3D "uart", "clk_uart_baud0"; + interrupts =3D ; + pinctrl-0 =3D <&uart6_bus_single>; + pinctrl-names =3D "default"; + samsung,uart-fifosize =3D <64>; + status =3D "disabled"; + }; + }; + + usi4_i2c: usi@105100c0 { + compatible =3D "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg =3D <0x105100c0 0x20>; + ranges; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>, + <&cmu_peric0 CLK_DOUT_PERIC0_I2C>; + clock-names =3D "pclk", "ipclk"; + samsung,mode =3D ; + samsung,sysreg =3D <&syscon_peric0 0x1024>; + status =3D "disabled"; + + hsi2c_9: i2c@10510000 { + compatible =3D "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg =3D <0x10510000 0xc0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&cmu_peric0 CLK_DOUT_PERIC0_I2C>, + <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>; + clock-names =3D "hsi2c", "hsi2c_pclk"; + interrupts =3D ; + pinctrl-0 =3D <&hsi2c9_bus>; + pinctrl-names =3D "default"; + status =3D "disabled"; + }; + }; + cmu_peric1: clock-controller@10700000 { compatible =3D "samsung,exynos2200-cmu-peric1"; reg =3D <0x10700000 0x8000>; @@ -336,6 +407,287 @@ pinctrl_peric1: pinctrl@10730000 { reg =3D <0x10730000 0x1000>; }; =20 + usi7: usi@109000c0 { + compatible =3D "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg =3D <0x109000c0 0x20>; + ranges; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>, + <&cmu_peric1 CLK_DOUT_PERIC1_USI07>; + clock-names =3D "pclk", "ipclk"; + samsung,sysreg =3D <&syscon_peric1 0x2030>; + status =3D "disabled"; + + hsi2c_14: i2c@10900000 { + compatible =3D "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg =3D <0x10900000 0xc0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&cmu_peric1 CLK_DOUT_PERIC1_USI07>, + <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>; + clock-names =3D "hsi2c", "hsi2c_pclk"; + interrupts =3D ; + pinctrl-0 =3D <&hsi2c14_bus>; + pinctrl-names =3D "default"; + status =3D "disabled"; + }; + + serial_9: serial@10900000 { + compatible =3D "samsung,exynos2200-uart", "google,gs101-uart"; + reg =3D <0x10900000 0xc0>; + clocks =3D <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>, + <&cmu_peric1 CLK_DOUT_PERIC1_USI07>; + clock-names =3D "uart", "clk_uart_baud0"; + interrupts =3D ; + pinctrl-0 =3D <&uart9_bus_single>; + pinctrl-names =3D "default"; + samsung,uart-fifosize =3D <64>; + status =3D "disabled"; + }; + }; + + usi7_i2c: usi@109100c0 { + compatible =3D "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg =3D <0x109100c0 0x20>; + ranges; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&cmu_peric1 CLK_MOUT_PERIC0_NOC_USER>, + <&cmu_peric1 CLK_DOUT_PERIC1_USI07_SPI_I2C>; + clock-names =3D "pclk", "ipclk"; + samsung,mode =3D ; + samsung,sysreg =3D <&syscon_peric1 0x2034>; + status =3D "disabled"; + + hsi2c_15: i2c@10910000 { + compatible =3D "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg =3D <0x10910000 0xc0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&cmu_peric1 CLK_DOUT_PERIC1_USI07_SPI_I2C>, + <&cmu_peric1 CLK_MOUT_PERIC0_NOC_USER>; + clock-names =3D "hsi2c", "hsi2c_pclk"; + interrupts =3D ; + pinctrl-0 =3D <&hsi2c15_bus>; + pinctrl-names =3D "default"; + status =3D "disabled"; + }; + }; + + usi8: usi@109200c0 { + compatible =3D "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg =3D <0x109200c0 0x20>; + ranges; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>, + <&cmu_peric1 CLK_DOUT_PERIC1_USI08>; + clock-names =3D "pclk", "ipclk"; + samsung,sysreg =3D <&syscon_peric1 0x2038>; + status =3D "disabled"; + + hsi2c_16: i2c@10920000 { + compatible =3D "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg =3D <0x10920000 0xc0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&cmu_peric1 CLK_DOUT_PERIC1_USI08>, + <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>; + clock-names =3D "hsi2c", "hsi2c_pclk"; + interrupts =3D ; + pinctrl-0 =3D <&hsi2c16_bus>; + pinctrl-names =3D "default"; + status =3D "disabled"; + }; + + serial_10: serial@10920000 { + compatible =3D "samsung,exynos2200-uart", "google,gs101-uart"; + reg =3D <0x10920000 0xc0>; + clocks =3D <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>, + <&cmu_peric1 CLK_DOUT_PERIC1_USI08>; + clock-names =3D "uart", "clk_uart_baud0"; + interrupts =3D ; + pinctrl-0 =3D <&uart10_bus_single>; + pinctrl-names =3D "default"; + samsung,uart-fifosize =3D <64>; + status =3D "disabled"; + }; + }; + + usi8_i2c: usi@109300c0 { + compatible =3D "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg =3D <0x109300c0 0x20>; + ranges; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&cmu_peric1 CLK_MOUT_PERIC0_NOC_USER>, + <&cmu_peric1 CLK_DOUT_PERIC1_USI08_SPI_I2C>; + clock-names =3D "pclk", "ipclk"; + samsung,mode =3D ; + samsung,sysreg =3D <&syscon_peric1 0x203c>; + status =3D "disabled"; + + hsi2c_17: i2c@10930000 { + compatible =3D "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg =3D <0x10930000 0xc0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&cmu_peric1 CLK_DOUT_PERIC1_USI08_SPI_I2C>, + <&cmu_peric1 CLK_MOUT_PERIC0_NOC_USER>; + clock-names =3D "hsi2c", "hsi2c_pclk"; + interrupts =3D ; + pinctrl-0 =3D <&hsi2c17_bus>; + pinctrl-names =3D "default"; + status =3D "disabled"; + }; + }; + + usi9: usi@109400c0 { + compatible =3D "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg =3D <0x109400c0 0x20>; + ranges; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>, + <&cmu_peric1 CLK_DOUT_PERIC1_USI09>; + clock-names =3D "pclk", "ipclk"; + samsung,sysreg =3D <&syscon_peric1 0x2040>; + status =3D "disabled"; + + hsi2c_18: i2c@10940000 { + compatible =3D "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg =3D <0x10940000 0xc0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&cmu_peric1 CLK_DOUT_PERIC1_USI09>, + <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>; + clock-names =3D "hsi2c", "hsi2c_pclk"; + interrupts =3D ; + pinctrl-0 =3D <&hsi2c18_bus>; + pinctrl-names =3D "default"; + status =3D "disabled"; + }; + + serial_11: serial@10940000 { + compatible =3D "samsung,exynos2200-uart", "google,gs101-uart"; + reg =3D <0x10940000 0xc0>; + clocks =3D <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>, + <&cmu_peric1 CLK_DOUT_PERIC1_USI09>; + clock-names =3D "uart", "clk_uart_baud0"; + interrupts =3D ; + pinctrl-0 =3D <&uart11_bus_single>; + pinctrl-names =3D "default"; + samsung,uart-fifosize =3D <64>; + status =3D "disabled"; + }; + }; + + usi9_i2c: usi@109500c0 { + compatible =3D "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg =3D <0x109500c0 0x20>; + ranges; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&cmu_peric1 CLK_MOUT_PERIC0_NOC_USER>, + <&cmu_peric1 CLK_DOUT_PERIC1_I2C>; + clock-names =3D "pclk", "ipclk"; + samsung,mode =3D ; + samsung,sysreg =3D <&syscon_peric1 0x2044>; + status =3D "disabled"; + + hsi2c_19: i2c@10950000 { + compatible =3D "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg =3D <0x10950000 0xc0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&cmu_peric1 CLK_DOUT_PERIC1_I2C>, + <&cmu_peric1 CLK_MOUT_PERIC0_NOC_USER>; + clock-names =3D "hsi2c", "hsi2c_pclk"; + interrupts =3D ; + pinctrl-0 =3D <&hsi2c19_bus>; + pinctrl-names =3D "default"; + status =3D "disabled"; + }; + }; + + usi10: usi@109600c0 { + compatible =3D "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg =3D <0x109600c0 0x20>; + ranges; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>, + <&cmu_peric1 CLK_DOUT_PERIC1_USI10>; + clock-names =3D "pclk", "ipclk"; + samsung,sysreg =3D <&syscon_peric1 0x2048>; + status =3D "disabled"; + + hsi2c_20: i2c@10960000 { + compatible =3D "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg =3D <0x10960000 0xc0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&cmu_peric1 CLK_DOUT_PERIC1_USI10>, + <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>; + clock-names =3D "hsi2c", "hsi2c_pclk"; + interrupts =3D ; + pinctrl-0 =3D <&hsi2c20_bus>; + pinctrl-names =3D "default"; + status =3D "disabled"; + }; + + serial_12: serial@10960000 { + compatible =3D "samsung,exynos2200-uart", "google,gs101-uart"; + reg =3D <0x10960000 0xc0>; + clocks =3D <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>, + <&cmu_peric1 CLK_DOUT_PERIC1_USI10>; + clock-names =3D "uart", "clk_uart_baud0"; + interrupts =3D ; + pinctrl-0 =3D <&uart12_bus_single>; + pinctrl-names =3D "default"; + samsung,uart-fifosize =3D <64>; + status =3D "disabled"; + }; + }; + + usi10_i2c: usi@109700c0 { + compatible =3D "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg =3D <0x109700c0 0x20>; + ranges; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&cmu_peric1 CLK_MOUT_PERIC0_NOC_USER>, + <&cmu_peric1 CLK_DOUT_PERIC1_I2C>; + clock-names =3D "pclk", "ipclk"; + samsung,mode =3D ; + samsung,sysreg =3D <&syscon_peric1 0x204c>; + status =3D "disabled"; + + hsi2c_21: i2c@10970000 { + compatible =3D "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg =3D <0x10970000 0xc0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&cmu_peric1 CLK_DOUT_PERIC1_I2C>, + <&cmu_peric1 CLK_MOUT_PERIC0_NOC_USER>; + clock-names =3D "hsi2c", "hsi2c_pclk"; + interrupts =3D ; + pinctrl-0 =3D <&hsi2c21_bus>; + pinctrl-names =3D "default"; + status =3D "disabled"; + }; + + }; + cmu_hsi0: clock-controller@10a00000 { compatible =3D "samsung,exynos2200-cmu-hsi0"; reg =3D <0x10a00000 0x8000>; @@ -458,6 +810,496 @@ pinctrl_peric2: pinctrl@11c30000 { reg =3D <0x11c30000 0x1000>; }; =20 + usi0: usi@11d000c0 { + compatible =3D "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg =3D <0x11d000c0 0x20>; + ranges; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_USI00>; + clock-names =3D "pclk", "ipclk"; + samsung,sysreg =3D <&syscon_peric2 0x2000>; + status =3D "disabled"; + + hsi2c_0: i2c@11d00000 { + compatible =3D "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg =3D <0x11d00000 0xc0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&cmu_peric2 CLK_DOUT_PERIC2_USI00>, + <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>; + clock-names =3D "hsi2c", "hsi2c_pclk"; + interrupts =3D ; + pinctrl-0 =3D <&hsi2c0_bus>; + pinctrl-names =3D "default"; + status =3D "disabled"; + }; + + serial_2: serial@11d00000 { + compatible =3D "samsung,exynos2200-uart", "google,gs101-uart"; + reg =3D <0x11d00000 0xc0>; + clocks =3D <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_USI00>; + clock-names =3D "uart", "clk_uart_baud0"; + interrupts =3D ; + pinctrl-0 =3D <&uart2_bus_single>; + pinctrl-names =3D "default"; + samsung,uart-fifosize =3D <64>; + status =3D "disabled"; + }; + }; + + usi0_i2c: usi@11d100c0 { + compatible =3D "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg =3D <0x11d100c0 0x20>; + ranges; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_USI00_SPI_I2C>; + clock-names =3D "pclk", "ipclk"; + samsung,mode =3D ; + samsung,sysreg =3D <&syscon_peric2 0x2004>; + status =3D "disabled"; + + hsi2c_1: i2c@11d10000 { + compatible =3D "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg =3D <0x11d10000 0xc0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&cmu_peric2 CLK_DOUT_PERIC2_USI00_SPI_I2C>, + <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>; + clock-names =3D "hsi2c", "hsi2c_pclk"; + interrupts =3D ; + pinctrl-0 =3D <&hsi2c1_bus>; + pinctrl-names =3D "default"; + status =3D "disabled"; + }; + }; + + usi1: usi@11d200c0 { + compatible =3D "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg =3D <0x11d200c0 0x20>; + ranges; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_USI01>; + clock-names =3D "pclk", "ipclk"; + samsung,sysreg =3D <&syscon_peric2 0x2008>; + status =3D "disabled"; + + hsi2c_2: i2c@11d20000 { + compatible =3D "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg =3D <0x11d20000 0xc0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&cmu_peric2 CLK_DOUT_PERIC2_USI01>, + <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>; + clock-names =3D "hsi2c", "hsi2c_pclk"; + interrupts =3D ; + pinctrl-0 =3D <&hsi2c2_bus>; + pinctrl-names =3D "default"; + status =3D "disabled"; + }; + + serial_3: serial@11d20000 { + compatible =3D "samsung,exynos2200-uart", "google,gs101-uart"; + reg =3D <0x11d20000 0xc0>; + clocks =3D <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_USI01>; + clock-names =3D "uart", "clk_uart_baud0"; + interrupts =3D ; + pinctrl-0 =3D <&uart3_bus_single>; + pinctrl-names =3D "default"; + samsung,uart-fifosize =3D <64>; + status =3D "disabled"; + }; + }; + + usi1_i2c: usi@11d300c0 { + compatible =3D "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg =3D <0x11d300c0 0x20>; + ranges; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_USI01_SPI_I2C>; + clock-names =3D "pclk", "ipclk"; + samsung,mode =3D ; + samsung,sysreg =3D <&syscon_peric2 0x200c>; + status =3D "disabled"; + + hsi2c_3: i2c@11d30000 { + compatible =3D "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg =3D <0x11d30000 0xc0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&cmu_peric2 CLK_DOUT_PERIC2_USI01_SPI_I2C>, + <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>; + clock-names =3D "hsi2c", "hsi2c_pclk"; + interrupts =3D ; + pinctrl-0 =3D <&hsi2c3_bus>; + pinctrl-names =3D "default"; + status =3D "disabled"; + }; + }; + + usi2: usi@11d400c0 { + compatible =3D "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg =3D <0x11d400c0 0x20>; + ranges; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_USI02>; + clock-names =3D "pclk", "ipclk"; + samsung,sysreg =3D <&syscon_peric2 0x2010>; + status =3D "disabled"; + + hsi2c_4: i2c@11d40000 { + compatible =3D "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg =3D <0x11d40000 0xc0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&cmu_peric2 CLK_DOUT_PERIC2_USI02>, + <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>; + clock-names =3D "hsi2c", "hsi2c_pclk"; + interrupts =3D ; + pinctrl-0 =3D <&hsi2c4_bus>; + pinctrl-names =3D "default"; + status =3D "disabled"; + }; + + serial_4: serial@11d40000 { + compatible =3D "samsung,exynos2200-uart", "google,gs101-uart"; + reg =3D <0x11d40000 0xc0>; + clocks =3D <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_USI02>; + clock-names =3D "uart", "clk_uart_baud0"; + interrupts =3D ; + pinctrl-0 =3D <&uart4_bus_single>; + pinctrl-names =3D "default"; + samsung,uart-fifosize =3D <256>; + status =3D "disabled"; + }; + }; + + usi2_i2c: usi@11d500c0 { + compatible =3D "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg =3D <0x11d500c0 0x20>; + ranges; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_I2C>; + clock-names =3D "pclk", "ipclk"; + samsung,mode =3D ; + samsung,sysreg =3D <&syscon_peric2 0x2014>; + status =3D "disabled"; + + hsi2c_5: i2c@11d50000 { + compatible =3D "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg =3D <0x11d50000 0xc0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&cmu_peric2 CLK_DOUT_PERIC2_I2C>, + <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>; + clock-names =3D "hsi2c", "hsi2c_pclk"; + interrupts =3D ; + pinctrl-0 =3D <&hsi2c5_bus>; + pinctrl-names =3D "default"; + status =3D "disabled"; + }; + }; + + usi3: usi@11d600c0 { + compatible =3D "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg =3D <0x11d600c0 0x20>; + ranges; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_USI03>; + clock-names =3D "pclk", "ipclk"; + samsung,sysreg =3D <&syscon_peric2 0x2018>; + status =3D "disabled"; + + hsi2c_6: i2c@11d60000 { + compatible =3D "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg =3D <0x11d60000 0xc0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&cmu_peric2 CLK_DOUT_PERIC2_USI03>, + <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>; + clock-names =3D "hsi2c", "hsi2c_pclk"; + interrupts =3D ; + pinctrl-0 =3D <&hsi2c6_bus>; + pinctrl-names =3D "default"; + status =3D "disabled"; + }; + + serial_5: serial@11d60000 { + compatible =3D "samsung,exynos2200-uart", "google,gs101-uart"; + reg =3D <0x11d60000 0xc0>; + clocks =3D <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_USI03>; + clock-names =3D "uart", "clk_uart_baud0"; + interrupts =3D ; + pinctrl-0 =3D <&uart5_bus_single>; + pinctrl-names =3D "default"; + samsung,uart-fifosize =3D <256>; + status =3D "disabled"; + }; + }; + + usi3_i2c: usi@11d700c0 { + compatible =3D "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg =3D <0x11d700c0 0x20>; + ranges; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_I2C>; + clock-names =3D "pclk", "ipclk"; + samsung,mode =3D ; + samsung,sysreg =3D <&syscon_peric2 0x201c>; + status =3D "disabled"; + + hsi2c_7: i2c@11d70000 { + compatible =3D "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg =3D <0x11d70000 0xc0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&cmu_peric2 CLK_DOUT_PERIC2_I2C>, + <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>; + clock-names =3D "hsi2c", "hsi2c_pclk"; + interrupts =3D ; + pinctrl-0 =3D <&hsi2c7_bus>; + pinctrl-names =3D "default"; + status =3D "disabled"; + }; + }; + + usi5_i2c: usi@11d800c0 { + compatible =3D "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg =3D <0x11d800c0 0x20>; + ranges; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_I2C>; + clock-names =3D "pclk", "ipclk"; + samsung,mode =3D ; + samsung,sysreg =3D <&syscon_peric2 0x102c>; + status =3D "disabled"; + + hsi2c_11: i2c@11d80000 { + compatible =3D "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg =3D <0x11d80000 0xc0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&cmu_peric2 CLK_DOUT_PERIC2_I2C>, + <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>; + clock-names =3D "hsi2c", "hsi2c_pclk"; + interrupts =3D ; + pinctrl-0 =3D <&hsi2c11_bus>; + pinctrl-names =3D "default"; + status =3D "disabled"; + }; + }; + + usi6_i2c: usi@11d900c0 { + compatible =3D "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg =3D <0x11d900c0 0x20>; + ranges; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_I2C>; + clock-names =3D "pclk", "ipclk"; + samsung,mode =3D ; + samsung,sysreg =3D <&syscon_peric2 0x1004>; + status =3D "disabled"; + + hsi2c_13: i2c@11d90000 { + compatible =3D "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg =3D <0x11d90000 0xc0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&cmu_peric2 CLK_DOUT_PERIC2_I2C>, + <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>; + clock-names =3D "hsi2c", "hsi2c_pclk"; + interrupts =3D ; + pinctrl-0 =3D <&hsi2c13_bus>; + pinctrl-names =3D "default"; + status =3D "disabled"; + }; + }; + + usi11: usi@11da00c0 { + compatible =3D "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg =3D <0x11da00c0 0x20>; + ranges; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_USI11>; + clock-names =3D "pclk", "ipclk"; + samsung,sysreg =3D <&syscon_peric2 0x1058>; + status =3D "disabled"; + + hsi2c_22: i2c@11da0000 { + compatible =3D "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg =3D <0x11da0000 0xc0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&cmu_peric2 CLK_DOUT_PERIC2_USI11>, + <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>; + clock-names =3D "hsi2c", "hsi2c_pclk"; + interrupts =3D ; + pinctrl-0 =3D <&hsi2c22_bus>; + pinctrl-names =3D "default"; + status =3D "disabled"; + }; + + serial_13: serial@11da0000 { + compatible =3D "samsung,exynos2200-uart", "google,gs101-uart"; + reg =3D <0x11da0000 0xc0>; + clocks =3D <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_USI11>; + clock-names =3D "uart", "clk_uart_baud0"; + interrupts =3D ; + pinctrl-0 =3D <&uart13_bus_single>; + pinctrl-names =3D "default"; + samsung,uart-fifosize =3D <64>; + status =3D "disabled"; + }; + }; + + usi11_i2c: usi@11db00c0 { + compatible =3D "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg =3D <0x11db00c0 0x20>; + ranges; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_I2C>; + clock-names =3D "pclk", "ipclk"; + samsung,mode =3D ; + samsung,sysreg =3D <&syscon_peric2 0x105c>; + status =3D "disabled"; + + hsi2c_23: i2c@11db0000 { + compatible =3D "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg =3D <0x11db0000 0xc0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&cmu_peric2 CLK_DOUT_PERIC2_I2C>, + <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>; + clock-names =3D "hsi2c", "hsi2c_pclk"; + interrupts =3D ; + pinctrl-0 =3D <&hsi2c23_bus>; + pinctrl-names =3D "default"; + status =3D "disabled"; + }; + }; + + usi5: usi@11dd00c0 { + compatible =3D "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg =3D <0x11dd00c0 0x20>; + ranges; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_USI05>; + clock-names =3D "pclk", "ipclk"; + samsung,sysreg =3D <&syscon_peric2 0x117c>; + status =3D "disabled"; + + hsi2c_10: i2c@11dd0000 { + compatible =3D "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg =3D <0x11dd0000 0xc0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&cmu_peric2 CLK_DOUT_PERIC2_USI05>, + <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>; + clock-names =3D "hsi2c", "hsi2c_pclk"; + interrupts =3D ; + pinctrl-0 =3D <&hsi2c10_bus>; + pinctrl-names =3D "default"; + status =3D "disabled"; + }; + + serial_7: serial@11dd0000 { + compatible =3D "samsung,exynos2200-uart", "google,gs101-uart"; + reg =3D <0x11dd0000 0xc0>; + clocks =3D <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_USI05>; + clock-names =3D "uart", "clk_uart_baud0"; + interrupts =3D ; + pinctrl-0 =3D <&uart7_bus_single>; + pinctrl-names =3D "default"; + samsung,uart-fifosize =3D <256>; + status =3D "disabled"; + }; + }; + + usi6: usi@11de00c0 { + compatible =3D "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg =3D <0x11de00c0 0x20>; + ranges; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_USI06>; + clock-names =3D "pclk", "ipclk"; + samsung,sysreg =3D <&syscon_peric2 0x1180>; + status =3D "disabled"; + + hsi2c_12: i2c@11de0000 { + compatible =3D "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg =3D <0x11de0000 0xc0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&cmu_peric2 CLK_DOUT_PERIC2_USI06>, + <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>; + clock-names =3D "hsi2c", "hsi2c_pclk"; + interrupts =3D ; + pinctrl-0 =3D <&hsi2c12_bus>; + pinctrl-names =3D "default"; + status =3D "disabled"; + }; + + serial_8: serial@11de0000 { + compatible =3D "samsung,exynos2200-uart", "google,gs101-uart"; + reg =3D <0x11de0000 0xc0>; + clocks =3D <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_USI06>; + clock-names =3D "uart", "clk_uart_baud0"; + interrupts =3D ; + pinctrl-0 =3D <&uart8_bus_single>; + pinctrl-names =3D "default"; + samsung,uart-fifosize =3D <64>; + status =3D "disabled"; + }; + }; + cmu_cmgp: clock-controller@14e00000 { compatible =3D "samsung,exynos2200-cmu-cmgp"; reg =3D <0x14e00000 0x8000>; @@ -485,6 +1327,525 @@ wakeup-interrupt-controller { }; }; =20 + usi_cmgp0: usi@14f000c0 { + compatible =3D "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg =3D <0x14f000c0 0x20>; + ranges; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_USI0>; + clock-names =3D "pclk", "ipclk"; + samsung,sysreg =3D <&syscon_cmgp 0x2000>; + status =3D "disabled"; + + hsi2c_24: i2c@14f00000 { + compatible =3D "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg =3D <0x14f00000 0xc0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&cmu_cmgp CLK_DOUT_CMGP_USI0>, + <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>; + clock-names =3D "hsi2c", "hsi2c_pclk"; + interrupts =3D ; + pinctrl-0 =3D <&hsi2c24_bus>; + pinctrl-names =3D "default"; + status =3D "disabled"; + }; + + serial_14: serial@14f00000 { + compatible =3D "samsung,exynos2200-uart", "google,gs101-uart"; + reg =3D <0x14f00000 0xc0>; + clocks =3D <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_USI0>; + clock-names =3D "uart", "clk_uart_baud0"; + interrupts =3D ; + pinctrl-0 =3D <&uart14_bus_single>; + pinctrl-names =3D "default"; + samsung,uart-fifosize =3D <64>; + status =3D "disabled"; + }; + }; + + usi_i2c_cmgp0: usi@14f100c0 { + compatible =3D "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg =3D <0x14f100c0 0x20>; + ranges; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_SPI_I2C0>; + clock-names =3D "pclk", "ipclk"; + samsung,mode =3D ; + samsung,sysreg =3D <&syscon_cmgp 0x2070>; + status =3D "disabled"; + + hsi2c_25: i2c@14f10000 { + compatible =3D "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg =3D <0x14f10000 0xc0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&cmu_cmgp CLK_DOUT_CMGP_SPI_I2C0>, + <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>; + clock-names =3D "hsi2c", "hsi2c_pclk"; + interrupts =3D ; + pinctrl-0 =3D <&hsi2c25_bus>; + pinctrl-names =3D "default"; + status =3D "disabled"; + }; + }; + + usi_cmgp1: usi@14f200c0 { + compatible =3D "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg =3D <0x14f200c0 0x20>; + ranges; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_USI1>; + clock-names =3D "pclk", "ipclk"; + samsung,sysreg =3D <&syscon_cmgp 0x2010>; + status =3D "disabled"; + + hsi2c_26: i2c@14f20000 { + compatible =3D "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg =3D <0x14f20000 0xc0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&cmu_cmgp CLK_DOUT_CMGP_USI1>, + <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>; + clock-names =3D "hsi2c", "hsi2c_pclk"; + interrupts =3D ; + pinctrl-0 =3D <&hsi2c26_bus>; + pinctrl-names =3D "default"; + status =3D "disabled"; + }; + + serial_15: serial@14f20000 { + compatible =3D "samsung,exynos2200-uart", "google,gs101-uart"; + reg =3D <0x14f20000 0xc0>; + clocks =3D <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_USI1>; + clock-names =3D "uart", "clk_uart_baud0"; + interrupts =3D ; + pinctrl-0 =3D <&uart15_bus_single>; + pinctrl-names =3D "default"; + samsung,uart-fifosize =3D <64>; + status =3D "disabled"; + }; + }; + + usi_i2c_cmgp1: usi@14f300c0 { + compatible =3D "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg =3D <0x14f300c0 0x20>; + ranges; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_SPI_I2C1>; + clock-names =3D "pclk", "ipclk"; + samsung,mode =3D ; + samsung,sysreg =3D <&syscon_cmgp 0x2074>; + status =3D "disabled"; + + hsi2c_27: i2c@14f30000 { + compatible =3D "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg =3D <0x14f30000 0xc0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&cmu_cmgp CLK_DOUT_CMGP_SPI_I2C1>, + <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>; + clock-names =3D "hsi2c", "hsi2c_pclk"; + interrupts =3D ; + pinctrl-0 =3D <&hsi2c27_bus>; + pinctrl-names =3D "default"; + status =3D "disabled"; + }; + }; + + usi_cmgp2: usi@14f400c0 { + compatible =3D "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg =3D <0x14f400c0 0x20>; + ranges; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_USI2>; + clock-names =3D "pclk", "ipclk"; + samsung,sysreg =3D <&syscon_cmgp 0x2020>; + status =3D "disabled"; + + hsi2c_28: i2c@14f40000 { + compatible =3D "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg =3D <0x14f40000 0xc0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&cmu_cmgp CLK_DOUT_CMGP_USI2>, + <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>; + clock-names =3D "hsi2c", "hsi2c_pclk"; + interrupts =3D ; + pinctrl-0 =3D <&hsi2c28_bus>; + pinctrl-names =3D "default"; + status =3D "disabled"; + }; + + serial_16: serial@14f40000 { + compatible =3D "samsung,exynos2200-uart", "google,gs101-uart"; + reg =3D <0x14f40000 0xc0>; + clocks =3D <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_USI2>; + clock-names =3D "uart", "clk_uart_baud0"; + interrupts =3D ; + pinctrl-0 =3D <&uart16_bus_single>; + pinctrl-names =3D "default"; + samsung,uart-fifosize =3D <64>; + status =3D "disabled"; + }; + }; + + usi_i2c_cmgp2: usi@14f500c0 { + compatible =3D "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg =3D <0x14f500c0 0x20>; + ranges; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_I2C>; + clock-names =3D "pclk", "ipclk"; + samsung,mode =3D ; + samsung,sysreg =3D <&syscon_cmgp 0x2024>; + status =3D "disabled"; + + hsi2c_29: i2c@14f50000 { + compatible =3D "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg =3D <0x14f50000 0xc0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&cmu_cmgp CLK_DOUT_CMGP_I2C>, + <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>; + clock-names =3D "hsi2c", "hsi2c_pclk"; + interrupts =3D ; + pinctrl-0 =3D <&hsi2c29_bus>; + pinctrl-names =3D "default"; + status =3D "disabled"; + }; + }; + + usi_cmgp3: usi@14f600c0 { + compatible =3D "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg =3D <0x14f600c0 0x20>; + ranges; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_USI3>; + clock-names =3D "pclk", "ipclk"; + samsung,sysreg =3D <&syscon_cmgp 0x2030>; + status =3D "disabled"; + + hsi2c_30: i2c@14f60000 { + compatible =3D "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg =3D <0x14f60000 0xc0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&cmu_cmgp CLK_DOUT_CMGP_USI3>, + <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>; + clock-names =3D "hsi2c", "hsi2c_pclk"; + interrupts =3D ; + pinctrl-0 =3D <&hsi2c30_bus>; + pinctrl-names =3D "default"; + status =3D "disabled"; + }; + + serial_17: serial@14f60000 { + compatible =3D "samsung,exynos2200-uart", "google,gs101-uart"; + reg =3D <0x14f60000 0xc0>; + clocks =3D <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_USI3>; + clock-names =3D "uart", "clk_uart_baud0"; + interrupts =3D ; + pinctrl-0 =3D <&uart17_bus_single>; + pinctrl-names =3D "default"; + samsung,uart-fifosize =3D <64>; + status =3D "disabled"; + }; + }; + + usi_i2c_cmgp3: usi@14f700c0 { + compatible =3D "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg =3D <0x14f700c0 0x20>; + ranges; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_I2C>; + clock-names =3D "pclk", "ipclk"; + samsung,mode =3D ; + samsung,sysreg =3D <&syscon_cmgp 0x2034>; + status =3D "disabled"; + + hsi2c_31: i2c@14f70000 { + compatible =3D "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg =3D <0x14f70000 0xc0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&cmu_cmgp CLK_DOUT_CMGP_I2C>, + <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>; + clock-names =3D "hsi2c", "hsi2c_pclk"; + interrupts =3D ; + pinctrl-0 =3D <&hsi2c31_bus>; + pinctrl-names =3D "default"; + status =3D "disabled"; + }; + }; + + usi_cmgp4: usi@14f800c0 { + compatible =3D "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg =3D <0x14f800c0 0x20>; + ranges; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_USI4>; + clock-names =3D "pclk", "ipclk"; + samsung,sysreg =3D <&syscon_cmgp 0x2040>; + status =3D "disabled"; + + hsi2c_32: i2c@14f80000 { + compatible =3D "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg =3D <0x14f80000 0xc0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&cmu_cmgp CLK_DOUT_CMGP_USI4>, + <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>; + clock-names =3D "hsi2c", "hsi2c_pclk"; + interrupts =3D ; + pinctrl-0 =3D <&hsi2c32_bus>; + pinctrl-names =3D "default"; + status =3D "disabled"; + }; + + serial_18: serial@14f80000 { + compatible =3D "samsung,exynos2200-uart", "google,gs101-uart"; + reg =3D <0x14f80000 0xc0>; + clocks =3D <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_USI4>; + clock-names =3D "uart", "clk_uart_baud0"; + interrupts =3D ; + pinctrl-0 =3D <&uart18_bus_single>; + pinctrl-names =3D "default"; + samsung,uart-fifosize =3D <64>; + status =3D "disabled"; + }; + }; + + usi_i2c_cmgp4: usi@14f900c0 { + compatible =3D "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg =3D <0x14f900c0 0x20>; + ranges; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_I2C>; + clock-names =3D "pclk", "ipclk"; + samsung,mode =3D ; + samsung,sysreg =3D <&syscon_cmgp 0x2044>; + status =3D "disabled"; + + hsi2c_33: i2c@14f90000 { + compatible =3D "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg =3D <0x14f90000 0xc0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&cmu_cmgp CLK_DOUT_CMGP_I2C>, + <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>; + clock-names =3D "hsi2c", "hsi2c_pclk"; + interrupts =3D ; + pinctrl-0 =3D <&hsi2c33_bus>; + pinctrl-names =3D "default"; + status =3D "disabled"; + }; + }; + + usi_cmgp5: usi@14fa00c0 { + compatible =3D "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg =3D <0x14fa00c0 0x20>; + ranges; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_USI5>; + clock-names =3D "pclk", "ipclk"; + samsung,sysreg =3D <&syscon_cmgp 0x2050>; + status =3D "disabled"; + + hsi2c_34: i2c@14fa0000 { + compatible =3D "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg =3D <0x14fa0000 0xc0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&cmu_cmgp CLK_DOUT_CMGP_USI5>, + <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>; + clock-names =3D "hsi2c", "hsi2c_pclk"; + interrupts =3D ; + pinctrl-0 =3D <&hsi2c34_bus>; + pinctrl-names =3D "default"; + status =3D "disabled"; + }; + + serial_19: serial@14fa0000 { + compatible =3D "samsung,exynos2200-uart", "google,gs101-uart"; + reg =3D <0x14fa0000 0xc0>; + clocks =3D <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_USI5>; + clock-names =3D "uart", "clk_uart_baud0"; + interrupts =3D ; + pinctrl-0 =3D <&uart19_bus_single>; + pinctrl-names =3D "default"; + samsung,uart-fifosize =3D <64>; + status =3D "disabled"; + }; + }; + + usi_i2c_cmgp5: usi@14fb00c0 { + compatible =3D "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg =3D <0x14fb00c0 0x20>; + ranges; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_I2C>; + clock-names =3D "pclk", "ipclk"; + samsung,mode =3D ; + samsung,sysreg =3D <&syscon_cmgp 0x2054>; + status =3D "disabled"; + + hsi2c_35: i2c@14fb0000 { + compatible =3D "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg =3D <0x14fb0000 0xc0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&cmu_cmgp CLK_DOUT_CMGP_I2C>, + <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>; + clock-names =3D "hsi2c", "hsi2c_pclk"; + interrupts =3D ; + pinctrl-0 =3D <&hsi2c35_bus>; + pinctrl-names =3D "default"; + status =3D "disabled"; + }; + }; + + usi_cmgp6: usi@14fc00c0 { + compatible =3D "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg =3D <0x14fc00c0 0x20>; + ranges; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_USI6>; + clock-names =3D "pclk", "ipclk"; + samsung,sysreg =3D <&syscon_cmgp 0x2060>; + status =3D "disabled"; + + hsi2c_36: i2c@14fc0000 { + compatible =3D "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg =3D <0x14fc0000 0xc0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&cmu_cmgp CLK_DOUT_CMGP_USI6>, + <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>; + clock-names =3D "hsi2c", "hsi2c_pclk"; + interrupts =3D ; + pinctrl-0 =3D <&hsi2c36_bus>; + pinctrl-names =3D "default"; + status =3D "disabled"; + }; + + serial_20: serial@14fc0000 { + compatible =3D "samsung,exynos2200-uart", "google,gs101-uart"; + reg =3D <0x14fc0000 0xc0>; + clocks =3D <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_USI6>; + clock-names =3D "uart", "clk_uart_baud0"; + interrupts =3D ; + pinctrl-0 =3D <&uart20_bus_single>; + pinctrl-names =3D "default"; + samsung,uart-fifosize =3D <64>; + status =3D "disabled"; + }; + }; + + usi_i2c_cmgp6: usi@14fd00c0 { + compatible =3D "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg =3D <0x14fd00c0 0x20>; + ranges; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_I2C>; + clock-names =3D "pclk", "ipclk"; + samsung,mode =3D ; + samsung,sysreg =3D <&syscon_cmgp 0x2064>; + status =3D "disabled"; + + hsi2c_37: i2c@14fd0000 { + compatible =3D "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg =3D <0x14fd0000 0xc0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&cmu_cmgp CLK_DOUT_CMGP_I2C>, + <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>; + clock-names =3D "hsi2c", "hsi2c_pclk"; + interrupts =3D ; + pinctrl-0 =3D <&hsi2c37_bus>; + pinctrl-names =3D "default"; + status =3D "disabled"; + }; + }; + + usi_i2c_cmgp7: usi@14fe00c0 { + compatible =3D "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg =3D <0x14fe00c0 0x20>; + ranges; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_I2C>; + clock-names =3D "pclk", "ipclk"; + samsung,mode =3D ; + samsung,sysreg =3D <&syscon_cmgp 0x2080>; + status =3D "disabled"; + + hsi2c_38: i2c@14fe0000 { + compatible =3D "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg =3D <0x14fe0000 0xc0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&cmu_cmgp CLK_DOUT_CMGP_I2C>, + <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>; + clock-names =3D "hsi2c", "hsi2c_pclk"; + interrupts =3D ; + pinctrl-0 =3D <&hsi2c38_bus>; + pinctrl-names =3D "default"; + status =3D "disabled"; + }; + }; + cmu_vts: clock-controller@15300000 { compatible =3D "samsung,exynos2200-cmu-vts"; reg =3D <0x15300000 0x8000>; --=20 2.43.0