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Peter Anvin" , David Woodhouse , Sean Christopherson , Peter Zijlstra , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v4 23/34] x86/cacheinfo: Pass a 'struct cpuinfo_x86' refrence to CPUID(0x4) code Date: Fri, 15 Aug 2025 09:02:16 +0200 Message-ID: <20250815070227.19981-24-darwi@linutronix.de> In-Reply-To: <20250815070227.19981-1-darwi@linutronix.de> References: <20250815070227.19981-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Prepare the CPUID(0x4) cache topology code for using parsed CPUID APIs instead of invoking direct CPUID queries. Since such an API requires a 'struct cpuinfo_x86' reference, trickle it from the 's populate_cache_leaves() x86 implementation down to fill_cpuid4_info() and its Intel-specific CPUID(0x4) code. No functional change intended. Suggested-by: Ingo Molnar Signed-off-by: Ahmed S. Darwish Link: https://lore.kernel.org/lkml/aBnEBbDATdE2LTGU@gmail.com --- arch/x86/kernel/cpu/cacheinfo.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinf= o.c index f837ccdec116..0ed5dd6d29ef 100644 --- a/arch/x86/kernel/cpu/cacheinfo.c +++ b/arch/x86/kernel/cpu/cacheinfo.c @@ -252,7 +252,7 @@ static int amd_fill_cpuid4_info(int index, struct _cpui= d4_info *id4) return cpuid4_info_fill_done(id4, eax, ebx, ecx); } =20 -static int intel_fill_cpuid4_info(int index, struct _cpuid4_info *id4) +static int intel_fill_cpuid4_info(struct cpuinfo_x86 *unused, int index, s= truct _cpuid4_info *id4) { union _cpuid4_leaf_eax eax; union _cpuid4_leaf_ebx ebx; @@ -264,13 +264,13 @@ static int intel_fill_cpuid4_info(int index, struct _= cpuid4_info *id4) return cpuid4_info_fill_done(id4, eax, ebx, ecx); } =20 -static int fill_cpuid4_info(int index, struct _cpuid4_info *id4) +static int fill_cpuid4_info(struct cpuinfo_x86 *c, int index, struct _cpui= d4_info *id4) { u8 cpu_vendor =3D boot_cpu_data.x86_vendor; =20 return (cpu_vendor =3D=3D X86_VENDOR_AMD || cpu_vendor =3D=3D X86_VENDOR_= HYGON) ? amd_fill_cpuid4_info(index, id4) : - intel_fill_cpuid4_info(index, id4); + intel_fill_cpuid4_info(c, index, id4); } =20 static int find_num_cache_leaves(struct cpuinfo_x86 *c) @@ -434,7 +434,7 @@ static bool intel_cacheinfo_0x4(struct cpuinfo_x86 *c) struct _cpuid4_info id4 =3D {}; int ret; =20 - ret =3D intel_fill_cpuid4_info(i, &id4); + ret =3D intel_fill_cpuid4_info(c, i, &id4); if (ret < 0) continue; =20 @@ -618,13 +618,14 @@ int populate_cache_leaves(unsigned int cpu) { struct cpu_cacheinfo *this_cpu_ci =3D get_cpu_cacheinfo(cpu); struct cacheinfo *ci =3D this_cpu_ci->info_list; + struct cpuinfo_x86 *c =3D &cpu_data(cpu); u8 cpu_vendor =3D boot_cpu_data.x86_vendor; struct amd_northbridge *nb =3D NULL; struct _cpuid4_info id4 =3D {}; int idx, ret; =20 for (idx =3D 0; idx < this_cpu_ci->num_leaves; idx++) { - ret =3D fill_cpuid4_info(idx, &id4); + ret =3D fill_cpuid4_info(c, idx, &id4); if (ret) return ret; =20 --=20 2.50.1