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Peter Anvin" , David Woodhouse , Sean Christopherson , Peter Zijlstra , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v4 21/34] x86/cpuid: Remove direct CPUID(0x2) query API Date: Fri, 15 Aug 2025 09:02:14 +0200 Message-ID: <20250815070227.19981-22-darwi@linutronix.de> In-Reply-To: <20250815070227.19981-1-darwi@linutronix.de> References: <20250815070227.19981-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" All call sites at x86/cpu and x86/cacheinfo has been switched from direct CPUID(0x2) access to parsed CPUID access. Remove the direct CPUID(0x2) query APIs at : cpuid_leaf_0x2() for_each_cpuid_0x2_desc() Rename the iterator macro: for_each_parsed_cpuid_0x2_desc() back to: for_each_cpuid_0x2_desc() since the "for_each_parsed_.." name and was just chosen to accommodate the transition from direct CPUID(0x2) access to parsed access. Signed-off-by: Ahmed S. Darwish --- arch/x86/include/asm/cpuid/api.h | 75 ++------------------------------ arch/x86/kernel/cpu/cacheinfo.c | 2 +- arch/x86/kernel/cpu/intel.c | 2 +- 3 files changed, 5 insertions(+), 74 deletions(-) diff --git a/arch/x86/include/asm/cpuid/api.h b/arch/x86/include/asm/cpuid/= api.h index b125e492d239..146498d5dbfa 100644 --- a/arch/x86/include/asm/cpuid/api.h +++ b/arch/x86/include/asm/cpuid/api.h @@ -213,75 +213,6 @@ static inline u32 cpuid_base_hypervisor(const char *si= g, u32 leaves) return 0; } =20 -/* - * CPUID(0x2) parsing: - */ - -/** - * cpuid_leaf_0x2() - Return sanitized CPUID(0x2) register output - * @regs: Output parameter - * - * Query CPUID(0x2) and store its output in @regs. Force set any - * invalid 1-byte descriptor returned by the hardware to zero (the NULL - * cache/TLB descriptor) before returning it to the caller. - * - * Use for_each_cpuid_0x2_desc() to iterate over the register output in - * parsed form. - */ -static inline void cpuid_leaf_0x2(union leaf_0x2_regs *regs) -{ - cpuid_read(0x2, regs); - - /* - * All Intel CPUs must report an iteration count of 1. In case - * of bogus hardware, treat all returned descriptors as NULL. - */ - if (regs->desc[0] !=3D 0x01) { - for (int i =3D 0; i < 4; i++) - regs->regv[i] =3D 0; - return; - } - - /* - * The most significant bit (MSB) of each register must be clear. - * If a register is invalid, replace its descriptors with NULL. - */ - for (int i =3D 0; i < 4; i++) { - if (regs->reg[i].invalid) - regs->regv[i] =3D 0; - } -} - -/** - * for_each_cpuid_0x2_desc() - Iterator for parsed CPUID(0x2) descriptors - * @_regs: CPUID(0x2) register output, as returned by cpuid_leaf_0x2() - * @_ptr: u8 pointer, for macro internal use only - * @_desc: Pointer to the parsed CPUID(0x2) descriptor at each iteration - * - * Loop over the 1-byte descriptors in the passed CPUID(0x2) output regist= ers - * @_regs. Provide the parsed information for each descriptor through @_d= esc. - * - * To handle cache-specific descriptors, switch on @_desc->c_type. For TLB - * descriptors, switch on @_desc->t_type. - * - * Example usage for cache descriptors:: - * - * const struct leaf_0x2_table *desc; - * union leaf_0x2_regs regs; - * u8 *ptr; - * - * cpuid_leaf_0x2(®s); - * for_each_cpuid_0x2_desc(regs, ptr, desc) { - * switch (desc->c_type) { - * ... - * } - * } - */ -#define for_each_cpuid_0x2_desc(_regs, _ptr, _desc) \ - for (_ptr =3D &(_regs).desc[1]; \ - _ptr < &(_regs).desc[16] && (_desc =3D &cpuid_0x2_table[*_ptr]); \ - _ptr++) - /* * CPUID(0x80000006) parsing: */ @@ -554,7 +485,7 @@ static inline bool cpuid_amd_hygon_has_l3_cache(void) */ =20 /** - * for_each_parsed_cpuid_0x2_desc() - Iterator for parsed CPUID(0x2) descr= iptors + * for_each_cpuid_0x2_desc() - Iterator for parsed CPUID(0x2) descriptors * @_regs: Leaf 0x2 register output, as returned by cpuid_leaf_regs() * @_ptr: u8 pointer, for macro internal use only * @_desc: Pointer to parsed descriptor information at each iteration @@ -576,13 +507,13 @@ static inline bool cpuid_amd_hygon_has_l3_cache(void) * // Handle error * } * - * for_each_parsed_cpuid_0x2_desc(regs, ptr, desc) { + * for_each_cpuid_0x2_desc(regs, ptr, desc) { * switch (desc->c_type) { * ... * } * } */ -#define for_each_parsed_cpuid_0x2_desc(_regs, _ptr, _desc) \ +#define for_each_cpuid_0x2_desc(_regs, _ptr, _desc) \ for (({ static_assert(sizeof(*_regs) =3D=3D sizeof(union leaf_0x2_regs));= }), \ _ptr =3D &((union leaf_0x2_regs *)(_regs))->desc[1]; \ _ptr < &((union leaf_0x2_regs *)(_regs))->desc[16] && (_desc =3D &cp= uid_0x2_table[*_ptr]);\ diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinf= o.c index 39cd6db4f702..f837ccdec116 100644 --- a/arch/x86/kernel/cpu/cacheinfo.c +++ b/arch/x86/kernel/cpu/cacheinfo.c @@ -389,7 +389,7 @@ static void intel_cacheinfo_0x2(struct cpuinfo_x86 *c) if (!regs) return; =20 - for_each_parsed_cpuid_0x2_desc(regs, ptr, desc) { + for_each_cpuid_0x2_desc(regs, ptr, desc) { switch (desc->c_type) { case CACHE_L1_INST: l1i +=3D desc->c_size; break; case CACHE_L1_DATA: l1d +=3D desc->c_size; break; diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index 5eab9135b144..06c249110c8b 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -717,7 +717,7 @@ static void intel_detect_tlb(struct cpuinfo_x86 *c) if (!regs) return; =20 - for_each_parsed_cpuid_0x2_desc(regs, ptr, desc) + for_each_cpuid_0x2_desc(regs, ptr, desc) intel_tlb_lookup(desc); } =20 --=20 2.50.1