From nobody Sat Oct 4 14:35:16 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 11C4E2BE7AC for ; Fri, 15 Aug 2025 07:05:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755241509; cv=none; b=FscoFEtXk0fyqC79mpeRZHOS5cKsHbhYXfs5NS93u7zn/lCOYQgt2DQ4i4af4wFGsVwEaTIBTTzoHfEEiB1YSDenGh5Y5ekr7mBGkBPXKDPDStUnfSjUx0pk/S6A9I+QMKtsKPNT03K2k28AQ+2eXH6oCxkMaoOlIxMjuvk6i3g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755241509; c=relaxed/simple; bh=SYRZmFM3Ioa0y0H9EeRaz2/V19DLQSJh6KQlg7ks8hM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=GnogOn1ShBRKygdAp8+8ieY5AsHsQxUBZJteTTvjyLCzBrQaNIvmr628MeFjYdQbrzKyg3RcWjNI4i3Fh3tWgbXz6lg1cHtZwO5XWl3oVsMz0qptejKfGLGBjYeylpY4Txf4Fz1d9Hfo+1IPwGUrBe0E597HCdPuVbvpSsKml/k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=kIpU3FqV; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=NH0bE7lT; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="kIpU3FqV"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="NH0bE7lT" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1755241506; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=d8Xp1mFPuuaOTq+ytYDakiRoJMAib8ShAL5vVh6jiIQ=; b=kIpU3FqViZ2EFUjb8sLgNDY4119QhW/tcxlOG9Eww4JplVrD6Y61gB2bOICrAG0tybakFw ngdVTF2ckYGai0cjyhJph+UVWfTxuMg+cG6WpYKtxv9nQa2tbmxO149aoiIqnXV7Nj2DU5 MK/cN+poYU/Iotaj17nG5mMVNgHCht6ScCtpNWDrCaRzo5yADTiGIlrslyBAGxnYPLNTuR d4oW+L3I3Vcg7C9XLXpapL+jDc8Qrvz8vj9H+SHrpYgpuv2g+NyEy4eMG1yzPRdXvod23x vQ3EMv3CEXbEqFEMi/wss36F4wKDA2eNHceqFibr6UCCTe261T+vwt60oqEAsQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1755241506; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=d8Xp1mFPuuaOTq+ytYDakiRoJMAib8ShAL5vVh6jiIQ=; b=NH0bE7lTDlbdzxT/+tBnMBAaoqkcNu1P72dNL845emBw+0KOiQQ/qmz5mCMXC3dK0hQtwN NdEF2vm99DWrdQBg== To: Borislav Petkov , Ingo Molnar , Dave Hansen Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , David Woodhouse , Sean Christopherson , Peter Zijlstra , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v4 01/34] x86/cpuid: Remove transitional header Date: Fri, 15 Aug 2025 09:01:54 +0200 Message-ID: <20250815070227.19981-2-darwi@linutronix.de> In-Reply-To: <20250815070227.19981-1-darwi@linutronix.de> References: <20250815070227.19981-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" All CPUID call sites were updated at commit: 968e30006807 ("x86/cpuid: Set as the main CPUID heade= r") to include instead of . The header was still retained as a wrapper, just in case some new code in -next started using it. Now that everything is merged to Linus' tree, remove the header. Signed-off-by: Ahmed S. Darwish --- arch/x86/include/asm/cpuid.h | 8 -------- 1 file changed, 8 deletions(-) delete mode 100644 arch/x86/include/asm/cpuid.h diff --git a/arch/x86/include/asm/cpuid.h b/arch/x86/include/asm/cpuid.h deleted file mode 100644 index d5749b25fa10..000000000000 --- a/arch/x86/include/asm/cpuid.h +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ - -#ifndef _ASM_X86_CPUID_H -#define _ASM_X86_CPUID_H - -#include - -#endif /* _ASM_X86_CPUID_H */ --=20 2.50.1 From nobody Sat Oct 4 14:35:16 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 460DC2D062B for ; Fri, 15 Aug 2025 07:05:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755241512; cv=none; b=DvW2KiFMxbRz1CiUyaB0W7R1cSt4DTYf/q0KKXD6p4lbVXFCN8+tgK8BgOWmV1nOVg4/XjoQFqYM/A96ttvrTobJCpvVy43ebEkdHW+vHykIVLoRATmJO0CCUzz7evH0xAXN0g/QtSGFkXSVSH/GXOt7KB2Jtnm+B77nPFgI0OQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755241512; c=relaxed/simple; bh=l8ElQRAT1Hszveqk+X21k8IIcIZzDZmj+WUDZsTY2C0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=GdMKJTKQrQBQKj/D4VapEs9T3j0tEyIWGjKD1F6o+YyVww8UwHQIPRYaEO9M2V2xZX3oFpFmw0qoMPKIz4/P+Nkmw2V/wJkqkl9BtFMzvNFadtxLsgrny7ZPJt/R3MLGKnQ3TNADYo7v5Xe/gDrSRiF2gf4S8OPzzWwL62nSZec= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=KKFSdjy6; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=0MrI4Vpb; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="KKFSdjy6"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="0MrI4Vpb" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1755241509; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ILIDCHvFGsvZiwtpyNNKEdOsJOlcSIX04cXR7l0HOA4=; b=KKFSdjy6QMK6FOURu5VL1RdQxBQrrA8slVU2xXVOIPqA9vNTzvrF7y4fO8jzBH4oS2/3LT nV6pWmmsJVonwEqtDWzPdDwWKsEemYO3y6Sy277+8BXewim5ufLyzWw2x/a/98eAPxKmm/ 4JpuCCj2zCHwWxAf2FPKmla2siJFP6Vw9CzNXJxbEti0PCirKSiflXmFvLppbyUZCHiwDP fpZg7hFppvU7Sfr5ZaGh7fG5uY+cufNnPlAWIWrzReyquXS5RQLvMudPdKOVuQ27VJgy5P 6a/A2vrC945Y+itk5L/HHgG16SdzpaOjhg6Q55qgtqKHP/Ys1EoxOIHq3D7fEg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1755241509; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ILIDCHvFGsvZiwtpyNNKEdOsJOlcSIX04cXR7l0HOA4=; b=0MrI4Vpbh4vFB208XxcGcGZ8HxCDl75Qpc2yfMWGskzA5GdpRAhKhibcGObKhDvHZXVIHX 22dA0Do8zAwjtPBg== To: Borislav Petkov , Ingo Molnar , Dave Hansen Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , David Woodhouse , Sean Christopherson , Peter Zijlstra , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v4 02/34] ASoC: Intel: avs: Include CPUID header at file scope Date: Fri, 15 Aug 2025 09:01:55 +0200 Message-ID: <20250815070227.19981-3-darwi@linutronix.de> In-Reply-To: <20250815070227.19981-1-darwi@linutronix.de> References: <20250815070227.19981-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Commit cbe37a4d2b3c ("ASoC: Intel: avs: Configure basefw on TGL-based platform= s") includes the main CPUID header from within a C function. This works by luck and forbids valid refactorings inside the CPUID header. Include the CPUID header at file scope instead. Note, for the CPUID(0x15) leaf number, use CPUID_LEAF_TSC instead of defining a custom local macro for it. Signed-off-by: Ahmed S. Darwish Acked-by: Cezary Rojewski --- sound/soc/intel/avs/tgl.c | 25 ++++++++++++++++--------- 1 file changed, 16 insertions(+), 9 deletions(-) diff --git a/sound/soc/intel/avs/tgl.c b/sound/soc/intel/avs/tgl.c index 9dbb3ad0954a..cf19d3a7ced2 100644 --- a/sound/soc/intel/avs/tgl.c +++ b/sound/soc/intel/avs/tgl.c @@ -10,8 +10,6 @@ #include "avs.h" #include "messages.h" =20 -#define CPUID_TSC_LEAF 0x15 - static int avs_tgl_dsp_core_power(struct avs_dev *adev, u32 core_mask, boo= l power) { core_mask &=3D AVS_MAIN_CORE_MASK; @@ -39,22 +37,31 @@ static int avs_tgl_dsp_core_stall(struct avs_dev *adev,= u32 core_mask, bool stal return avs_dsp_core_stall(adev, core_mask, stall); } =20 +#ifdef CONFIG_X86 +#include +static unsigned int intel_crystal_freq_hz(void) +{ + return cpuid_ecx(CPUID_LEAF_TSC); +} +#else +static unsigned int intel_crystal_freq_hz(void) +{ + return 0; +} +#endif /* !CONFIG_X86 */ + static int avs_tgl_config_basefw(struct avs_dev *adev) { + unsigned int freq =3D intel_crystal_freq_hz(); struct pci_dev *pci =3D adev->base.pci; struct avs_bus_hwid hwid; int ret; -#ifdef CONFIG_X86 - unsigned int ecx; =20 -#include - ecx =3D cpuid_ecx(CPUID_TSC_LEAF); - if (ecx) { - ret =3D avs_ipc_set_fw_config(adev, 1, AVS_FW_CFG_XTAL_FREQ_HZ, sizeof(e= cx), &ecx); + if (freq) { + ret =3D avs_ipc_set_fw_config(adev, 1, AVS_FW_CFG_XTAL_FREQ_HZ, sizeof(f= req), &freq); if (ret) return AVS_IPC_RET(ret); } -#endif =20 hwid.device =3D pci->device; hwid.subsystem =3D pci->subsystem_vendor | (pci->subsystem_device << 16); --=20 2.50.1 From nobody Sat Oct 4 14:35:16 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CA4882D0C78 for ; Fri, 15 Aug 2025 07:05:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755241517; cv=none; b=u3VZtPBoYf0VT4Ev82z9UWs2QdhG6OAVxI76mYOBR9JmRD3IX//IHhMRVY3+KvOJEIWNjTktawAP/j6ROpDvACExIS4DcZvsBnNi1Qke8bYrPLdssxl5sbzh2PhvURYVLNo+RyrbfIhEa9kBvlK9PXKNJKHsCN5gk40BwrMgA1E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755241517; c=relaxed/simple; bh=/DElHWqB38KDW+ogsTZWC3oUCQoGoRX07kASWeVSyzY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=aA+snY22jRYFjohRcoG6SZNakJc2fRS37ep8ZPamSf1YgaFt4eIw2l4NdsUA7yCKiz9F6MixUUq4Sf3EjXJs0m/QGJWoObrPe88VSGr/6PvrYGUZkvZX3ReeMmZfleTtrB7AsHewuLgFVcKlqiwxCa5TgmAd9o/bFrAKabMr/ZU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=e6AiqFBK; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=RUxCyMjW; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="e6AiqFBK"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="RUxCyMjW" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1755241513; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=GEIHxDk1Shc6EBM2c8snKDuQu1H8/rgYtnnrLAj9r3o=; b=e6AiqFBKJemYEVfAVR8bYquQayAZQpYeNjg+62pv+Oc2sOgFDCj/WQLIgSJqnxo2wRRiLp CN5hRwm+yAVWZgJvYrTr67Vv3o0z1dYrl6Z3y6N+ezlnROs37n5b4sDaIWlUeGU9VT5HL9 36dEzScBl6eWot3SPvx8lVHa0aMrXGmDZ6kDm/7kRuFqRl2ugzuO7CXSyoD0bqpgg3Vs2w r+QGsYn9qDDPleKz/p1eEUBgxXr068VBRDk+HtWBuMnt+FYB5LoHe7imvpHVr1hYSMpGV2 vmCZ8JBs2lyXSru9JkuGlT7envZrTPCwPnDg+9he4VbhC8rQhcKiVWqx6OHImg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1755241513; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=GEIHxDk1Shc6EBM2c8snKDuQu1H8/rgYtnnrLAj9r3o=; b=RUxCyMjWjdUDCrCaJSpKUYwbbgAN1GQlAKSIntJr5a9lByprcv6QKDX987yY/2lhIPkcQX UQiGuzNYuBBOjZBg== To: Borislav Petkov , Ingo Molnar , Dave Hansen Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , David Woodhouse , Sean Christopherson , Peter Zijlstra , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v4 03/34] treewide: Explicitly include the x86 CPUID headers Date: Fri, 15 Aug 2025 09:01:56 +0200 Message-ID: <20250815070227.19981-4-darwi@linutronix.de> In-Reply-To: <20250815070227.19981-1-darwi@linutronix.de> References: <20250815070227.19981-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Modify all CPUID call sites which implicitly include any of the CPUID headers to explicitly include them instead. For arch/x86/kvm/reverse_cpuid.h, just include since it references the CPUID_EAX..EDX symbols without using any of the CPUID APIs. Note, adding explicit CPUID includes for all call sites allows removing the include from next. This way, the CPUID API header can include at a later step without introducing a circular dependency. Signed-off-by: Ahmed S. Darwish --- arch/x86/boot/compressed/pgtable_64.c | 1 + arch/x86/boot/startup/sme.c | 1 + arch/x86/coco/tdx/tdx.c | 1 + arch/x86/events/amd/core.c | 2 ++ arch/x86/events/amd/ibs.c | 1 + arch/x86/events/amd/lbr.c | 2 ++ arch/x86/events/amd/power.c | 3 +++ arch/x86/events/amd/uncore.c | 1 + arch/x86/events/intel/core.c | 1 + arch/x86/events/intel/lbr.c | 1 + arch/x86/events/zhaoxin/core.c | 1 + arch/x86/include/asm/acrn.h | 2 ++ arch/x86/include/asm/microcode.h | 1 + arch/x86/include/asm/xen/hypervisor.h | 1 + arch/x86/kernel/apic/apic.c | 1 + arch/x86/kernel/cpu/amd.c | 1 + arch/x86/kernel/cpu/centaur.c | 1 + arch/x86/kernel/cpu/hygon.c | 1 + arch/x86/kernel/cpu/mce/core.c | 1 + arch/x86/kernel/cpu/mce/inject.c | 1 + arch/x86/kernel/cpu/microcode/amd.c | 1 + arch/x86/kernel/cpu/microcode/core.c | 1 + arch/x86/kernel/cpu/microcode/intel.c | 1 + arch/x86/kernel/cpu/mshyperv.c | 1 + arch/x86/kernel/cpu/resctrl/core.c | 1 + arch/x86/kernel/cpu/resctrl/monitor.c | 1 + arch/x86/kernel/cpu/scattered.c | 1 + arch/x86/kernel/cpu/sgx/driver.c | 3 +++ arch/x86/kernel/cpu/sgx/main.c | 3 +++ arch/x86/kernel/cpu/topology_amd.c | 1 + arch/x86/kernel/cpu/topology_common.c | 1 + arch/x86/kernel/cpu/topology_ext.c | 1 + arch/x86/kernel/cpu/transmeta.c | 3 +++ arch/x86/kernel/cpu/vmware.c | 1 + arch/x86/kernel/cpu/zhaoxin.c | 1 + arch/x86/kernel/cpuid.c | 1 + arch/x86/kernel/jailhouse.c | 1 + arch/x86/kernel/kvm.c | 1 + arch/x86/kernel/paravirt.c | 1 + arch/x86/kvm/mmu/mmu.c | 1 + arch/x86/kvm/mmu/spte.c | 1 + arch/x86/kvm/reverse_cpuid.h | 2 ++ arch/x86/kvm/svm/sev.c | 1 + arch/x86/kvm/svm/svm.c | 1 + arch/x86/kvm/vmx/pmu_intel.c | 1 + arch/x86/kvm/vmx/sgx.c | 1 + arch/x86/kvm/vmx/vmx.c | 1 + arch/x86/mm/pti.c | 1 + arch/x86/pci/xen.c | 2 +- arch/x86/xen/enlighten_hvm.c | 1 + arch/x86/xen/pmu.c | 1 + arch/x86/xen/time.c | 1 + drivers/char/agp/efficeon-agp.c | 1 + drivers/cpufreq/longrun.c | 1 + drivers/cpufreq/powernow-k7.c | 2 +- drivers/cpufreq/powernow-k8.c | 1 + drivers/cpufreq/speedstep-lib.c | 1 + drivers/firmware/efi/libstub/x86-5lvl.c | 1 + drivers/gpu/drm/gma500/mmu.c | 2 ++ drivers/hwmon/fam15h_power.c | 1 + drivers/hwmon/k10temp.c | 2 ++ drivers/hwmon/k8temp.c | 1 + drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c | 1 + drivers/ras/amd/fmpm.c | 1 + drivers/thermal/intel/intel_hfi.c | 1 + drivers/thermal/intel/x86_pkg_temp_thermal.c | 1 + drivers/virt/acrn/hsm.c | 1 + drivers/xen/events/events_base.c | 1 + drivers/xen/grant-table.c | 1 + drivers/xen/xenbus/xenbus_xs.c | 3 +++ 70 files changed, 86 insertions(+), 2 deletions(-) diff --git a/arch/x86/boot/compressed/pgtable_64.c b/arch/x86/boot/compress= ed/pgtable_64.c index bdd26050dff7..d94d98595780 100644 --- a/arch/x86/boot/compressed/pgtable_64.c +++ b/arch/x86/boot/compressed/pgtable_64.c @@ -2,6 +2,7 @@ #include "misc.h" #include #include +#include #include #include #include "../string.h" diff --git a/arch/x86/boot/startup/sme.c b/arch/x86/boot/startup/sme.c index 70ea1748c0a7..1b1bcb41bf23 100644 --- a/arch/x86/boot/startup/sme.c +++ b/arch/x86/boot/startup/sme.c @@ -42,6 +42,7 @@ #include #include #include +#include #include #include =20 diff --git a/arch/x86/coco/tdx/tdx.c b/arch/x86/coco/tdx/tdx.c index 7b2833705d47..168388be3a3e 100644 --- a/arch/x86/coco/tdx/tdx.c +++ b/arch/x86/coco/tdx/tdx.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/x86/events/amd/core.c b/arch/x86/events/amd/core.c index b20661b8621d..d28d45ceb707 100644 --- a/arch/x86/events/amd/core.c +++ b/arch/x86/events/amd/core.c @@ -7,8 +7,10 @@ #include #include #include + #include #include +#include #include #include =20 diff --git a/arch/x86/events/amd/ibs.c b/arch/x86/events/amd/ibs.c index 112f43b23ebf..0c7848e6149e 100644 --- a/arch/x86/events/amd/ibs.c +++ b/arch/x86/events/amd/ibs.c @@ -15,6 +15,7 @@ #include =20 #include +#include #include =20 #include "../perf_event.h" diff --git a/arch/x86/events/amd/lbr.c b/arch/x86/events/amd/lbr.c index d24da377df77..5b437dc8e4ce 100644 --- a/arch/x86/events/amd/lbr.c +++ b/arch/x86/events/amd/lbr.c @@ -1,5 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 #include + +#include #include #include =20 diff --git a/arch/x86/events/amd/power.c b/arch/x86/events/amd/power.c index dad42790cf7d..744dffa42dee 100644 --- a/arch/x86/events/amd/power.c +++ b/arch/x86/events/amd/power.c @@ -10,8 +10,11 @@ #include #include #include + #include +#include #include + #include "../perf_event.h" =20 /* Event code: LSB 8 bits, passed in attr->config any other bit is reserve= d. */ diff --git a/arch/x86/events/amd/uncore.c b/arch/x86/events/amd/uncore.c index e8b6af199c73..c602542f3a36 100644 --- a/arch/x86/events/amd/uncore.c +++ b/arch/x86/events/amd/uncore.c @@ -16,6 +16,7 @@ #include =20 #include +#include #include =20 #define NUM_COUNTERS_NB 4 diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index c2fb729c270e..ebbcdf82b494 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -17,6 +17,7 @@ #include =20 #include +#include #include #include #include diff --git a/arch/x86/events/intel/lbr.c b/arch/x86/events/intel/lbr.c index 7aa59966e7c3..0d1ec3651735 100644 --- a/arch/x86/events/intel/lbr.c +++ b/arch/x86/events/intel/lbr.c @@ -3,6 +3,7 @@ #include =20 #include +#include #include #include =20 diff --git a/arch/x86/events/zhaoxin/core.c b/arch/x86/events/zhaoxin/core.c index 4bdfcf091200..6ed644fe89aa 100644 --- a/arch/x86/events/zhaoxin/core.c +++ b/arch/x86/events/zhaoxin/core.c @@ -13,6 +13,7 @@ #include =20 #include +#include #include #include #include diff --git a/arch/x86/include/asm/acrn.h b/arch/x86/include/asm/acrn.h index fab11192c60a..db42b477c41d 100644 --- a/arch/x86/include/asm/acrn.h +++ b/arch/x86/include/asm/acrn.h @@ -2,6 +2,8 @@ #ifndef _ASM_X86_ACRN_H #define _ASM_X86_ACRN_H =20 +#include + /* * This CPUID returns feature bitmaps in EAX. * Guest VM uses this to detect the appropriate feature bit. diff --git a/arch/x86/include/asm/microcode.h b/arch/x86/include/asm/microc= ode.h index 8b41f26f003b..645e65ac1586 100644 --- a/arch/x86/include/asm/microcode.h +++ b/arch/x86/include/asm/microcode.h @@ -3,6 +3,7 @@ #define _ASM_X86_MICROCODE_H =20 #include +#include =20 struct cpu_signature { unsigned int sig; diff --git a/arch/x86/include/asm/xen/hypervisor.h b/arch/x86/include/asm/x= en/hypervisor.h index c2fc7869b996..7c596cebfb78 100644 --- a/arch/x86/include/asm/xen/hypervisor.h +++ b/arch/x86/include/asm/xen/hypervisor.h @@ -37,6 +37,7 @@ extern struct shared_info *HYPERVISOR_shared_info; extern struct start_info *xen_start_info; =20 #include +#include #include =20 #define XEN_SIGNATURE "XenVMMXenVMM" diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c index d73ba5a7b623..42045b7200ac 100644 --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -63,6 +63,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index a5ece6ebe8a7..61e858cf5b23 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/x86/kernel/cpu/centaur.c b/arch/x86/kernel/cpu/centaur.c index a3b55db35c96..cc5a390dcd07 100644 --- a/arch/x86/kernel/cpu/centaur.c +++ b/arch/x86/kernel/cpu/centaur.c @@ -5,6 +5,7 @@ =20 #include #include +#include #include #include #include diff --git a/arch/x86/kernel/cpu/hygon.c b/arch/x86/kernel/cpu/hygon.c index 2154f12766fb..75ad7eb1301a 100644 --- a/arch/x86/kernel/cpu/hygon.c +++ b/arch/x86/kernel/cpu/hygon.c @@ -10,6 +10,7 @@ =20 #include #include +#include #include #include #include diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index 4da4eab56c81..2b0da00b9d4b 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -48,6 +48,7 @@ =20 #include #include +#include #include #include #include diff --git a/arch/x86/kernel/cpu/mce/inject.c b/arch/x86/kernel/cpu/mce/inj= ect.c index d02c4f556cd0..42c82c14c48a 100644 --- a/arch/x86/kernel/cpu/mce/inject.c +++ b/arch/x86/kernel/cpu/mce/inject.c @@ -26,6 +26,7 @@ =20 #include #include +#include #include #include #include diff --git a/arch/x86/kernel/cpu/microcode/amd.c b/arch/x86/kernel/cpu/micr= ocode/amd.c index 097e39327942..eddb665b2db2 100644 --- a/arch/x86/kernel/cpu/microcode/amd.c +++ b/arch/x86/kernel/cpu/microcode/amd.c @@ -34,6 +34,7 @@ =20 #include #include +#include #include #include #include diff --git a/arch/x86/kernel/cpu/microcode/core.c b/arch/x86/kernel/cpu/mic= rocode/core.c index b92e09a87c69..f3b433d90e0d 100644 --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -34,6 +34,7 @@ =20 #include #include +#include #include #include #include diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/mi= crocode/intel.c index 371ca6eac00e..dacfbffe4cd2 100644 --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -22,6 +22,7 @@ #include =20 #include +#include #include #include #include diff --git a/arch/x86/kernel/cpu/mshyperv.c b/arch/x86/kernel/cpu/mshyperv.c index c78f860419d6..b397c1385ebd 100644 --- a/arch/x86/kernel/cpu/mshyperv.c +++ b/arch/x86/kernel/cpu/mshyperv.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resct= rl/core.c index 187d527ef73b..c1dd1a3d4b38 100644 --- a/arch/x86/kernel/cpu/resctrl/core.c +++ b/arch/x86/kernel/cpu/resctrl/core.c @@ -22,6 +22,7 @@ #include =20 #include +#include #include #include #include "internal.h" diff --git a/arch/x86/kernel/cpu/resctrl/monitor.c b/arch/x86/kernel/cpu/re= sctrl/monitor.c index c261558276cd..5dffb9453d77 100644 --- a/arch/x86/kernel/cpu/resctrl/monitor.c +++ b/arch/x86/kernel/cpu/resctrl/monitor.c @@ -21,6 +21,7 @@ #include =20 #include +#include #include =20 #include "internal.h" diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattere= d.c index b4a1f6732a3a..54b98b326f33 100644 --- a/arch/x86/kernel/cpu/scattered.c +++ b/arch/x86/kernel/cpu/scattered.c @@ -6,6 +6,7 @@ =20 #include #include +#include #include =20 #include "cpu.h" diff --git a/arch/x86/kernel/cpu/sgx/driver.c b/arch/x86/kernel/cpu/sgx/dri= ver.c index 7f8d1e11dbee..f0c0a001bce6 100644 --- a/arch/x86/kernel/cpu/sgx/driver.c +++ b/arch/x86/kernel/cpu/sgx/driver.c @@ -6,7 +6,10 @@ #include #include #include + +#include #include + #include "driver.h" #include "encl.h" =20 diff --git a/arch/x86/kernel/cpu/sgx/main.c b/arch/x86/kernel/cpu/sgx/main.c index 2de01b379aa3..00bf42f4c536 100644 --- a/arch/x86/kernel/cpu/sgx/main.c +++ b/arch/x86/kernel/cpu/sgx/main.c @@ -14,8 +14,11 @@ #include #include #include + +#include #include #include + #include "driver.h" #include "encl.h" #include "encls.h" diff --git a/arch/x86/kernel/cpu/topology_amd.c b/arch/x86/kernel/cpu/topol= ogy_amd.c index 843b1655ab45..abc6f5a7a486 100644 --- a/arch/x86/kernel/cpu/topology_amd.c +++ b/arch/x86/kernel/cpu/topology_amd.c @@ -2,6 +2,7 @@ #include =20 #include +#include #include #include #include diff --git a/arch/x86/kernel/cpu/topology_common.c b/arch/x86/kernel/cpu/to= pology_common.c index b5a5e1411469..b8c55f025b7e 100644 --- a/arch/x86/kernel/cpu/topology_common.c +++ b/arch/x86/kernel/cpu/topology_common.c @@ -6,6 +6,7 @@ #include #include #include +#include #include =20 #include "cpu.h" diff --git a/arch/x86/kernel/cpu/topology_ext.c b/arch/x86/kernel/cpu/topol= ogy_ext.c index 467b0326bf1a..eb915c73895f 100644 --- a/arch/x86/kernel/cpu/topology_ext.c +++ b/arch/x86/kernel/cpu/topology_ext.c @@ -2,6 +2,7 @@ #include =20 #include +#include #include #include =20 diff --git a/arch/x86/kernel/cpu/transmeta.c b/arch/x86/kernel/cpu/transmet= a.c index 42c939827621..1fdcd69c625c 100644 --- a/arch/x86/kernel/cpu/transmeta.c +++ b/arch/x86/kernel/cpu/transmeta.c @@ -3,8 +3,11 @@ #include #include #include + #include +#include #include + #include "cpu.h" =20 static void early_init_transmeta(struct cpuinfo_x86 *c) diff --git a/arch/x86/kernel/cpu/vmware.c b/arch/x86/kernel/cpu/vmware.c index cb3f900c46fc..fe181620f8f6 100644 --- a/arch/x86/kernel/cpu/vmware.c +++ b/arch/x86/kernel/cpu/vmware.c @@ -32,6 +32,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/x86/kernel/cpu/zhaoxin.c b/arch/x86/kernel/cpu/zhaoxin.c index 89b1c8a70fe8..cfcfb6221e3f 100644 --- a/arch/x86/kernel/cpu/zhaoxin.c +++ b/arch/x86/kernel/cpu/zhaoxin.c @@ -4,6 +4,7 @@ =20 #include #include +#include #include =20 #include "cpu.h" diff --git a/arch/x86/kernel/cpuid.c b/arch/x86/kernel/cpuid.c index dae436253de4..cbd04b677fd1 100644 --- a/arch/x86/kernel/cpuid.c +++ b/arch/x86/kernel/cpuid.c @@ -37,6 +37,7 @@ #include #include =20 +#include #include #include =20 diff --git a/arch/x86/kernel/jailhouse.c b/arch/x86/kernel/jailhouse.c index 9e9a591a5fec..f58ce9220e0f 100644 --- a/arch/x86/kernel/jailhouse.c +++ b/arch/x86/kernel/jailhouse.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/x86/kernel/kvm.c b/arch/x86/kernel/kvm.c index 8ae750cde0c6..f89e3fea5e97 100644 --- a/arch/x86/kernel/kvm.c +++ b/arch/x86/kernel/kvm.c @@ -39,6 +39,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/x86/kernel/paravirt.c b/arch/x86/kernel/paravirt.c index ab3e172dcc69..15f608f057ac 100644 --- a/arch/x86/kernel/paravirt.c +++ b/arch/x86/kernel/paravirt.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/x86/kvm/mmu/mmu.c b/arch/x86/kvm/mmu/mmu.c index 6e838cb6c9e1..024d8990b1a7 100644 --- a/arch/x86/kvm/mmu/mmu.c +++ b/arch/x86/kvm/mmu/mmu.c @@ -52,6 +52,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/x86/kvm/mmu/spte.c b/arch/x86/kvm/mmu/spte.c index df31039b5d63..86053e52ca4f 100644 --- a/arch/x86/kvm/mmu/spte.c +++ b/arch/x86/kvm/mmu/spte.c @@ -15,6 +15,7 @@ #include "x86.h" #include "spte.h" =20 +#include #include #include #include diff --git a/arch/x86/kvm/reverse_cpuid.h b/arch/x86/kvm/reverse_cpuid.h index c53b92379e6e..77bdc3fe3fc5 100644 --- a/arch/x86/kvm/reverse_cpuid.h +++ b/arch/x86/kvm/reverse_cpuid.h @@ -3,8 +3,10 @@ #define ARCH_X86_KVM_REVERSE_CPUID_H =20 #include + #include #include +#include =20 /* * Define a KVM-only feature flag. diff --git a/arch/x86/kvm/svm/sev.c b/arch/x86/kvm/svm/sev.c index 2fbdebf79fbb..f703d48a76b6 100644 --- a/arch/x86/kvm/svm/sev.c +++ b/arch/x86/kvm/svm/sev.c @@ -23,6 +23,7 @@ =20 #include #include +#include #include #include #include diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index d9931c6c4bc6..fcb780352ac9 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -41,6 +41,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c index 0b173602821b..c3c43c15bc5a 100644 --- a/arch/x86/kvm/vmx/pmu_intel.c +++ b/arch/x86/kvm/vmx/pmu_intel.c @@ -15,6 +15,7 @@ #include #include #include +#include #include "x86.h" #include "cpuid.h" #include "lapic.h" diff --git a/arch/x86/kvm/vmx/sgx.c b/arch/x86/kvm/vmx/sgx.c index df1d0cf76947..29a1f8e3be60 100644 --- a/arch/x86/kvm/vmx/sgx.c +++ b/arch/x86/kvm/vmx/sgx.c @@ -2,6 +2,7 @@ /* Copyright(c) 2021 Intel Corporation. */ #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt =20 +#include #include #include =20 diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index aa157fe5b7b3..4b21cace955f 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -34,6 +34,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/x86/mm/pti.c b/arch/x86/mm/pti.c index b10d4d131dce..f45fd1482c86 100644 --- a/arch/x86/mm/pti.c +++ b/arch/x86/mm/pti.c @@ -31,6 +31,7 @@ =20 #include #include +#include #include #include #include diff --git a/arch/x86/pci/xen.c b/arch/x86/pci/xen.c index b8755cde2419..6acfbdbaf4d5 100644 --- a/arch/x86/pci/xen.c +++ b/arch/x86/pci/xen.c @@ -18,6 +18,7 @@ #include #include #include +#include =20 #include =20 @@ -583,4 +584,3 @@ int __init pci_xen_initial_domain(void) return 0; } #endif - diff --git a/arch/x86/xen/enlighten_hvm.c b/arch/x86/xen/enlighten_hvm.c index fe57ff85d004..bd57259a02e6 100644 --- a/arch/x86/xen/enlighten_hvm.c +++ b/arch/x86/xen/enlighten_hvm.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include =20 diff --git a/arch/x86/xen/pmu.c b/arch/x86/xen/pmu.c index 8f89ce0b67e3..5f50a3ee08f5 100644 --- a/arch/x86/xen/pmu.c +++ b/arch/x86/xen/pmu.c @@ -2,6 +2,7 @@ #include #include =20 +#include #include #include #include diff --git a/arch/x86/xen/time.c b/arch/x86/xen/time.c index 96521b1874ac..d935cc1f2896 100644 --- a/arch/x86/xen/time.c +++ b/arch/x86/xen/time.c @@ -17,6 +17,7 @@ #include #include =20 +#include #include #include #include diff --git a/drivers/char/agp/efficeon-agp.c b/drivers/char/agp/efficeon-ag= p.c index 0d25bbdc7e6a..4d0b7d7c0aad 100644 --- a/drivers/char/agp/efficeon-agp.c +++ b/drivers/char/agp/efficeon-agp.c @@ -27,6 +27,7 @@ #include #include #include +#include #include "agp.h" #include "intel-agp.h" =20 diff --git a/drivers/cpufreq/longrun.c b/drivers/cpufreq/longrun.c index 1caaec7c280b..f3aaca0496a4 100644 --- a/drivers/cpufreq/longrun.c +++ b/drivers/cpufreq/longrun.c @@ -14,6 +14,7 @@ #include #include #include +#include =20 static struct cpufreq_driver longrun_driver; =20 diff --git a/drivers/cpufreq/powernow-k7.c b/drivers/cpufreq/powernow-k7.c index 31039330a3ba..ee122aafa56a 100644 --- a/drivers/cpufreq/powernow-k7.c +++ b/drivers/cpufreq/powernow-k7.c @@ -29,6 +29,7 @@ #include /* Needed for recalibrate_cpu_khz() */ #include #include +#include =20 #ifdef CONFIG_X86_POWERNOW_K7_ACPI #include @@ -691,4 +692,3 @@ MODULE_LICENSE("GPL"); =20 late_initcall(powernow_init); module_exit(powernow_exit); - diff --git a/drivers/cpufreq/powernow-k8.c b/drivers/cpufreq/powernow-k8.c index f7512b4e923e..84d7a737203b 100644 --- a/drivers/cpufreq/powernow-k8.c +++ b/drivers/cpufreq/powernow-k8.c @@ -39,6 +39,7 @@ =20 #include #include +#include =20 #include #include diff --git a/drivers/cpufreq/speedstep-lib.c b/drivers/cpufreq/speedstep-li= b.c index 0b66df4ed513..b3fe873103a8 100644 --- a/drivers/cpufreq/speedstep-lib.c +++ b/drivers/cpufreq/speedstep-lib.c @@ -15,6 +15,7 @@ #include #include =20 +#include #include #include #include "speedstep-lib.h" diff --git a/drivers/firmware/efi/libstub/x86-5lvl.c b/drivers/firmware/efi= /libstub/x86-5lvl.c index f1c5fb45d5f7..029ad80cf0b4 100644 --- a/drivers/firmware/efi/libstub/x86-5lvl.c +++ b/drivers/firmware/efi/libstub/x86-5lvl.c @@ -2,6 +2,7 @@ #include =20 #include +#include #include #include =20 diff --git a/drivers/gpu/drm/gma500/mmu.c b/drivers/gpu/drm/gma500/mmu.c index e6753282e70e..4d2aba31a78c 100644 --- a/drivers/gpu/drm/gma500/mmu.c +++ b/drivers/gpu/drm/gma500/mmu.c @@ -7,6 +7,8 @@ #include #include =20 +#include + #include "mmu.h" #include "psb_drv.h" #include "psb_reg.h" diff --git a/drivers/hwmon/fam15h_power.c b/drivers/hwmon/fam15h_power.c index 8ecebea53651..e200c7b7a698 100644 --- a/drivers/hwmon/fam15h_power.c +++ b/drivers/hwmon/fam15h_power.c @@ -19,6 +19,7 @@ #include #include #include +#include #include =20 MODULE_DESCRIPTION("AMD Family 15h CPU processor power monitor"); diff --git a/drivers/hwmon/k10temp.c b/drivers/hwmon/k10temp.c index babf2413d666..12115654689a 100644 --- a/drivers/hwmon/k10temp.c +++ b/drivers/hwmon/k10temp.c @@ -20,7 +20,9 @@ #include #include #include + #include +#include #include =20 MODULE_DESCRIPTION("AMD Family 10h+ CPU core temperature monitor"); diff --git a/drivers/hwmon/k8temp.c b/drivers/hwmon/k8temp.c index 2b80ac410cd1..53241164570e 100644 --- a/drivers/hwmon/k8temp.c +++ b/drivers/hwmon/k8temp.c @@ -15,6 +15,7 @@ #include #include #include +#include =20 #define TEMP_FROM_REG(val) (((((val) >> 16) & 0xff) - 49) * 1000) #define REG_TEMP 0xe4 diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c b/drivers/ne= t/ethernet/stmicro/stmmac/dwmac-intel.c index ea33ae39be6b..7612759c7267 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c @@ -6,6 +6,7 @@ #include #include #include +#include #include "dwmac-intel.h" #include "dwmac4.h" #include "stmmac.h" diff --git a/drivers/ras/amd/fmpm.c b/drivers/ras/amd/fmpm.c index 8877c6ff64c4..416a14bbd714 100644 --- a/drivers/ras/amd/fmpm.c +++ b/drivers/ras/amd/fmpm.c @@ -52,6 +52,7 @@ #include =20 #include +#include #include =20 #include "../debugfs.h" diff --git a/drivers/thermal/intel/intel_hfi.c b/drivers/thermal/intel/inte= l_hfi.c index bd2fca7dc017..c910cc563d9d 100644 --- a/drivers/thermal/intel/intel_hfi.c +++ b/drivers/thermal/intel/intel_hfi.c @@ -41,6 +41,7 @@ #include #include =20 +#include #include =20 #include "intel_hfi.h" diff --git a/drivers/thermal/intel/x86_pkg_temp_thermal.c b/drivers/thermal= /intel/x86_pkg_temp_thermal.c index 3fc679b6f11b..80f98e4ae61f 100644 --- a/drivers/thermal/intel/x86_pkg_temp_thermal.c +++ b/drivers/thermal/intel/x86_pkg_temp_thermal.c @@ -20,6 +20,7 @@ #include =20 #include +#include #include =20 #include "thermal_interrupt.h" diff --git a/drivers/virt/acrn/hsm.c b/drivers/virt/acrn/hsm.c index e4e196abdaac..67119f9da449 100644 --- a/drivers/virt/acrn/hsm.c +++ b/drivers/virt/acrn/hsm.c @@ -16,6 +16,7 @@ #include =20 #include +#include #include =20 #include "acrn_drv.h" diff --git a/drivers/xen/events/events_base.c b/drivers/xen/events/events_b= ase.c index 41309d38f78c..4d847dcd6d76 100644 --- a/drivers/xen/events/events_base.c +++ b/drivers/xen/events/events_base.c @@ -40,6 +40,7 @@ #include =20 #ifdef CONFIG_X86 +#include #include #include #include diff --git a/drivers/xen/grant-table.c b/drivers/xen/grant-table.c index 04a6b470b15d..ae3e384c2d1b 100644 --- a/drivers/xen/grant-table.c +++ b/drivers/xen/grant-table.c @@ -59,6 +59,7 @@ #include #include #ifdef CONFIG_X86 +#include #include #endif #include diff --git a/drivers/xen/xenbus/xenbus_xs.c b/drivers/xen/xenbus/xenbus_xs.c index 3c9da446b85d..6fc6f5d54da5 100644 --- a/drivers/xen/xenbus/xenbus_xs.c +++ b/drivers/xen/xenbus/xenbus_xs.c @@ -47,6 +47,9 @@ #include #include #include +#ifdef CONFIG_X86 +#include +#endif #include #include #include "xenbus.h" --=20 2.50.1 From nobody Sat Oct 4 14:35:16 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C4A9E2D12F6 for ; Fri, 15 Aug 2025 07:05:18 +0000 (UTC) Authentication-Results: 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Peter Anvin" , David Woodhouse , Sean Christopherson , Peter Zijlstra , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v4 04/34] x86/cpu: : Do not include the CPUID API header Date: Fri, 15 Aug 2025 09:01:57 +0200 Message-ID: <20250815070227.19981-5-darwi@linutronix.de> In-Reply-To: <20250815070227.19981-1-darwi@linutronix.de> References: <20250815070227.19981-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" includes the main CPUID API header but it does not need it. Remove the include. Note, this allows the CPUID API header to include at a later step, which is needed for the upcoming CPUID model and parser, without introducing a circular dependency. Note, all call sites which implicitly included the CPUID API header through have been already modified to explicitly include the CPUID API instead. Signed-off-by: Ahmed S. Darwish --- arch/x86/include/asm/processor.h | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/proces= sor.h index bde58f6510ac..910e36b0c00d 100644 --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -16,7 +16,6 @@ struct vm86; #include #include #include -#include #include #include #include --=20 2.50.1 From nobody Sat Oct 4 14:35:16 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1631E2D3732 for ; Fri, 15 Aug 2025 07:05:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755241523; cv=none; b=SZssv2OgC7rYkNaL4YmHpVfoI+fN2xgCm/VYfPkuNcYpnFy6qLCubqhQbE0hZrn8VHrQL4Y5s+SD1sr9L+cYW3RJe2G8OBPdfW4IfCTexd0nyoVK8rhmFrbmxC6wO5MnyhXVP5zGKKqIRCRPeU1kPUNA0GVIVCQDVUCy8DusAhc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755241523; c=relaxed/simple; bh=emCbkD5SJ7g7eTyk/TsxVRiOZeLr+hHfnrtYkkpEdwQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=gSrKdGYY+0YlINgTtt1GaTI4x3agbGlm6wxIyYY98tPEnvm3FbtwiBlMAuFIymfTmMNsnTy3CAG6WwGK7yNzVNlCNC0IXfPcEWPE31W3+kHhjoaen2r20JhFZsqHrMepgDMwTtRjl10KXIuMsd+XVpQkv0vhTGtI00AbbD/tyGk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=HsZpiVsZ; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=CiQSU4M5; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="HsZpiVsZ"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="CiQSU4M5" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1755241520; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=2OQWpXu22RzlPo6dYJzx0xMunRTzP2P4ZZ0VxRA6gJQ=; b=HsZpiVsZOvO7p2hGjjtt2y+LQGzSiC61mqHVNDaXnQaKrdD0N6BLqSaq61tofTP2JzrnA1 GRnpLBIDtWIbh5FLu+Ds2mCdhpso1/suWJ5TaGITUo4fuKoyjs//Z4VyGEIL+a/R7QBcxC qp7pwjJkkV6Oja1RS0DBaTLUhW6YsDOVwNbuqHP/0V/Tn/t3KchXpgRwqC1HUsS4dYNAvm lCBmVgYTbmmv/UX/LWuMGM1AAmrc4ITAal3Drk5QhBd0wqnwLxdVlLXNnm5mD3VTsPZ7pL PLzTiGXgESMeDusoPSSswWnkyryvEln+svVov0HJ7Iw5JR/lzLvkjqpimI5jZA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1755241520; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=2OQWpXu22RzlPo6dYJzx0xMunRTzP2P4ZZ0VxRA6gJQ=; b=CiQSU4M58q7UwAtjI2biskdUTDpfdVcr8JR639VeJWxwM5tReJXSTfOWhCfKkRJcbskbmG XT0CTx7JKgv18bAQ== To: Borislav Petkov , Ingo Molnar , Dave Hansen Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , David Woodhouse , Sean Christopherson , Peter Zijlstra , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v4 05/34] x86/cpuid: Rename cpuid_leaf()/cpuid_subleaf() APIs Date: Fri, 15 Aug 2025 09:01:58 +0200 Message-ID: <20250815070227.19981-6-darwi@linutronix.de> In-Reply-To: <20250815070227.19981-1-darwi@linutronix.de> References: <20250815070227.19981-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" A new CPUID model will be added where its APIs will be designated as the "official" CPUID API. Free the cpuid_leaf() and cpuid_subleaf() function names for that model. Rename them accordingly to cpuid_read() and cpuid_read_subleaf(). Note, for kernel/cpuid.c, rename its local file operations read function from cpuid_read() to cpuid_read_f() so that it does not conflict with the new names. No functional change. Signed-off-by: Ahmed S. Darwish --- arch/x86/include/asm/cpuid/api.h | 6 +++--- arch/x86/kernel/cpu/topology_amd.c | 2 +- arch/x86/kernel/cpu/topology_ext.c | 2 +- arch/x86/kernel/cpuid.c | 5 ++--- 4 files changed, 7 insertions(+), 8 deletions(-) diff --git a/arch/x86/include/asm/cpuid/api.h b/arch/x86/include/asm/cpuid/= api.h index 44fa82e1267c..2b9750cc8a75 100644 --- a/arch/x86/include/asm/cpuid/api.h +++ b/arch/x86/include/asm/cpuid/api.h @@ -131,12 +131,12 @@ static inline void __cpuid_read(u32 leaf, u32 subleaf= , u32 *regs) __cpuid(regs + CPUID_EAX, regs + CPUID_EBX, regs + CPUID_ECX, regs + CPUI= D_EDX); } =20 -#define cpuid_subleaf(leaf, subleaf, regs) { \ +#define cpuid_read_subleaf(leaf, subleaf, regs) { \ static_assert(sizeof(*(regs)) =3D=3D 16); \ __cpuid_read(leaf, subleaf, (u32 *)(regs)); \ } =20 -#define cpuid_leaf(leaf, regs) { \ +#define cpuid_read(leaf, regs) { \ static_assert(sizeof(*(regs)) =3D=3D 16); \ __cpuid_read(leaf, 0, (u32 *)(regs)); \ } @@ -228,7 +228,7 @@ static inline u32 cpuid_base_hypervisor(const char *sig= , u32 leaves) */ static inline void cpuid_leaf_0x2(union leaf_0x2_regs *regs) { - cpuid_leaf(0x2, regs); + cpuid_read(0x2, regs); =20 /* * All Intel CPUs must report an iteration count of 1. In case diff --git a/arch/x86/kernel/cpu/topology_amd.c b/arch/x86/kernel/cpu/topol= ogy_amd.c index abc6f5a7a486..c6bedae12a7e 100644 --- a/arch/x86/kernel/cpu/topology_amd.c +++ b/arch/x86/kernel/cpu/topology_amd.c @@ -80,7 +80,7 @@ static bool parse_8000_001e(struct topo_scan *tscan, bool= has_topoext) if (!boot_cpu_has(X86_FEATURE_TOPOEXT)) return false; =20 - cpuid_leaf(0x8000001e, &leaf); + cpuid_read(0x8000001e, &leaf); =20 tscan->c->topo.initial_apicid =3D leaf.ext_apic_id; =20 diff --git a/arch/x86/kernel/cpu/topology_ext.c b/arch/x86/kernel/cpu/topol= ogy_ext.c index eb915c73895f..60dfaa02ffd0 100644 --- a/arch/x86/kernel/cpu/topology_ext.c +++ b/arch/x86/kernel/cpu/topology_ext.c @@ -71,7 +71,7 @@ static inline bool topo_subleaf(struct topo_scan *tscan, = u32 leaf, u32 subleaf, default: return false; } =20 - cpuid_subleaf(leaf, subleaf, &sl); + cpuid_read_subleaf(leaf, subleaf, &sl); =20 if (!sl.num_processors || sl.type =3D=3D INVALID_TYPE) return false; diff --git a/arch/x86/kernel/cpuid.c b/arch/x86/kernel/cpuid.c index cbd04b677fd1..b55fe9c7359a 100644 --- a/arch/x86/kernel/cpuid.c +++ b/arch/x86/kernel/cpuid.c @@ -59,8 +59,7 @@ static void cpuid_smp_cpuid(void *cmd_block) complete(&cmd->done); } =20 -static ssize_t cpuid_read(struct file *file, char __user *buf, - size_t count, loff_t *ppos) +static ssize_t cpuid_read_f(struct file *file, char __user *buf, size_t co= unt, loff_t *ppos) { char __user *tmp =3D buf; struct cpuid_regs_done cmd; @@ -120,7 +119,7 @@ static int cpuid_open(struct inode *inode, struct file = *file) static const struct file_operations cpuid_fops =3D { .owner =3D THIS_MODULE, .llseek =3D no_seek_end_llseek, - .read =3D cpuid_read, + .read =3D cpuid_read_f, .open =3D cpuid_open, }; =20 --=20 2.50.1 From nobody Sat Oct 4 14:35:16 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 211E42D5A14 for ; Fri, 15 Aug 2025 07:05:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755241529; cv=none; b=ZPh6P4yRsCJ7I/RvSjt5jI7MBHsiMpevYfl8l7Y1qF3DKF2X7ARFx6+/kndIzhmSXkkBl5yQ776UtA30qvbn28vyJ0eshrVY43hJnsRfzeGkqngBGfhdz/FL4emV26Whwjr02veLQPhNdOHhbiam7gRYN4ZzIvEBba94LCbAyPI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755241529; c=relaxed/simple; bh=uTyc4pLkpTQG57msy566bPWREi7/juIfVcoSLE3yJa0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=lsbcPSQQ9bLcC7ROpgK2p+2ioR/QVco1Pvj+uc5UTyJ4X733S2eLbRjtio3uoFZJVWwLRb8S+rtchHlBS00lCLFwH6NbTKYKwM29lIaJECrTzL6rd6rRSnthDgf3N20KzbmrdLhmnWXGP0O2upmNkeXfmhkBVZdHImN8ldjF1ew= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=ZHAeqMGz; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=D7QKbXMm; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="ZHAeqMGz"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="D7QKbXMm" From: "Ahmed S. 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Peter Anvin" , David Woodhouse , Sean Christopherson , Peter Zijlstra , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v4 06/34] x86/cpuid: Introduce Date: Fri, 15 Aug 2025 09:01:59 +0200 Message-ID: <20250815070227.19981-7-darwi@linutronix.de> In-Reply-To: <20250815070227.19981-1-darwi@linutronix.de> References: <20250815070227.19981-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" To centralize CPUID access across the x86 subsystem, introduce . It is generated by the x86-cpuid-db project and includes detailed C99 bitfield listings for all publicly known CPUID leaves. Add the header to MAINTAINERS x86 CPUID database entry. Suggested-by: Thomas Gleixner Signed-off-by: Ahmed S. Darwish Link: https://gitlab.com/x86-cpuid.org/x86-cpuid-db/-/blob/v2.4/CHANGELOG.r= st --- MAINTAINERS | 1 + arch/x86/include/asm/cpuid/leaf_types.h | 2055 +++++++++++++++++++++++ 2 files changed, 2056 insertions(+) create mode 100644 arch/x86/include/asm/cpuid/leaf_types.h diff --git a/MAINTAINERS b/MAINTAINERS index fe168477caa4..bcb50236fbd2 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -27243,6 +27243,7 @@ R: Ahmed S. Darwish L: x86-cpuid@lists.linux.dev S: Maintained W: https://x86-cpuid.org +F: arch/x86/include/asm/cpuid/leaf_types.h F: tools/arch/x86/kcpuid/ =20 X86 ENTRY CODE diff --git a/arch/x86/include/asm/cpuid/leaf_types.h b/arch/x86/include/asm= /cpuid/leaf_types.h new file mode 100644 index 000000000000..0af2f67aee40 --- /dev/null +++ b/arch/x86/include/asm/cpuid/leaf_types.h @@ -0,0 +1,2055 @@ +/* SPDX-License-Identifier: MIT */ +/* Generator: x86-cpuid-db v2.4 */ + +/* + * Auto-generated file. + * Please submit all updates and bugfixes to https://x86-cpuid.org + */ + +#ifndef _ASM_X86_CPUID_LEAVES +#define _ASM_X86_CPUID_LEAVES + +#include + +/* + * Leaf 0x0 + * Maximum standard leaf number + CPU vendor string + */ + +struct leaf_0x0_0 { + // eax + u32 max_std_leaf : 32; // Highest standard CPUID leaf supported + // ebx + u32 cpu_vendorid_0 : 32; // CPU vendor ID string bytes 0 - 3 + // ecx + u32 cpu_vendorid_2 : 32; // CPU vendor ID string bytes 8 - 11 + // edx + u32 cpu_vendorid_1 : 32; // CPU vendor ID string bytes 4 - 7 +}; + +/* + * Leaf 0x1 + * CPU FMS (Family/Model/Stepping) + standard feature flags + */ + +struct leaf_0x1_0 { + // eax + u32 stepping : 4, // Stepping ID + base_model : 4, // Base CPU model ID + base_family_id : 4, // Base CPU family ID + cpu_type : 2, // CPU type + : 2, // Reserved + ext_model : 4, // Extended CPU model ID + ext_family : 8, // Extended CPU family ID + : 4; // Reserved + // ebx + u32 brand_id : 8, // Brand index + clflush_size : 8, // CLFLUSH instruction cache line size + n_logical_cpu : 8, // Logical CPU count + local_apic_id : 8; // Initial local APIC physical ID + // ecx + u32 sse3 : 1, // Streaming SIMD Extensions 3 (SSE3) + pclmulqdq : 1, // PCLMULQDQ instruction support + dtes64 : 1, // 64-bit DS save area + monitor : 1, // MONITOR/MWAIT support + dscpl : 1, // CPL Qualified Debug Store + vmx : 1, // Virtual Machine Extensions + smx : 1, // Safer Mode Extensions + est : 1, // Enhanced Intel SpeedStep + tm2 : 1, // Thermal Monitor 2 + ssse3 : 1, // Supplemental SSE3 + cntxt_id : 1, // L1 Context ID + sdbg : 1, // Silicon Debug + fma : 1, // FMA extensions using YMM state + cx16 : 1, // CMPXCHG16B instruction support + xtpr_update : 1, // xTPR Update Control + pdcm : 1, // Perfmon and Debug Capability + : 1, // Reserved + pcid : 1, // Process-context identifiers + dca : 1, // Direct Cache Access + sse4_1 : 1, // SSE4.1 + sse4_2 : 1, // SSE4.2 + x2apic : 1, // X2APIC support + movbe : 1, // MOVBE instruction support + popcnt : 1, // POPCNT instruction support + tsc_deadline_timer : 1, // APIC timer one-shot operation + aes : 1, // AES instructions + xsave : 1, // XSAVE (and related instructions) support + osxsave : 1, // XSAVE (and related instructions) are enabled by OS + avx : 1, // AVX instructions support + f16c : 1, // Half-precision floating-point conversion support + rdrand : 1, // RDRAND instruction support + guest_status : 1; // System is running as guest; (para-)virtualized s= ystem + // edx + u32 fpu : 1, // Floating-Point Unit on-chip (x87) + vme : 1, // Virtual-8086 Mode Extensions + de : 1, // Debugging Extensions + pse : 1, // Page Size Extension + tsc : 1, // Time Stamp Counter + msr : 1, // Model-Specific Registers (RDMSR and WRMSR support) + pae : 1, // Physical Address Extensions + mce : 1, // Machine Check Exception + cx8 : 1, // CMPXCHG8B instruction + apic : 1, // APIC on-chip + : 1, // Reserved + sep : 1, // SYSENTER, SYSEXIT, and associated MSRs + mtrr : 1, // Memory Type Range Registers + pge : 1, // Page Global Extensions + mca : 1, // Machine Check Architecture + cmov : 1, // Conditional Move Instruction + pat : 1, // Page Attribute Table + pse36 : 1, // Page Size Extension (36-bit) + psn : 1, // Processor Serial Number + clflush : 1, // CLFLUSH instruction + : 1, // Reserved + ds : 1, // Debug Store + acpi : 1, // Thermal monitor and clock control + mmx : 1, // MMX instructions + fxsr : 1, // FXSAVE and FXRSTOR instructions + sse : 1, // SSE instructions + sse2 : 1, // SSE2 instructions + selfsnoop : 1, // Self Snoop + htt : 1, // Hyper-threading + tm : 1, // Thermal Monitor + ia64 : 1, // Legacy IA-64 (Itanium) support bit, now reserved + pbe : 1; // Pending Break Enable +}; + +/* + * Leaf 0x2 + * Intel cache and TLB information one-byte descriptors + */ + +struct leaf_0x2_0 { + // eax + u32 iteration_count : 8, // Number of times this leaf must be queried + desc1 : 8, // Descriptor #1 + desc2 : 8, // Descriptor #2 + desc3 : 7, // Descriptor #3 + eax_invalid : 1; // Descriptors 1-3 are invalid if set + // ebx + u32 desc4 : 8, // Descriptor #4 + desc5 : 8, // Descriptor #5 + desc6 : 8, // Descriptor #6 + desc7 : 7, // Descriptor #7 + ebx_invalid : 1; // Descriptors 4-7 are invalid if set + // ecx + u32 desc8 : 8, // Descriptor #8 + desc9 : 8, // Descriptor #9 + desc10 : 8, // Descriptor #10 + desc11 : 7, // Descriptor #11 + ecx_invalid : 1; // Descriptors 8-11 are invalid if set + // edx + u32 desc12 : 8, // Descriptor #12 + desc13 : 8, // Descriptor #13 + desc14 : 8, // Descriptor #14 + desc15 : 7, // Descriptor #15 + edx_invalid : 1; // Descriptors 12-15 are invalid if set +}; + +/* + * Leaf 0x4 + * Intel deterministic cache parameters + */ + +struct leaf_0x4_0 { + // eax + u32 cache_type : 5, // Cache type field + cache_level : 3, // Cache level (1-based) + cache_self_init : 1, // Self-initializing cache level + fully_associative : 1, // Fully-associative cache + : 4, // Reserved + num_threads_sharing : 12, // Number logical CPUs sharing this cache + num_cores_on_die : 6; // Number of cores in the physical package + // ebx + u32 cache_linesize : 12, // System coherency line size (0-based) + cache_npartitions : 10, // Physical line partitions (0-based) + cache_nways : 10; // Ways of associativity (0-based) + // ecx + u32 cache_nsets : 31, // Cache number of sets (0-based) + : 1; // Reserved + // edx + u32 wbinvd_rll_no_guarantee : 1, // WBINVD/INVD not guaranteed for Remo= te Lower-Level caches + ll_inclusive : 1, // Cache is inclusive of Lower-Level caches + complex_indexing : 1, // Not a direct-mapped cache (complex function) + : 29; // Reserved +}; + +/* + * Leaf 0x5 + * MONITOR/MWAIT instructions enumeration + */ + +struct leaf_0x5_0 { + // eax + u32 min_mon_size : 16, // Smallest monitor-line size, in bytes + : 16; // Reserved + // ebx + u32 max_mon_size : 16, // Largest monitor-line size, in bytes + : 16; // Reserved + // ecx + u32 mwait_ext : 1, // Enumeration of MONITOR/MWAIT extensions is suppo= rted + mwait_irq_break : 1, // Interrupts as a break-event for MWAIT is supp= orted + : 30; // Reserved + // edx + u32 n_c0_substates : 4, // Number of C0 sub C-states supported using M= WAIT + n_c1_substates : 4, // Number of C1 sub C-states supported using MWAIT + n_c2_substates : 4, // Number of C2 sub C-states supported using MWAIT + n_c3_substates : 4, // Number of C3 sub C-states supported using MWAIT + n_c4_substates : 4, // Number of C4 sub C-states supported using MWAIT + n_c5_substates : 4, // Number of C5 sub C-states supported using MWAIT + n_c6_substates : 4, // Number of C6 sub C-states supported using MWAIT + n_c7_substates : 4; // Number of C7 sub C-states supported using MWAIT +}; + +/* + * Leaf 0x6 + * Thermal and Power Management enumeration + */ + +struct leaf_0x6_0 { + // eax + u32 digital_temp : 1, // Digital temperature sensor + turbo_boost : 1, // Intel Turbo Boost + lapic_timer_always_on : 1, // Always-Running APIC Timer (not affected = by p-state) + : 1, // Reserved + power_limit_event : 1, // Power Limit Notification (PLN) event + ecmd : 1, // Clock modulation duty cycle extension + package_thermal : 1, // Package thermal management + hwp_base_regs : 1, // HWP (Hardware P-states) base registers are supp= orted + hwp_notify : 1, // HWP notification (IA32_HWP_INTERRUPT MSR) + hwp_activity_window : 1, // HWP activity window (IA32_HWP_REQUEST[bits= 41:32]) supported + hwp_energy_perf_pr : 1, // HWP Energy Performance Preference + hwp_package_req : 1, // HWP Package Level Request + : 1, // Reserved + hdc_base_regs : 1, // HDC base registers are supported + turbo_boost_3_0 : 1, // Intel Turbo Boost Max 3.0 + hwp_capabilities : 1, // HWP Highest Performance change + hwp_peci_override : 1, // HWP PECI override + hwp_flexible : 1, // Flexible HWP + hwp_fast : 1, // IA32_HWP_REQUEST MSR fast access mode + hw_feedback : 1, // HW_FEEDBACK MSRs supported + hwp_ignore_idle : 1, // Ignoring idle logical CPU HWP req is supported + : 2, // Reserved + thread_director : 1, // Intel thread director support + therm_interrupt_bit25 : 1, // IA32_THERM_INTERRUPT MSR bit 25 is suppo= rted + : 7; // Reserved + // ebx + u32 n_therm_thresholds : 4, // Digital thermometer thresholds + : 28; // Reserved + // ecx + u32 aperf_mperf : 1, // MPERF/APERF MSRs (effective frequency interfac= e) + : 2, // Reserved + energy_perf_bias : 1, // IA32_ENERGY_PERF_BIAS MSR support + : 4, // Reserved + thrd_director_nclasses : 8, // Number of classes, Intel thread director + : 16; // Reserved + // edx + u32 perfcap_reporting : 1, // Performance capability reporting + encap_reporting : 1, // Energy efficiency capability reporting + : 6, // Reserved + feedback_sz : 4, // Feedback interface structure size, in 4K pages + : 4, // Reserved + this_lcpu_hwfdbk_idx : 16; // This logical CPU hardware feedback interf= ace index +}; + +/* + * Leaf 0x7 + * Extended CPU features enumeration + */ + +struct leaf_0x7_0 { + // eax + u32 leaf7_n_subleaves : 32; // Number of leaf 0x7 subleaves + // ebx + u32 fsgsbase : 1, // FSBASE/GSBASE read/write support + tsc_adjust : 1, // IA32_TSC_ADJUST MSR supported + sgx : 1, // Intel SGX (Software Guard Extensions) + bmi1 : 1, // Bit manipulation extensions group 1 + hle : 1, // Hardware Lock Elision + avx2 : 1, // AVX2 instruction set + fdp_excptn_only : 1, // FPU Data Pointer updated only on x87 exceptio= ns + smep : 1, // Supervisor Mode Execution Protection + bmi2 : 1, // Bit manipulation extensions group 2 + erms : 1, // Enhanced REP MOVSB/STOSB + invpcid : 1, // INVPCID instruction (Invalidate Processor Context ID) + rtm : 1, // Intel restricted transactional memory + pqm : 1, // Intel RDT-CMT / AMD Platform-QoS cache monitoring + zero_fcs_fds : 1, // Deprecated FPU CS/DS (stored as zero) + mpx : 1, // Intel memory protection extensions + rdt_a : 1, // Intel RDT / AMD Platform-QoS Enforcement + avx512f : 1, // AVX-512 foundation instructions + avx512dq : 1, // AVX-512 double/quadword instructions + rdseed : 1, // RDSEED instruction + adx : 1, // ADCX/ADOX instructions + smap : 1, // Supervisor mode access prevention + avx512ifma : 1, // AVX-512 integer fused multiply add + : 1, // Reserved + clflushopt : 1, // CLFLUSHOPT instruction + clwb : 1, // CLWB instruction + intel_pt : 1, // Intel processor trace + avx512pf : 1, // AVX-512 prefetch instructions + avx512er : 1, // AVX-512 exponent/reciprocal instructions + avx512cd : 1, // AVX-512 conflict detection instructions + sha : 1, // SHA/SHA256 instructions + avx512bw : 1, // AVX-512 byte/word instructions + avx512vl : 1; // AVX-512 VL (128/256 vector length) extensions + // ecx + u32 prefetchwt1 : 1, // PREFETCHWT1 (Intel Xeon Phi only) + avx512vbmi : 1, // AVX-512 Vector byte manipulation instructions + umip : 1, // User mode instruction protection + pku : 1, // Protection keys for user-space + ospke : 1, // OS protection keys enable + waitpkg : 1, // WAITPKG instructions + avx512_vbmi2 : 1, // AVX-512 vector byte manipulation instructions gr= oup 2 + cet_ss : 1, // CET shadow stack features + gfni : 1, // Galois field new instructions + vaes : 1, // Vector AES instructions + vpclmulqdq : 1, // VPCLMULQDQ 256-bit instruction support + avx512_vnni : 1, // Vector neural network instructions + avx512_bitalg : 1, // AVX-512 bitwise algorithms + tme : 1, // Intel total memory encryption + avx512_vpopcntdq : 1, // AVX-512: POPCNT for vectors of DWORD/QWORD + : 1, // Reserved + la57 : 1, // 57-bit linear addresses (five-level paging) + mawau_val_lm : 5, // BNDLDX/BNDSTX MAWAU value in 64-bit mode + rdpid : 1, // RDPID instruction + key_locker : 1, // Intel key locker support + bus_lock_detect : 1, // OS bus-lock detection + cldemote : 1, // CLDEMOTE instruction + : 1, // Reserved + movdiri : 1, // MOVDIRI instruction + movdir64b : 1, // MOVDIR64B instruction + enqcmd : 1, // Enqueue stores supported (ENQCMD{,S}) + sgx_lc : 1, // Intel SGX launch configuration + pks : 1; // Protection keys for supervisor-mode pages + // edx + u32 : 1, // Reserved + sgx_keys : 1, // Intel SGX attestation services + avx512_4vnniw : 1, // AVX-512 neural network instructions + avx512_4fmaps : 1, // AVX-512 multiply accumulation single precision + fsrm : 1, // Fast short REP MOV + uintr : 1, // CPU supports user interrupts + : 2, // Reserved + avx512_vp2intersect : 1, // VP2INTERSECT{D,Q} instructions + srdbs_ctrl : 1, // SRBDS mitigation MSR available + md_clear : 1, // VERW MD_CLEAR microcode support + rtm_always_abort : 1, // XBEGIN (RTM transaction) always aborts + : 1, // Reserved + tsx_force_abort : 1, // MSR TSX_FORCE_ABORT, RTM_ABORT bit, supported + serialize : 1, // SERIALIZE instruction + hybrid_cpu : 1, // The CPU is identified as a 'hybrid part' + tsxldtrk : 1, // TSX suspend/resume load address tracking + : 1, // Reserved + pconfig : 1, // PCONFIG instruction + arch_lbr : 1, // Intel architectural LBRs + cet_ibt : 1, // CET indirect branch tracking + : 1, // Reserved + amx_bf16 : 1, // AMX-BF16: tile bfloat16 support + avx512_fp16 : 1, // AVX-512 FP16 instructions + amx_tile : 1, // AMX-TILE: tile architecture support + amx_int8 : 1, // AMX-INT8: tile 8-bit integer support + spec_ctrl : 1, // Speculation Control (IBRS/IBPB: indirect branch res= trictions) + intel_stibp : 1, // Single thread indirect branch predictors + flush_l1d : 1, // FLUSH L1D cache: IA32_FLUSH_CMD MSR + arch_capabilities : 1, // Intel IA32_ARCH_CAPABILITIES MSR + core_capabilities : 1, // IA32_CORE_CAPABILITIES MSR + spec_ctrl_ssbd : 1; // Speculative store bypass disable +}; + +struct leaf_0x7_1 { + // eax + u32 : 4, // Reserved + avx_vnni : 1, // AVX-VNNI instructions + avx512_bf16 : 1, // AVX-512 bfloat16 instructions + lass : 1, // Linear address space separation + cmpccxadd : 1, // CMPccXADD instructions + arch_perfmon_ext : 1, // ArchPerfmonExt: leaf 0x23 is supported + : 1, // Reserved + fzrm : 1, // Fast zero-length REP MOVSB + fsrs : 1, // Fast short REP STOSB + fsrc : 1, // Fast Short REP CMPSB/SCASB + : 4, // Reserved + fred : 1, // FRED: Flexible return and event delivery transitions + lkgs : 1, // LKGS: Load 'kernel' (userspace) GS + wrmsrns : 1, // WRMSRNS instruction (WRMSR-non-serializing) + nmi_src : 1, // NMI-source reporting with FRED event data + amx_fp16 : 1, // AMX-FP16: FP16 tile operations + hreset : 1, // History reset support + avx_ifma : 1, // Integer fused multiply add + : 2, // Reserved + lam : 1, // Linear address masking + rd_wr_msrlist : 1, // RDMSRLIST/WRMSRLIST instructions + : 4; // Reserved + // ebx + u32 intel_ppin : 1, // Protected processor inventory number (PPIN{,_CT= L} MSRs) + : 31; // Reserved + // ecx + u32 : 32; // Reserved + // edx + u32 : 4, // Reserved + avx_vnni_int8 : 1, // AVX-VNNI-INT8 instructions + avx_ne_convert : 1, // AVX-NE-CONVERT instructions + : 2, // Reserved + amx_complex : 1, // AMX-COMPLEX instructions (starting from Granite R= apids) + : 5, // Reserved + prefetchit_0_1 : 1, // PREFETCHIT0/1 instructions + : 3, // Reserved + cet_sss : 1, // CET supervisor shadow stacks safe to use + : 13; // Reserved +}; + +struct leaf_0x7_2 { + // eax + u32 : 32; // Reserved + // ebx + u32 : 32; // Reserved + // ecx + u32 : 32; // Reserved + // edx + u32 intel_psfd : 1, // Intel predictive store forward disable + ipred_ctrl : 1, // MSR bits IA32_SPEC_CTRL.IPRED_DIS_{U,S} + rrsba_ctrl : 1, // MSR bits IA32_SPEC_CTRL.RRSBA_DIS_{U,S} + ddp_ctrl : 1, // MSR bit IA32_SPEC_CTRL.DDPD_U + bhi_ctrl : 1, // MSR bit IA32_SPEC_CTRL.BHI_DIS_S + mcdt_no : 1, // MCDT mitigation not needed + uclock_disable : 1, // UC-lock disable is supported + : 25; // Reserved +}; + +/* + * Leaf 0x9 + * Intel DCA (Direct Cache Access) enumeration + */ + +struct leaf_0x9_0 { + // eax + u32 dca_enabled_in_bios : 1, // DCA is enabled in BIOS + : 31; // Reserved + // ebx + u32 : 32; // Reserved + // ecx + u32 : 32; // Reserved + // edx + u32 : 32; // Reserved +}; + +/* + * Leaf 0xa + * Intel PMU (Performance Monitoring Unit) enumeration + */ + +struct leaf_0xa_0 { + // eax + u32 pmu_version : 8, // Performance monitoring unit version ID + pmu_n_gcounters : 8, // Number of general PMU counters per logical CPU + pmu_gcounters_nbits : 8, // Bitwidth of PMU general counters + pmu_cpuid_ebx_bits : 8; // Length of leaf 0xa EBX bit vector + // ebx + u32 no_core_cycle_evt : 1, // Core cycle event not available + no_insn_retired_evt : 1, // Instruction retired event not available + no_refcycle_evt : 1, // Reference cycles event not available + no_llc_ref_evt : 1, // LLC-reference event not available + no_llc_miss_evt : 1, // LLC-misses event not available + no_br_insn_ret_evt : 1, // Branch instruction retired event not availa= ble + no_br_mispredict_evt : 1, // Branch mispredict retired event not avail= able + no_td_slots_evt : 1, // Topdown slots event not available + : 24; // Reserved + // ecx + u32 pmu_fcounters_bitmap : 32; // Fixed-function PMU counters support bi= tmap + // edx + u32 pmu_n_fcounters : 5, // Number of fixed PMU counters + pmu_fcounters_nbits : 8, // Bitwidth of PMU fixed counters + : 2, // Reserved + anythread_depr : 1, // AnyThread deprecation + : 16; // Reserved +}; + +/* + * Leaf 0xb + * CPUs v1 extended topology enumeration + */ + +struct leaf_0xb_0 { + // eax + u32 x2apic_id_shift : 5, // Bit width of this level (previous levels i= nclusive) + : 27; // Reserved + // ebx + u32 domain_lcpus_count : 16, // Logical CPUs count across all instances = of this domain + : 16; // Reserved + // ecx + u32 domain_nr : 8, // This domain level (subleaf ID) + domain_type : 8, // This domain type + : 16; // Reserved + // edx + u32 x2apic_id : 32; // x2APIC ID of current logical CPU +}; + +/* + * Leaf 0xd + * Processor extended state enumeration + */ + +struct leaf_0xd_0 { + // eax + u32 xcr0_x87 : 1, // XCR0.X87 (bit 0) supported + xcr0_sse : 1, // XCR0.SEE (bit 1) supported + xcr0_avx : 1, // XCR0.AVX (bit 2) supported + xcr0_mpx_bndregs : 1, // XCR0.BNDREGS (bit 3) supported (MPX BND0-BND3= registers) + xcr0_mpx_bndcsr : 1, // XCR0.BNDCSR (bit 4) supported (MPX BNDCFGU/BN= DSTATUS registers) + xcr0_avx512_opmask : 1, // XCR0.OPMASK (bit 5) supported (AVX-512 k0-k= 7 registers) + xcr0_avx512_zmm_hi256 : 1, // XCR0.ZMM_Hi256 (bit 6) supported (AVX-51= 2 ZMM0->ZMM7/15 registers) + xcr0_avx512_hi16_zmm : 1, // XCR0.HI16_ZMM (bit 7) supported (AVX-512 = ZMM16->ZMM31 registers) + : 1, // Reserved + xcr0_pkru : 1, // XCR0.PKRU (bit 9) supported (XSAVE PKRU registers) + : 1, // Reserved + xcr0_cet_u : 1, // XCR0.CET_U (bit 11) supported (CET user state) + xcr0_cet_s : 1, // XCR0.CET_S (bit 12) supported (CET supervisor stat= e) + : 4, // Reserved + xcr0_tileconfig : 1, // XCR0.TILECONFIG (bit 17) supported (AMX can m= anage TILECONFIG) + xcr0_tiledata : 1, // XCR0.TILEDATA (bit 18) supported (AMX can manag= e TILEDATA) + : 13; // Reserved + // ebx + u32 xsave_sz_xcr0_enabled : 32; // XSAVE/XRSTOR area byte size, for XCR0= enabled features + // ecx + u32 xsave_sz_max : 32; // XSAVE/XRSTOR area max byte size, all CPU feat= ures + // edx + u32 : 30, // Reserved + xcr0_lwp : 1, // AMD XCR0.LWP (bit 62) supported (Light-weight Profil= ing) + : 1; // Reserved +}; + +struct leaf_0xd_1 { + // eax + u32 xsaveopt : 1, // XSAVEOPT instruction + xsavec : 1, // XSAVEC instruction + xgetbv1 : 1, // XGETBV instruction with ECX =3D 1 + xsaves : 1, // XSAVES/XRSTORS instructions (and XSS MSR) + xfd : 1, // Extended feature disable support + : 27; // Reserved + // ebx + u32 xsave_sz_xcr0_xmms_enabled : 32; // XSAVE area size, all XCR0 and XMM= S features enabled + // ecx + u32 : 8, // Reserved + xss_pt : 1, // PT state, supported + : 1, // Reserved + xss_pasid : 1, // PASID state, supported + xss_cet_u : 1, // CET user state, supported + xss_cet_p : 1, // CET supervisor state, supported + xss_hdc : 1, // HDC state, supported + xss_uintr : 1, // UINTR state, supported + xss_lbr : 1, // LBR state, supported + xss_hwp : 1, // HWP state, supported + : 15; // Reserved + // edx + u32 : 32; // Reserved +}; + +struct leaf_0xd_2 { + // eax + u32 xsave_sz : 32; // Size of save area for subleaf-N feature, in bytes + // ebx + u32 xsave_offset : 32; // Offset of save area for subleaf-N feature, in= bytes + // ecx + u32 is_xss_bit : 1, // Subleaf N describes an XSS bit, otherwise XCR0 = bit + compacted_xsave_64byte_aligned : 1, // When compacted, subleaf-N featur= e XSAVE area is 64-byte aligned + : 30; // Reserved + // edx + u32 : 32; // Reserved +}; + +/* + * Leaf 0xf + * Intel RDT / AMD PQoS resource monitoring + */ + +struct leaf_0xf_0 { + // eax + u32 : 32; // Reserved + // ebx + u32 core_rmid_max : 32; // RMID max, within this core, all types (0-bas= ed) + // ecx + u32 : 32; // Reserved + // edx + u32 : 1, // Reserved + llc_qos_mon : 1, // LLC QoS-monitoring supported + : 30; // Reserved +}; + +struct leaf_0xf_1 { + // eax + u32 l3c_qm_bitwidth : 8, // L3 QoS-monitoring counter bitwidth (24-bas= ed) + l3c_qm_overflow_bit : 1, // QM_CTR MSR bit 61 is an overflow bit + : 23; // Reserved + // ebx + u32 l3c_qm_conver_factor : 32; // QM_CTR MSR conversion factor to bytes + // ecx + u32 l3c_qm_rmid_max : 32; // L3 QoS-monitoring max RMID + // edx + u32 l3c_qm_occupancy : 1, // L3 QoS occupancy monitoring supported + l3c_qm_mbm_total : 1, // L3 QoS total bandwidth monitoring supported + l3c_qm_mbm_local : 1, // L3 QoS local bandwidth monitoring supported + : 29; // Reserved +}; + +/* + * Leaf 0x10 + * Intel RDT / AMD PQoS allocation enumeration + */ + +struct leaf_0x10_0 { + // eax + u32 : 32; // Reserved + // ebx + u32 : 1, // Reserved + cat_l3 : 1, // L3 Cache Allocation Technology supported + cat_l2 : 1, // L2 Cache Allocation Technology supported + mba : 1, // Memory Bandwidth Allocation supported + : 28; // Reserved + // ecx + u32 : 32; // Reserved + // edx + u32 : 32; // Reserved +}; + +struct leaf_0x10_1 { + // eax + u32 cat_cbm_len : 5, // L3/L2_CAT capacity bitmask length, minus-one n= otation + : 27; // Reserved + // ebx + u32 cat_units_bitmap : 32; // L3/L2_CAT bitmap of allocation units + // ecx + u32 : 1, // Reserved + l3_cat_cos_infreq_updates : 1, // L3_CAT COS updates should be infreque= nt + cat_cdp_supported : 1, // L3/L2_CAT CDP (Code and Data Prioritization) + cat_sparse_1s : 1, // L3/L2_CAT non-contiguous 1s value supported + : 28; // Reserved + // edx + u32 cat_cos_max : 16, // L3/L2_CAT max COS (Class of Service) supported + : 16; // Reserved +}; + +struct leaf_0x10_3 { + // eax + u32 mba_max_delay : 12, // Max MBA throttling value; minus-one notation + : 20; // Reserved + // ebx + u32 : 32; // Reserved + // ecx + u32 mba_per_thread : 1, // Per-thread MBA controls are supported + : 1, // Reserved + mba_delay_linear : 1, // Delay values are linear + : 29; // Reserved + // edx + u32 mba_cos_max : 16, // MBA max Class of Service supported + : 16; // Reserved +}; + +/* + * Leaf 0x12 + * Intel Software Guard Extensions (SGX) enumeration + */ + +struct leaf_0x12_0 { + // eax + u32 sgx1 : 1, // SGX1 leaf functions supported + sgx2 : 1, // SGX2 leaf functions supported + : 3, // Reserved + enclv_leaves : 1, // ENCLV leaves (E{INC,DEC}VIRTCHILD, ESETCONTEXT) = supported + encls_leaves : 1, // ENCLS leaves (ENCLS ETRACKC, ERDINFO, ELDBC, ELD= UC) supported + enclu_everifyreport2 : 1, // ENCLU leaf EVERIFYREPORT2 supported + : 2, // Reserved + encls_eupdatesvn : 1, // ENCLS leaf EUPDATESVN supported + enclu_edeccssa : 1, // ENCLU leaf EDECCSSA supported + : 20; // Reserved + // ebx + u32 miscselect_exinfo : 1, // SSA.MISC frame: reporting #PF and #GP exc= eptions inside enclave supported + miscselect_cpinfo : 1, // SSA.MISC frame: reporting #CP exceptions ins= ide enclave supported + : 30; // Reserved + // ecx + u32 : 32; // Reserved + // edx + u32 max_enclave_sz_not64 : 8, // Maximum enclave size in non-64-bit mod= e (log2) + max_enclave_sz_64 : 8, // Maximum enclave size in 64-bit mode (log2) + : 16; // Reserved +}; + +struct leaf_0x12_1 { + // eax + u32 secs_attr_init : 1, // ATTRIBUTES.INIT supported (enclave initiali= zed by EINIT) + secs_attr_debug : 1, // ATTRIBUTES.DEBUG supported (enclave permits d= ebugger read/write) + secs_attr_mode64bit : 1, // ATTRIBUTES.MODE64BIT supported (enclave ru= ns in 64-bit mode) + : 1, // Reserved + secs_attr_provisionkey : 1, // ATTRIBUTES.PROVISIONKEY supported (prov= isioning key available) + secs_attr_einittoken_key : 1, // ATTRIBUTES.EINITTOKEN_KEY supported (E= INIT token key available) + secs_attr_cet : 1, // ATTRIBUTES.CET supported (enable CET attributes) + secs_attr_kss : 1, // ATTRIBUTES.KSS supported (Key Separation and Sh= aring enabled) + : 2, // Reserved + secs_attr_aexnotify : 1, // ATTRIBUTES.AEXNOTIFY supported (enclave th= reads may get AEX notifications + : 21; // Reserved + // ebx + u32 : 32; // Reserved + // ecx + u32 xfrm_x87 : 1, // Enclave XFRM.X87 (bit 0) supported + xfrm_sse : 1, // Enclave XFRM.SEE (bit 1) supported + xfrm_avx : 1, // Enclave XFRM.AVX (bit 2) supported + xfrm_mpx_bndregs : 1, // Enclave XFRM.BNDREGS (bit 3) supported (MPX B= ND0-BND3 registers) + xfrm_mpx_bndcsr : 1, // Enclave XFRM.BNDCSR (bit 4) supported (MPX BN= DCFGU/BNDSTATUS registers) + xfrm_avx512_opmask : 1, // Enclave XFRM.OPMASK (bit 5) supported (AVX-= 512 k0-k7 registers) + xfrm_avx512_zmm_hi256 : 1, // Enclave XFRM.ZMM_Hi256 (bit 6) supported= (AVX-512 ZMM0->ZMM7/15 registers) + xfrm_avx512_hi16_zmm : 1, // Enclave XFRM.HI16_ZMM (bit 7) supported (= AVX-512 ZMM16->ZMM31 registers) + : 1, // Reserved + xfrm_pkru : 1, // Enclave XFRM.PKRU (bit 9) supported (XSAVE PKRU reg= isters) + : 7, // Reserved + xfrm_tileconfig : 1, // Enclave XFRM.TILECONFIG (bit 17) supported (A= MX can manage TILECONFIG) + xfrm_tiledata : 1, // Enclave XFRM.TILEDATA (bit 18) supported (AMX c= an manage TILEDATA) + : 13; // Reserved + // edx + u32 : 32; // Reserved +}; + +struct leaf_0x12_2 { + // eax + u32 subleaf_type : 4, // Subleaf type (dictates output layout) + : 8, // Reserved + epc_sec_base_addr_0 : 20; // EPC section base address, bits[12:31] + // ebx + u32 epc_sec_base_addr_1 : 20, // EPC section base address, bits[32:51] + : 12; // Reserved + // ecx + u32 epc_sec_type : 4, // EPC section type / property encoding + : 8, // Reserved + epc_sec_size_0 : 20; // EPC section size, bits[12:31] + // edx + u32 epc_sec_size_1 : 20, // EPC section size, bits[32:51] + : 12; // Reserved +}; + +/* + * Leaf 0x14 + * Intel Processor Trace enumeration + */ + +struct leaf_0x14_0 { + // eax + u32 pt_max_subleaf : 32; // Maximum leaf 0x14 subleaf + // ebx + u32 cr3_filtering : 1, // IA32_RTIT_CR3_MATCH is accessible + psb_cyc : 1, // Configurable PSB and cycle-accurate mode + ip_filtering : 1, // IP/TraceStop filtering; Warm-reset PT MSRs prese= rvation + mtc_timing : 1, // MTC timing packet; COFI-based packets suppression + ptwrite : 1, // PTWRITE support + power_event_trace : 1, // Power Event Trace support + psb_pmi_preserve : 1, // PSB and PMI preservation support + event_trace : 1, // Event Trace packet generation through IA32_RTIT_C= TL.EventEn + tnt_disable : 1, // TNT packet generation disable through IA32_RTIT_C= TL.DisTNT + : 23; // Reserved + // ecx + u32 topa_output : 1, // ToPA output scheme support + topa_multiple_entries : 1, // ToPA tables can hold multiple entries + single_range_output : 1, // Single-range output scheme supported + trance_transport_output : 1, // Trace Transport subsystem output suppo= rt + : 27, // Reserved + ip_payloads_lip : 1; // IP payloads have LIP values (CS base included) + // edx + u32 : 32; // Reserved +}; + +struct leaf_0x14_1 { + // eax + u32 num_address_ranges : 3, // Filtering number of configurable Address= Ranges + : 13, // Reserved + mtc_periods_bmp : 16; // Bitmap of supported MTC period encodings + // ebx + u32 cycle_thresholds_bmp : 16, // Bitmap of supported Cycle Threshold en= codings + psb_periods_bmp : 16; // Bitmap of supported Configurable PSB frequenc= y encodings + // ecx + u32 : 32; // Reserved + // edx + u32 : 32; // Reserved +}; + +/* + * Leaf 0x15 + * Intel TSC (Time Stamp Counter) enumeration + */ + +struct leaf_0x15_0 { + // eax + u32 tsc_denominator : 32; // Denominator of the TSC/'core crystal clock= ' ratio + // ebx + u32 tsc_numerator : 32; // Numerator of the TSC/'core crystal clock' ra= tio + // ecx + u32 cpu_crystal_hz : 32; // Core crystal clock nominal frequency, in Hz + // edx + u32 : 32; // Reserved +}; + +/* + * Leaf 0x16 + * Intel processor frequency enumeration + */ + +struct leaf_0x16_0 { + // eax + u32 cpu_base_mhz : 16, // Processor base frequency, in MHz + : 16; // Reserved + // ebx + u32 cpu_max_mhz : 16, // Processor max frequency, in MHz + : 16; // Reserved + // ecx + u32 bus_mhz : 16, // Bus reference frequency, in MHz + : 16; // Reserved + // edx + u32 : 32; // Reserved +}; + +/* + * Leaf 0x17 + * Intel SoC vendor attributes enumeration + */ + +struct leaf_0x17_0 { + // eax + u32 soc_max_subleaf : 32; // Maximum leaf 0x17 subleaf + // ebx + u32 soc_vendor_id : 16, // SoC vendor ID + is_vendor_scheme : 1, // Assigned by industry enumeration scheme (not = Intel) + : 15; // Reserved + // ecx + u32 soc_proj_id : 32; // SoC project ID, assigned by vendor + // edx + u32 soc_stepping_id : 32; // Soc project stepping ID, assigned by vendor +}; + +struct leaf_0x17_1 { + // eax + u32 vendor_brand_a : 32; // Vendor Brand ID string, bytes subleaf_nr * = (0 -> 3) + // ebx + u32 vendor_brand_b : 32; // Vendor Brand ID string, bytes subleaf_nr * = (4 -> 7) + // ecx + u32 vendor_brand_c : 32; // Vendor Brand ID string, bytes subleaf_nr * = (8 -> 11) + // edx + u32 vendor_brand_d : 32; // Vendor Brand ID string, bytes subleaf_nr * = (12 -> 15) +}; + +/* + * Leaf 0x18 + * Intel determenestic address translation (TLB) parameters + */ + +struct leaf_0x18_0 { + // eax + u32 tlb_max_subleaf : 32; // Maximum leaf 0x18 subleaf + // ebx + u32 tlb_4k_page : 1, // TLB 4KB-page entries supported + tlb_2m_page : 1, // TLB 2MB-page entries supported + tlb_4m_page : 1, // TLB 4MB-page entries supported + tlb_1g_page : 1, // TLB 1GB-page entries supported + : 4, // Reserved + hard_partitioning : 3, // (Hard/Soft) partitioning between logical CPU= s sharing this structure + : 5, // Reserved + n_way_associative : 16; // Ways of associativity + // ecx + u32 n_sets : 32; // Number of sets + // edx + u32 tlb_type : 5, // Translation cache type (TLB type) + tlb_cache_level : 3, // Translation cache level (1-based) + is_fully_associative : 1, // Fully-associative structure + : 5, // Reserved + tlb_max_addressible_ids : 12, // Max number of addressable IDs for logi= cal CPUs sharing this TLB - 1 + : 6; // Reserved +}; + +/* + * Leaf 0x19 + * Intel Key Locker enumeration + */ + +struct leaf_0x19_0 { + // eax + u32 kl_cpl0_only : 1, // CPL0-only key Locker restriction supported + kl_no_encrypt : 1, // No-encrypt key locker restriction supported + kl_no_decrypt : 1, // No-decrypt key locker restriction supported + : 29; // Reserved + // ebx + u32 aes_keylocker : 1, // AES key locker instructions supported + : 1, // Reserved + aes_keylocker_wide : 1, // AES wide key locker instructions supported + : 1, // Reserved + kl_msr_iwkey : 1, // Key locker MSRs and IWKEY backups supported + : 27; // Reserved + // ecx + u32 loadiwkey_no_backup : 1, // LOADIWKEY NoBackup parameter supported + iwkey_rand : 1, // IWKEY randomization (KeySource encoding 1) support= ed + : 30; // Reserved + // edx + u32 : 32; // Reserved +}; + +/* + * Leaf 0x1a + * Intel hybrid CPUs identification (e.g. Atom, Core) + */ + +struct leaf_0x1a_0 { + // eax + u32 core_native_model : 24, // This core's native model ID + core_type : 8; // This core's type + // ebx + u32 : 32; // Reserved + // ecx + u32 : 32; // Reserved + // edx + u32 : 32; // Reserved +}; + +/* + * Leaf 0x1b + * Intel PCONFIG (Platform configuration) enumeration + */ + +struct leaf_0x1b_0 { + // eax + u32 pconfig_subleaf_type : 12, // CPUID 0x1b subleaf type + : 20; // Reserved + // ebx + u32 pconfig_target_id_x : 32; // A supported PCONFIG target ID + // ecx + u32 pconfig_target_id_y : 32; // A supported PCONFIG target ID + // edx + u32 pconfig_target_id_z : 32; // A supported PCONFIG target ID +}; + +/* + * Leaf 0x1c + * Intel LBR (Last Branch Record) enumeration + */ + +struct leaf_0x1c_0 { + // eax + u32 lbr_depth_8 : 1, // Max stack depth (number of LBR entries) =3D 8 + lbr_depth_16 : 1, // Max stack depth (number of LBR entries) =3D 16 + lbr_depth_24 : 1, // Max stack depth (number of LBR entries) =3D 24 + lbr_depth_32 : 1, // Max stack depth (number of LBR entries) =3D 32 + lbr_depth_40 : 1, // Max stack depth (number of LBR entries) =3D 40 + lbr_depth_48 : 1, // Max stack depth (number of LBR entries) =3D 48 + lbr_depth_56 : 1, // Max stack depth (number of LBR entries) =3D 56 + lbr_depth_64 : 1, // Max stack depth (number of LBR entries) =3D 64 + : 22, // Reserved + lbr_deep_c_reset : 1, // LBRs maybe cleared on MWAIT C-state > C1 + lbr_ip_is_lip : 1; // LBR IP contain Last IP, otherwise effective IP + // ebx + u32 lbr_cpl : 1, // CPL filtering (non-zero IA32_LBR_CTL[2:1]) suppor= ted + lbr_branch_filter : 1, // Branch filtering (non-zero IA32_LBR_CTL[22:1= 6]) supported + lbr_call_stack : 1, // Call-stack mode (IA32_LBR_CTL[3] =3D 1) suppor= ted + : 29; // Reserved + // ecx + u32 lbr_mispredict : 1, // Branch misprediction bit supported (IA32_LB= R_x_INFO[63]) + lbr_timed_lbr : 1, // Timed LBRs (CPU cycles since last LBR entry) su= pported + lbr_branch_type : 1, // Branch type field (IA32_LBR_INFO_x[59:56]) su= pported + : 13, // Reserved + lbr_events_gpc_bmp : 4, // LBR PMU-events logging support; bitmap for = first 4 GP (general-purpose) Counters + : 12; // Reserved + // edx + u32 : 32; // Reserved +}; + +/* + * Leaf 0x1d + * Intel AMX (Advanced Matrix Extensions) tile information + */ + +struct leaf_0x1d_0 { + // eax + u32 amx_max_palette : 32; // Highest palette ID / subleaf ID + // ebx + u32 : 32; // Reserved + // ecx + u32 : 32; // Reserved + // edx + u32 : 32; // Reserved +}; + +struct leaf_0x1d_1 { + // eax + u32 amx_palette_size : 16, // AMX palette total tiles size, in bytes + amx_tile_size : 16; // AMX single tile's size, in bytes + // ebx + u32 amx_tile_row_size : 16, // AMX tile single row's size, in bytes + amx_palette_nr_tiles : 16; // AMX palette number of tiles + // ecx + u32 amx_tile_nr_rows : 16, // AMX tile max number of rows + : 16; // Reserved + // edx + u32 : 32; // Reserved +}; + +/* + * Leaf 0x1e + * Intel AMX, TMUL (Tile-matrix MULtiply) accelerator unit enumeration + */ + +struct leaf_0x1e_0 { + // eax + u32 : 32; // Reserved + // ebx + u32 tmul_maxk : 8, // TMUL unit maximum height, K (rows or columns) + tmul_maxn : 16, // TMUL unit maximum SIMD dimension, N (column bytes) + : 8; // Reserved + // ecx + u32 : 32; // Reserved + // edx + u32 : 32; // Reserved +}; + +/* + * Leaf 0x1f + * Intel extended topology enumeration v2 + */ + +struct leaf_0x1f_0 { + // eax + u32 x2apic_id_shift : 5, // Bit width of this level (previous levels i= nclusive) + : 27; // Reserved + // ebx + u32 domain_lcpus_count : 16, // Logical CPUs count across all instances = of this domain + : 16; // Reserved + // ecx + u32 domain_level : 8, // This domain level (subleaf ID) + domain_type : 8, // This domain type + : 16; // Reserved + // edx + u32 x2apic_id : 32; // x2APIC ID of current logical CPU +}; + +/* + * Leaf 0x20 + * Intel HRESET (History Reset) enumeration + */ + +struct leaf_0x20_0 { + // eax + u32 hreset_nr_subleaves : 32; // CPUID 0x20 max subleaf + 1 + // ebx + u32 hreset_thread_director : 1, // HRESET of Intel thread director is s= upported + : 31; // Reserved + // ecx + u32 : 32; // Reserved + // edx + u32 : 32; // Reserved +}; + +/* + * Leaf 0x21 + * Intel TD (Trust Domain) guest execution environment enumeration + */ + +struct leaf_0x21_0 { + // eax + u32 : 32; // Reserved + // ebx + u32 tdx_vendorid_0 : 32; // TDX vendor ID string bytes 0 - 3 + // ecx + u32 tdx_vendorid_2 : 32; // CPU vendor ID string bytes 8 - 11 + // edx + u32 tdx_vendorid_1 : 32; // CPU vendor ID string bytes 4 - 7 +}; + +/* + * Leaf 0x23 + * Intel Architectural Performance Monitoring Extended (ArchPerfmonExt) + */ + +struct leaf_0x23_0 { + // eax + u32 : 1, // Reserved + subleaf_1_counters : 1, // Subleaf 1, PMU counters bitmaps, is valid + : 1, // Reserved + subleaf_3_events : 1, // Subleaf 3, PMU events bitmaps, is valid + : 28; // Reserved + // ebx + u32 unitmask2 : 1, // IA32_PERFEVTSELx MSRs UnitMask2 is supported + zbit : 1, // IA32_PERFEVTSELx MSRs Z-bit is supported + : 30; // Reserved + // ecx + u32 : 32; // Reserved + // edx + u32 : 32; // Reserved +}; + +struct leaf_0x23_1 { + // eax + u32 pmu_gp_counters_bitmap : 32; // General-purpose PMU counters bitmap + // ebx + u32 pmu_f_counters_bitmap : 32; // Fixed PMU counters bitmap + // ecx + u32 : 32; // Reserved + // edx + u32 : 32; // Reserved +}; + +struct leaf_0x23_3 { + // eax + u32 core_cycles_evt : 1, // Core cycles event supported + insn_retired_evt : 1, // Instructions retired event supported + ref_cycles_evt : 1, // Reference cycles event supported + llc_refs_evt : 1, // Last-level cache references event supported + llc_misses_evt : 1, // Last-level cache misses event supported + br_insn_ret_evt : 1, // Branch instruction retired event supported + br_mispr_evt : 1, // Branch mispredict retired event supported + td_slots_evt : 1, // Topdown slots event supported + td_backend_bound_evt : 1, // Topdown backend bound event supported + td_bad_spec_evt : 1, // Topdown bad speculation event supported + td_frontend_bound_evt : 1, // Topdown frontend bound event supported + td_retiring_evt : 1, // Topdown retiring event support + : 20; // Reserved + // ebx + u32 : 32; // Reserved + // ecx + u32 : 32; // Reserved + // edx + u32 : 32; // Reserved +}; + +/* + * Leaf 0x40000000 + * Maximum hypervisor standard leaf + hypervisor vendor string + */ + +struct leaf_0x40000000_0 { + // eax + u32 max_hyp_leaf : 32; // Maximum hypervisor standard leaf number + // ebx + u32 hypervisor_id_0 : 32; // Hypervisor ID string bytes 0 - 3 + // ecx + u32 hypervisor_id_1 : 32; // Hypervisor ID string bytes 4 - 7 + // edx + u32 hypervisor_id_2 : 32; // Hypervisor ID string bytes 8 - 11 +}; + +/* + * Leaf 0x80000000 + * Maximum extended leaf number + AMD/Transmeta CPU vendor string + */ + +struct leaf_0x80000000_0 { + // eax + u32 max_ext_leaf : 32; // Maximum extended CPUID leaf supported + // ebx + u32 cpu_vendorid_0 : 32; // Vendor ID string bytes 0 - 3 + // ecx + u32 cpu_vendorid_2 : 32; // Vendor ID string bytes 8 - 11 + // edx + u32 cpu_vendorid_1 : 32; // Vendor ID string bytes 4 - 7 +}; + +/* + * Leaf 0x80000001 + * Extended CPU feature identifiers + */ + +struct leaf_0x80000001_0 { + // eax + u32 e_stepping_id : 4, // Stepping ID + e_base_model : 4, // Base processor model + e_base_family : 4, // Base processor family + e_base_type : 2, // Base processor type (Transmeta) + : 2, // Reserved + e_ext_model : 4, // Extended processor model + e_ext_family : 8, // Extended processor family + : 4; // Reserved + // ebx + u32 brand_id : 16, // Brand ID + : 12, // Reserved + pkg_type : 4; // Package type + // ecx + u32 lahf_lm : 1, // LAHF and SAHF in 64-bit mode + cmp_legacy : 1, // Multi-processing legacy mode (No HT) + svm : 1, // Secure Virtual Machine + extapic : 1, // Extended APIC space + cr8_legacy : 1, // LOCK MOV CR0 means MOV CR8 + lzcnt_abm : 1, // LZCNT advanced bit manipulation + sse4a : 1, // SSE4A support + misaligned_sse : 1, // Misaligned SSE mode + _3dnow_prefetch : 1, // 3DNow PREFETCH/PREFETCHW support + osvw : 1, // OS visible workaround + ibs : 1, // Instruction based sampling + xop : 1, // XOP: extended operation (AVX instructions) + skinit : 1, // SKINIT/STGI support + wdt : 1, // Watchdog timer support + : 1, // Reserved + lwp : 1, // Lightweight profiling + fma4 : 1, // 4-operand FMA instruction + tce : 1, // Translation cache extension + : 1, // Reserved + nodeid_msr : 1, // NodeId MSR (0xc001100c) + : 1, // Reserved + tbm : 1, // Trailing bit manipulations + topoext : 1, // Topology Extensions (leaf 0x8000001d) + perfctr_core : 1, // Core performance counter extensions + perfctr_nb : 1, // NB/DF performance counter extensions + : 1, // Reserved + data_bp_ext : 1, // Data access breakpoint extension + perf_tsc : 1, // Performance time-stamp counter + perfctr_llc : 1, // LLC (L3) performance counter extensions + mwaitx : 1, // MWAITX/MONITORX support + addr_mask_ext : 1, // Breakpoint address mask extension (to bit 31) + : 1; // Reserved + // edx + u32 e_fpu : 1, // Floating-Point Unit on-chip (x87) + e_vme : 1, // Virtual-8086 Mode Extensions + e_de : 1, // Debugging Extensions + e_pse : 1, // Page Size Extension + e_tsc : 1, // Time Stamp Counter + e_msr : 1, // Model-Specific Registers (RDMSR and WRMSR support) + pae : 1, // Physical Address Extensions + mce : 1, // Machine Check Exception + cx8 : 1, // CMPXCHG8B instruction + apic : 1, // APIC on-chip + : 1, // Reserved + syscall : 1, // SYSCALL and SYSRET instructions + mtrr : 1, // Memory Type Range Registers + pge : 1, // Page Global Extensions + mca : 1, // Machine Check Architecture + cmov : 1, // Conditional Move Instruction + pat : 1, // Page Attribute Table + pse36 : 1, // Page Size Extension (36-bit) + : 1, // Reserved + obsolete_mp_bit : 1, // Out-of-spec AMD Multiprocessing bit + nx : 1, // No-execute page protection + : 1, // Reserved + mmxext : 1, // AMD MMX extensions + e_mmx : 1, // MMX instructions + e_fxsr : 1, // FXSAVE and FXRSTOR instructions + fxsr_opt : 1, // FXSAVE and FXRSTOR optimizations + page1gb : 1, // 1-GB large page support + rdtscp : 1, // RDTSCP instruction + : 1, // Reserved + lm : 1, // Long mode (x86-64, 64-bit support) + _3dnowext : 1, // AMD 3DNow extensions + _3dnow : 1; // 3DNow instructions +}; + +/* + * Leaf 0x80000002 + * CPU brand ID string, bytes 0 - 15 + */ + +struct leaf_0x80000002_0 { + // eax + u32 cpu_brandid_0 : 32; // CPU brand ID string, bytes 0 - 3 + // ebx + u32 cpu_brandid_1 : 32; // CPU brand ID string, bytes 4 - 7 + // ecx + u32 cpu_brandid_2 : 32; // CPU brand ID string, bytes 8 - 11 + // edx + u32 cpu_brandid_3 : 32; // CPU brand ID string, bytes 12 - 15 +}; + +/* + * Leaf 0x80000003 + * CPU brand ID string, bytes 16 - 31 + */ + +struct leaf_0x80000003_0 { + // eax + u32 cpu_brandid_4 : 32; // CPU brand ID string bytes, 16 - 19 + // ebx + u32 cpu_brandid_5 : 32; // CPU brand ID string bytes, 20 - 23 + // ecx + u32 cpu_brandid_6 : 32; // CPU brand ID string bytes, 24 - 27 + // edx + u32 cpu_brandid_7 : 32; // CPU brand ID string bytes, 28 - 31 +}; + +/* + * Leaf 0x80000004 + * CPU brand ID string, bytes 32 - 47 + */ + +struct leaf_0x80000004_0 { + // eax + u32 cpu_brandid_8 : 32; // CPU brand ID string, bytes 32 - 35 + // ebx + u32 cpu_brandid_9 : 32; // CPU brand ID string, bytes 36 - 39 + // ecx + u32 cpu_brandid_10 : 32; // CPU brand ID string, bytes 40 - 43 + // edx + u32 cpu_brandid_11 : 32; // CPU brand ID string, bytes 44 - 47 +}; + +/* + * Leaf 0x80000005 + * AMD/Transmeta L1 cache and L1 TLB enumeration + */ + +struct leaf_0x80000005_0 { + // eax + u32 l1_itlb_2m_4m_nentries : 8, // L1 ITLB #entries, 2M and 4M pages + l1_itlb_2m_4m_assoc : 8, // L1 ITLB associativity, 2M and 4M pages + l1_dtlb_2m_4m_nentries : 8, // L1 DTLB #entries, 2M and 4M pages + l1_dtlb_2m_4m_assoc : 8; // L1 DTLB associativity, 2M and 4M pages + // ebx + u32 l1_itlb_4k_nentries : 8, // L1 ITLB #entries, 4K pages + l1_itlb_4k_assoc : 8, // L1 ITLB associativity, 4K pages + l1_dtlb_4k_nentries : 8, // L1 DTLB #entries, 4K pages + l1_dtlb_4k_assoc : 8; // L1 DTLB associativity, 4K pages + // ecx + u32 l1_dcache_line_size : 8, // L1 dcache line size, in bytes + l1_dcache_nlines : 8, // L1 dcache lines per tag + l1_dcache_assoc : 8, // L1 dcache associativity + l1_dcache_size_kb : 8; // L1 dcache size, in KB + // edx + u32 l1_icache_line_size : 8, // L1 icache line size, in bytes + l1_icache_nlines : 8, // L1 icache lines per tag + l1_icache_assoc : 8, // L1 icache associativity + l1_icache_size_kb : 8; // L1 icache size, in KB +}; + +/* + * Leaf 0x80000006 + * (Mostly AMD) L2 TLB, L2 cache, and L3 cache enumeration + */ + +struct leaf_0x80000006_0 { + // eax + u32 l2_itlb_2m_4m_nentries : 12, // L2 iTLB #entries, 2M and 4M pages + l2_itlb_2m_4m_assoc : 4, // L2 iTLB associativity, 2M and 4M pages + l2_dtlb_2m_4m_nentries : 12, // L2 dTLB #entries, 2M and 4M pages + l2_dtlb_2m_4m_assoc : 4; // L2 dTLB associativity, 2M and 4M pages + // ebx + u32 l2_itlb_4k_nentries : 12, // L2 iTLB #entries, 4K pages + l2_itlb_4k_assoc : 4, // L2 iTLB associativity, 4K pages + l2_dtlb_4k_nentries : 12, // L2 dTLB #entries, 4K pages + l2_dtlb_4k_assoc : 4; // L2 dTLB associativity, 4K pages + // ecx + u32 l2_line_size : 8, // L2 cache line size, in bytes + l2_nlines : 4, // L2 cache number of lines per tag + l2_assoc : 4, // L2 cache associativity + l2_size_kb : 16; // L2 cache size, in KB + // edx + u32 l3_line_size : 8, // L3 cache line size, in bytes + l3_nlines : 4, // L3 cache number of lines per tag + l3_assoc : 4, // L3 cache associativity + : 2, // Reserved + l3_size_range : 14; // L3 cache size range +}; + +/* + * Leaf 0x80000007 + * CPU power management (mostly AMD) and AMD RAS enumeration + */ + +struct leaf_0x80000007_0 { + // eax + u32 : 32; // Reserved + // ebx + u32 mca_overflow_recovery : 1, // MCA overflow conditions not fatal + succor : 1, // Software containment of uncorrectable errors + hw_assert : 1, // Hardware assert MSRs + scalable_mca : 1, // Scalable MCA (MCAX MSRs) + : 28; // Reserved + // ecx + u32 cpu_pwr_sample_ratio : 32; // CPU power sample time ratio + // edx + u32 digital_temp : 1, // Digital temperature sensor + powernow_freq_id : 1, // PowerNOW! frequency scaling + powernow_volt_id : 1, // PowerNOW! voltage scaling + thermal_trip : 1, // THERMTRIP (Thermal Trip) + hw_thermal_control : 1, // Hardware thermal control + sw_thermal_control : 1, // Software thermal control + _100mhz_steps : 1, // 100 MHz multiplier control + hw_pstate : 1, // Hardware P-state control + constant_tsc : 1, // TSC ticks at constant rate across all P and C st= ates + core_perf_boost : 1, // Core performance boost + eff_freq_ro : 1, // Read-only effective frequency interface + proc_feedback : 1, // Processor feedback interface (deprecated) + proc_power_reporting : 1, // Processor power reporting interface + connected_standby : 1, // CPU Connected Standby support + rapl_interface : 1, // Runtime Average Power Limit interface + : 17; // Reserved +}; + +/* + * Leaf 0x80000008 + * CPU capacity parameters and extended feature flags (mostly AMD) + */ + +struct leaf_0x80000008_0 { + // eax + u32 phys_addr_bits : 8, // Max physical address bits + virt_addr_bits : 8, // Max virtual address bits + guest_phys_addr_bits : 8, // Max nested-paging guest physical address = bits + : 8; // Reserved + // ebx + u32 clzero : 1, // CLZERO supported + insn_retired_perf : 1, // Instruction retired counter MSR + xsave_err_ptr : 1, // XSAVE/XRSTOR always saves/restores FPU error po= inters + invlpgb : 1, // INVLPGB broadcasts a TLB invalidate to all threads + rdpru : 1, // RDPRU (Read Processor Register at User level) supported + : 1, // Reserved + mba : 1, // Memory Bandwidth Allocation (AMD bit) + : 1, // Reserved + mcommit : 1, // MCOMMIT (Memory commit) supported + wbnoinvd : 1, // WBNOINVD supported + : 2, // Reserved + ibpb : 1, // Indirect Branch Prediction Barrier + wbinvd_int : 1, // Interruptible WBINVD/WBNOINVD + ibrs : 1, // Indirect Branch Restricted Speculation + stibp : 1, // Single Thread Indirect Branch Prediction mode + ibrs_always_on : 1, // IBRS always-on preferred + stibp_always_on : 1, // STIBP always-on preferred + ibrs_fast : 1, // IBRS is preferred over software solution + ibrs_same_mode : 1, // IBRS provides same mode protection + no_efer_lmsle : 1, // EFER[LMSLE] bit (Long-Mode Segment Limit Enable= ) unsupported + tlb_flush_nested : 1, // INVLPGB RAX[5] bit can be set (nested transla= tions) + : 1, // Reserved + amd_ppin : 1, // Protected Processor Inventory Number + amd_ssbd : 1, // Speculative Store Bypass Disable + virt_ssbd : 1, // virtualized SSBD (Speculative Store Bypass Disable) + amd_ssb_no : 1, // SSBD is not needed (fixed in hardware) + cppc : 1, // Collaborative Processor Performance Control + amd_psfd : 1, // Predictive Store Forward Disable + btc_no : 1, // CPU not affected by Branch Type Confusion + ibpb_ret : 1, // IBPB clears RSB/RAS too + branch_sampling : 1; // Branch Sampling supported + // ecx + u32 cpu_nthreads : 8, // Number of physical threads - 1 + : 4, // Reserved + apicid_coreid_len : 4, // Number of thread core ID bits (shift) in API= C ID + perf_tsc_len : 2, // Performance time-stamp counter size + : 14; // Reserved + // edx + u32 invlpgb_max_pages : 16, // INVLPGB maximum page count + rdpru_max_reg_id : 16; // RDPRU max register ID (ECX input) +}; + +/* + * Leaf 0x8000000a + * AMD SVM (Secure Virtual Machine) enumeration + */ + +struct leaf_0x8000000a_0 { + // eax + u32 svm_version : 8, // SVM revision number + : 24; // Reserved + // ebx + u32 svm_nasid : 32; // Number of address space identifiers (ASID) + // ecx + u32 : 32; // Reserved + // edx + u32 nested_pt : 1, // Nested paging + lbr_virt : 1, // LBR virtualization + svm_lock : 1, // SVM lock + nrip_save : 1, // NRIP save support on #VMEXIT + tsc_rate_msr : 1, // MSR based TSC rate control + vmcb_clean : 1, // VMCB clean bits support + flush_by_asid : 1, // Flush by ASID + Extended VMCB TLB_Control + decode_assists : 1, // Decode Assists support + : 2, // Reserved + pause_filter : 1, // Pause intercept filter + : 1, // Reserved + pf_threshold : 1, // Pause filter threshold + avic : 1, // Advanced virtual interrupt controller + : 1, // Reserved + v_vmsave_vmload : 1, // Virtual VMSAVE/VMLOAD (nested virtualization) + v_gif : 1, // Virtualize the Global Interrupt Flag + gmet : 1, // Guest mode execution trap + x2avic : 1, // Virtual x2APIC + sss_check : 1, // Supervisor Shadow Stack restrictions + v_spec_ctrl : 1, // Virtual SPEC_CTRL + ro_gpt : 1, // Read-Only guest page table support + : 1, // Reserved + h_mce_override : 1, // Host MCE override + tlbsync_int : 1, // TLBSYNC intercept + INVLPGB/TLBSYNC in VMCB + nmi_virt : 1, // NMI virtualization + ibs_virt : 1, // IBS Virtualization + ext_lvt_off_chg : 1, // Extended LVT offset fault change + svme_addr_chk : 1, // Guest SVME address check + : 3; // Reserved +}; + +/* + * Leaf 0x80000019 + * AMD TLB 1G-pages enumeration + */ + +struct leaf_0x80000019_0 { + // eax + u32 l1_itlb_1g_nentries : 12, // L1 iTLB #entries, 1G pages + l1_itlb_1g_assoc : 4, // L1 iTLB associativity, 1G pages + l1_dtlb_1g_nentries : 12, // L1 dTLB #entries, 1G pages + l1_dtlb_1g_assoc : 4; // L1 dTLB associativity, 1G pages + // ebx + u32 l2_itlb_1g_nentries : 12, // L2 iTLB #entries, 1G pages + l2_itlb_1g_assoc : 4, // L2 iTLB associativity, 1G pages + l2_dtlb_1g_nentries : 12, // L2 dTLB #entries, 1G pages + l2_dtlb_1g_assoc : 4; // L2 dTLB associativity, 1G pages + // ecx + u32 : 32; // Reserved + // edx + u32 : 32; // Reserved +}; + +/* + * Leaf 0x8000001a + * AMD instruction optimizations enumeration + */ + +struct leaf_0x8000001a_0 { + // eax + u32 fp_128 : 1, // Internal FP/SIMD exec data path is 128-bits wide + movu_preferred : 1, // SSE: MOVU* better than MOVL*/MOVH* + fp_256 : 1, // internal FP/SSE exec data path is 256-bits wide + : 29; // Reserved + // ebx + u32 : 32; // Reserved + // ecx + u32 : 32; // Reserved + // edx + u32 : 32; // Reserved +}; + +/* + * Leaf 0x8000001b + * AMD IBS (Instruction-Based Sampling) enumeration + */ + +struct leaf_0x8000001b_0 { + // eax + u32 ibs_flags_valid : 1, // IBS feature flags valid + ibs_fetch_sampling : 1, // IBS fetch sampling supported + ibs_op_sampling : 1, // IBS execution sampling supported + ibs_rdwr_op_counter : 1, // IBS read/write of op counter supported + ibs_op_count : 1, // IBS OP counting mode supported + ibs_branch_target : 1, // IBS branch target address reporting supported + ibs_op_counters_ext : 1, // IBS IbsOpCurCnt/IbsOpMaxCnt extend by 7 bi= ts + ibs_rip_invalid_chk : 1, // IBS invalid RIP indication supported + ibs_op_branch_fuse : 1, // IBS fused branch micro-op indication suppor= ted + ibs_fetch_ctl_ext : 1, // IBS Fetch Control Extended MSR (0xc001103c) = supported + ibs_op_data_4 : 1, // IBS op data 4 MSR supported + ibs_l3_miss_filter : 1, // IBS L3-miss filtering supported (Zen4+) + : 20; // Reserved + // ebx + u32 : 32; // Reserved + // ecx + u32 : 32; // Reserved + // edx + u32 : 32; // Reserved +}; + +/* + * Leaf 0x8000001c + * AMD LWP (Lightweight Profiling) + */ + +struct leaf_0x8000001c_0 { + // eax + u32 os_lwp_avail : 1, // LWP is available to application programs (sup= ported by OS) + os_lpwval : 1, // LWPVAL instruction is supported by OS + os_lwp_ire : 1, // Instructions Retired Event is supported by OS + os_lwp_bre : 1, // Branch Retired Event is supported by OS + os_lwp_dme : 1, // Dcache Miss Event is supported by OS + os_lwp_cnh : 1, // CPU Clocks Not Halted event is supported by OS + os_lwp_rnh : 1, // CPU Reference clocks Not Halted event is supported= by OS + : 22, // Reserved + os_lwp_cont : 1, // LWP sampling in continuous mode is supported by OS + os_lwp_ptsc : 1, // Performance Time Stamp Counter in event records i= s supported by OS + os_lwp_int : 1; // Interrupt on threshold overflow is supported by OS + // ebx + u32 lwp_lwpcb_sz : 8, // LWP Control Block size, in quadwords + lwp_event_sz : 8, // LWP event record size, in bytes + lwp_max_events : 8, // LWP max supported EventID value (EventID 255 n= ot included) + lwp_event_offset : 8; // LWP events area offset in the LWP Control Blo= ck + // ecx + u32 lwp_latency_max : 5, // Number of bits in cache latency counters (= 10 to 31) + lwp_data_adddr : 1, // Cache miss events report the data address of t= he reference + lwp_latency_rnd : 3, // Amount by which cache latency is rounded + lwp_version : 7, // LWP implementation version + lwp_buf_min_sz : 8, // LWP event ring buffer min size, in units of 32= event records + : 4, // Reserved + lwp_branch_predict : 1, // Branches Retired events can be filtered + lwp_ip_filtering : 1, // IP filtering (IPI, IPF, BaseIP, and LimitIP @= LWPCP) supported + lwp_cache_levels : 1, // Cache-related events can be filtered by cache= level + lwp_cache_latency : 1; // Cache-related events can be filtered by late= ncy + // edx + u32 hw_lwp_avail : 1, // LWP is available in hardware + hw_lpwval : 1, // LWPVAL instruction is available in hardware + hw_lwp_ire : 1, // Instructions Retired Event is available in hardware + hw_lwp_bre : 1, // Branch Retired Event is available in hardware + hw_lwp_dme : 1, // Dcache Miss Event is available in hardware + hw_lwp_cnh : 1, // Clocks Not Halted event is available in hardware + hw_lwp_rnh : 1, // Reference clocks Not Halted event is available in = hardware + : 22, // Reserved + hw_lwp_cont : 1, // LWP sampling in continuous mode is available in h= ardware + hw_lwp_ptsc : 1, // Performance Time Stamp Counter in event records i= s available in hardware + hw_lwp_int : 1; // Interrupt on threshold overflow is available in ha= rdware +}; + +/* + * Leaf 0x8000001d + * AMD deterministic cache parameters + */ + +struct leaf_0x8000001d_0 { + // eax + u32 cache_type : 5, // Cache type field + cache_level : 3, // Cache level (1-based) + cache_self_init : 1, // Self-initializing cache level + fully_associative : 1, // Fully-associative cache + : 4, // Reserved + num_threads_sharing : 12, // Number of logical CPUs sharing cache + : 6; // Reserved + // ebx + u32 cache_linesize : 12, // System coherency line size (0-based) + cache_npartitions : 10, // Physical line partitions (0-based) + cache_nways : 10; // Ways of associativity (0-based) + // ecx + u32 cache_nsets : 31, // Cache number of sets (0-based) + : 1; // Reserved + // edx + u32 wbinvd_rll_no_guarantee : 1, // WBINVD/INVD not guaranteed for Remo= te Lower-Level caches + ll_inclusive : 1, // Cache is inclusive of Lower-Level caches + : 30; // Reserved +}; + +/* + * Leaf 0x8000001e + * AMD CPU topology enumeration + */ + +struct leaf_0x8000001e_0 { + // eax + u32 ext_apic_id : 32; // Extended APIC ID + // ebx + u32 core_id : 8, // Unique per-socket logical core unit ID + core_nthreas : 8, // #Threads per core (zero-based) + : 16; // Reserved + // ecx + u32 node_id : 8, // Node (die) ID of invoking logical CPU + nnodes_per_socket : 3, // #nodes in invoking logical CPU's package/soc= ket + : 21; // Reserved + // edx + u32 : 32; // Reserved +}; + +/* + * Leaf 0x8000001f + * AMD encrypted memory capabilities enumeration (SME/SEV) + */ + +struct leaf_0x8000001f_0 { + // eax + u32 sme : 1, // Secure Memory Encryption supported + sev : 1, // Secure Encrypted Virtualization supported + vm_page_flush : 1, // VM Page Flush MSR (0xc001011e) available + sev_encrypted_state : 1, // SEV Encrypted State supported + sev_nested_paging : 1, // SEV secure nested paging supported + vm_permission_levels : 1, // VMPL supported + rpmquery : 1, // RPMQUERY instruction supported + vmpl_sss : 1, // VMPL supervisor shadow stack supported + secure_tsc : 1, // Secure TSC supported + virt_tsc_aux : 1, // Hardware virtualizes TSC_AUX + sme_coherent : 1, // Cache coherency is enforced across encryption do= mains + req_64bit_hypervisor : 1, // SEV guest mandates 64-bit hypervisor + restricted_injection : 1, // Restricted Injection supported + alternate_injection : 1, // Alternate Injection supported + debug_swap : 1, // SEV-ES: full debug state swap is supported + disallow_host_ibs : 1, // SEV-ES: Disallowing IBS use by the host is s= upported + virt_transparent_enc : 1, // Virtual Transparent Encryption + vmgexit_paremeter : 1, // VmgexitParameter is supported in SEV_FEATURES + virt_tom_msr : 1, // Virtual TOM MSR is supported + virt_ibs : 1, // IBS state virtualization is supported for SEV-ES gue= sts + : 4, // Reserved + vmsa_reg_protection : 1, // VMSA register protection is supported + smt_protection : 1, // SMT protection is supported + : 2, // Reserved + svsm_page_msr : 1, // SVSM communication page MSR (0xc001f000) is sup= ported + nested_virt_snp_msr : 1, // VIRT_RMPUPDATE/VIRT_PSMASH MSRs are suppor= ted + : 2; // Reserved + // ebx + u32 pte_cbit_pos : 6, // PTE bit number used to enable memory encrypti= on + phys_addr_reduction_nbits : 6, // Reduction of phys address space when = encryption is enabled, in bits + vmpl_count : 4, // Number of VM permission levels (VMPL) supported + : 16; // Reserved + // ecx + u32 enc_guests_max : 32; // Max supported number of simultaneous encryp= ted guests + // edx + u32 min_sev_asid_no_sev_es : 32; // Minimum ASID for SEV-enabled SEV-ES-= disabled guest +}; + +/* + * Leaf 0x80000020 + * AMD Platform QoS extended feature IDs + */ + +struct leaf_0x80000020_0 { + // eax + u32 : 32; // Reserved + // ebx + u32 : 1, // Reserved + mba : 1, // Memory Bandwidth Allocation support + smba : 1, // Slow Memory Bandwidth Allocation support + bmec : 1, // Bandwidth Monitoring Event Configuration support + l3rr : 1, // L3 Range Reservation support + abmc : 1, // Assignable Bandwidth Monitoring Counters + sdciae : 1, // Smart Data Cache Injection (SDCI) Allocation Enforcem= ent + : 25; // Reserved + // ecx + u32 : 32; // Reserved + // edx + u32 : 32; // Reserved +}; + +struct leaf_0x80000020_1 { + // eax + u32 mba_limit_len : 32; // MBA enforcement limit size + // ebx + u32 : 32; // Reserved + // ecx + u32 : 32; // Reserved + // edx + u32 mba_cos_max : 32; // MBA max Class of Service number (zero-based) +}; + +struct leaf_0x80000020_2 { + // eax + u32 smba_limit_len : 32; // SMBA enforcement limit size + // ebx + u32 : 32; // Reserved + // ecx + u32 : 32; // Reserved + // edx + u32 smba_cos_max : 32; // SMBA max Class of Service number (zero-based) +}; + +struct leaf_0x80000020_3 { + // eax + u32 : 32; // Reserved + // ebx + u32 bmec_num_events : 8, // BMEC number of bandwidth events available + : 24; // Reserved + // ecx + u32 bmec_local_reads : 1, // Local NUMA reads can be tracked + bmec_remote_reads : 1, // Remote NUMA reads can be tracked + bmec_local_nontemp_wr : 1, // Local NUMA non-temporal writes can be tr= acked + bmec_remote_nontemp_wr : 1, // Remote NUMA non-temporal writes can be = tracked + bmec_local_slow_mem_rd : 1, // Local NUMA slow-memory reads can be tra= cked + bmec_remote_slow_mem_rd : 1, // Remote NUMA slow-memory reads can be t= racked + bmec_all_dirty_victims : 1, // Dirty QoS victims to all types of memor= y can be tracked + : 25; // Reserved + // edx + u32 : 32; // Reserved +}; + +/* + * Leaf 0x80000021 + * AMD extended features enumeration 2 + */ + +struct leaf_0x80000021_0 { + // eax + u32 no_nested_data_bp : 1, // No nested data breakpoints + fsgs_non_serializing : 1, // WRMSR to {FS,GS,KERNEL_GS}_BASE is non-se= rializing + lfence_serializing : 1, // LFENCE always serializing / synchronizes RD= TSC + smm_page_cfg_lock : 1, // SMM paging configuration lock + : 2, // Reserved + null_sel_clr_base : 1, // Null selector clears base + upper_addr_ignore : 1, // EFER MSR Upper Address Ignore + auto_ibrs : 1, // EFER MSR Automatic IBRS + no_smm_ctl_msr : 1, // SMM_CTL MSR (0xc0010116) is not available + fsrs : 1, // Fast Short Rep STOSB + fsrc : 1, // Fast Short Rep CMPSB + : 1, // Reserved + prefetch_ctl_msr : 1, // Prefetch control MSR is available + : 2, // Reserved + opcode_reclaim : 1, // Reserves opcode space + user_cpuid_disable : 1, // #GP when executing CPUID at CPL > 0 is supp= orted + epsf : 1, // Enhanced Predictive Store Forwarding + : 3, // Reserved + wl_feedback : 1, // Workload-based heuristic feedback to OS + : 1, // Reserved + eraps : 1, // Enhanced Return Address Predictor Security + : 2, // Reserved + sbpb : 1, // Selective Branch Predictor Barrier + ibpb_brtype : 1, // Branch predictions flushed from CPU branch predic= tor + srso_no : 1, // CPU is not subject to the SRSO vulnerability + srso_uk_no : 1, // CPU is not vulnerable to SRSO at user-kernel bound= ary + srso_msr_fix : 1; // Software may use MSR BP_CFG[BpSpecReduce] to mit= igate SRSO + // ebx + u32 microcode_patch_size : 16, // Size of microcode patch, in 16-byte un= its + rap_size : 8, // Return Address Predictor size + : 8; // Reserved + // ecx + u32 : 32; // Reserved + // edx + u32 : 32; // Reserved +}; + +/* + * Leaf 0x80000022 + * AMD Performance Monitoring v2 enumeration + */ + +struct leaf_0x80000022_0 { + // eax + u32 perfmon_v2 : 1, // Performance monitoring v2 supported + lbr_v2 : 1, // Last Branch Record v2 extensions (LBR Stack) + lbr_pmc_freeze : 1, // Freezing core performance counters / LBR Stack= supported + : 29; // Reserved + // ebx + u32 n_pmc_core : 4, // Number of core performance counters + lbr_v2_stack_size : 6, // Number of available LBR stack entries + n_pmc_northbridge : 6, // Number of available northbridge (data fabric= ) performance counters + n_pmc_umc : 6, // Number of available UMC performance counters + : 10; // Reserved + // ecx + u32 active_umc_bitmask : 32; // Active UMCs bitmask + // edx + u32 : 32; // Reserved +}; + +/* + * Leaf 0x80000023 + * AMD Secure Multi-key Encryption enumeration + */ + +struct leaf_0x80000023_0 { + // eax + u32 mem_hmk_mode : 1, // MEM-HMK encryption mode is supported + : 31; // Reserved + // ebx + u32 mem_hmk_avail_keys : 16, // MEM-HMK mode: total number of available = encryption keys + : 16; // Reserved + // ecx + u32 : 32; // Reserved + // edx + u32 : 32; // Reserved +}; + +/* + * Leaf 0x80000026 + * AMD extended topology enumeration v2 + */ + +struct leaf_0x80000026_0 { + // eax + u32 x2apic_id_shift : 5, // Bit width of this level (previous levels i= nclusive) + : 24, // Reserved + core_has_pwreff_ranking : 1, // This core has a power efficiency ranki= ng + domain_has_hybrid_cores : 1, // This domain level has hybrid (E, P) co= res + domain_core_count_asymm : 1; // The 'Core' domain has asymmetric cores= count + // ebx + u32 domain_lcpus_count : 16, // Number of logical CPUs at this domain in= stance + core_pwreff_ranking : 8, // This core's static power efficiency ranking + core_native_model_id : 4, // This core's native model ID + core_type : 4; // This core's type + // ecx + u32 domain_level : 8, // This domain level (subleaf ID) + domain_type : 8, // This domain type + : 16; // Reserved + // edx + u32 x2apic_id : 32; // x2APIC ID of current logical CPU +}; + +/* + * Leaf 0x80860000 + * Maximum Transmeta leaf number + CPU vendor ID string + */ + +struct leaf_0x80860000_0 { + // eax + u32 max_tra_leaf : 32; // Maximum supported Transmeta leaf number + // ebx + u32 cpu_vendorid_0 : 32; // Transmeta Vendor ID string bytes 0 - 3 + // ecx + u32 cpu_vendorid_2 : 32; // Transmeta Vendor ID string bytes 8 - 11 + // edx + u32 cpu_vendorid_1 : 32; // Transmeta Vendor ID string bytes 4 - 7 +}; + +/* + * Leaf 0x80860001 + * Transmeta extended CPU information + */ + +struct leaf_0x80860001_0 { + // eax + u32 stepping : 4, // Stepping ID + base_model : 4, // Base CPU model ID + base_family_id : 4, // Base CPU family ID + cpu_type : 2, // CPU type + : 18; // Reserved + // ebx + u32 cpu_rev_mask_minor : 8, // CPU revision ID, mask minor + cpu_rev_mask_major : 8, // CPU revision ID, mask major + cpu_rev_minor : 8, // CPU revision ID, minor + cpu_rev_major : 8; // CPU revision ID, major + // ecx + u32 cpu_base_mhz : 32; // CPU nominal frequency, in MHz + // edx + u32 recovery : 1, // Recovery CMS is active (after bad flush) + longrun : 1, // LongRun power management capabilities + : 1, // Reserved + lrti : 1, // LongRun Table Interface + : 28; // Reserved +}; + +/* + * Leaf 0x80860002 + * Transmeta Code Morphing Software (CMS) enumeration + */ + +struct leaf_0x80860002_0 { + // eax + u32 cpu_rev_id : 32; // CPU revision ID + // ebx + u32 cms_rev_mask_2 : 8, // CMS revision ID, mask component 2 + cms_rev_mask_1 : 8, // CMS revision ID, mask component 1 + cms_rev_minor : 8, // CMS revision ID, minor + cms_rev_major : 8; // CMS revision ID, major + // ecx + u32 cms_rev_mask_3 : 32; // CMS revision ID, mask component 3 + // edx + u32 : 32; // Reserved +}; + +/* + * Leaf 0x80860003 + * Transmeta CPU information string, bytes 0 - 15 + */ + +struct leaf_0x80860003_0 { + // eax + u32 cpu_info_0 : 32; // CPU info string bytes 0 - 3 + // ebx + u32 cpu_info_1 : 32; // CPU info string bytes 4 - 7 + // ecx + u32 cpu_info_2 : 32; // CPU info string bytes 8 - 11 + // edx + u32 cpu_info_3 : 32; // CPU info string bytes 12 - 15 +}; + +/* + * Leaf 0x80860004 + * Transmeta CPU information string, bytes 16 - 31 + */ + +struct leaf_0x80860004_0 { + // eax + u32 cpu_info_4 : 32; // CPU info string bytes 16 - 19 + // ebx + u32 cpu_info_5 : 32; // CPU info string bytes 20 - 23 + // ecx + u32 cpu_info_6 : 32; // CPU info string bytes 24 - 27 + // edx + u32 cpu_info_7 : 32; // CPU info string bytes 28 - 31 +}; + +/* + * Leaf 0x80860005 + * Transmeta CPU information string, bytes 32 - 47 + */ + +struct leaf_0x80860005_0 { + // eax + u32 cpu_info_8 : 32; // CPU info string bytes 32 - 35 + // ebx + u32 cpu_info_9 : 32; // CPU info string bytes 36 - 39 + // ecx + u32 cpu_info_10 : 32; // CPU info string bytes 40 - 43 + // edx + u32 cpu_info_11 : 32; // CPU info string bytes 44 - 47 +}; + +/* + * Leaf 0x80860006 + * Transmeta CPU information string, bytes 48 - 63 + */ + +struct leaf_0x80860006_0 { + // eax + u32 cpu_info_12 : 32; // CPU info string bytes 48 - 51 + // ebx + u32 cpu_info_13 : 32; // CPU info string bytes 52 - 55 + // ecx + u32 cpu_info_14 : 32; // CPU info string bytes 56 - 59 + // edx + u32 cpu_info_15 : 32; // CPU info string bytes 60 - 63 +}; + +/* + * Leaf 0x80860007 + * Transmeta live CPU information + */ + +struct leaf_0x80860007_0 { + // eax + u32 cpu_cur_mhz : 32; // Current CPU frequency, in MHz + // ebx + u32 cpu_cur_voltage : 32; // Current CPU voltage, in millivolts + // ecx + u32 cpu_cur_perf_pctg : 32; // Current CPU performance percentage, 0 - 1= 00 + // edx + u32 cpu_cur_gate_delay : 32; // Current CPU gate delay, in femtoseconds +}; + +/* + * Leaf 0xc0000000 + * Maximum Centaur/Zhaoxin leaf number + */ + +struct leaf_0xc0000000_0 { + // eax + u32 max_cntr_leaf : 32; // Maximum Centaur/Zhaoxin leaf number + // ebx + u32 : 32; // Reserved + // ecx + u32 : 32; // Reserved + // edx + u32 : 32; // Reserved +}; + +/* + * Leaf 0xc0000001 + * Centaur/Zhaoxin extended CPU features + */ + +struct leaf_0xc0000001_0 { + // eax + u32 : 32; // Reserved + // ebx + u32 : 32; // Reserved + // ecx + u32 : 32; // Reserved + // edx + u32 ccs_sm2 : 1, // CCS SM2 instructions + ccs_sm2_en : 1, // CCS SM2 enabled + rng : 1, // Random Number Generator + rng_en : 1, // RNG enabled + ccs_sm3_sm4 : 1, // CCS SM3 and SM4 instructions + ccs_sm3_sm4_en : 1, // CCS SM3/SM4 enabled + ace : 1, // Advanced Cryptography Engine + ace_en : 1, // ACE enabled + ace2 : 1, // Advanced Cryptography Engine v2 + ace2_en : 1, // ACE v2 enabled + phe : 1, // PadLock Hash Engine + phe_en : 1, // PHE enabled + pmm : 1, // PadLock Montgomery Multiplier + pmm_en : 1, // PMM enabled + : 2, // Reserved + parallax : 1, // Parallax auto adjust processor voltage + parallax_en : 1, // Parallax enabled + : 2, // Reserved + tm3 : 1, // Thermal Monitor v3 + tm3_en : 1, // TM v3 enabled + : 3, // Reserved + phe2 : 1, // PadLock Hash Engine v2 (SHA384/SHA512) + phe2_en : 1, // PHE v2 enabled + rsa : 1, // RSA instructions (XMODEXP/MONTMUL2) + rsa_en : 1, // RSA instructions enabled + : 3; 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Peter Anvin" , David Woodhouse , Sean Christopherson , Peter Zijlstra , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v4 07/34] x86/cpuid: Introduce a centralized CPUID data model Date: Fri, 15 Aug 2025 09:02:00 +0200 Message-ID: <20250815070227.19981-8-darwi@linutronix.de> In-Reply-To: <20250815070227.19981-1-darwi@linutronix.de> References: <20250815070227.19981-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable ** Context The x86-cpuid-db project generates a C header file with full C99 bitfield listings for all known CPUID leaf/subleaf query outputs. That header is now merged by parent commits at , and is in the form: struct leaf_0x0_0 { /* CPUID(0x0), subleaf 0, C99 bitfields */ }; ... struct leaf_0x7_0 { /* CPUID(0x7), subleaf 0, C99 bitfields */ }; struct leaf_0x7_1 { /* CPUID(0x7), subleaf 1, C99 bitfields */ }; ... ** Goal Introduce a structured, size-efficient, per-CPU, CPUID data repository. Use the x86-cpuid-db auto-generated data types, and custom CPUID leaf parsers, to build that repository. Given a leaf, subleaf, and index, provide direct memory access to the parsed and cached per-CPU CPUID output. ** Long-term goal Remove the need for drivers and other areas in the kernel to invoke direct CPUID queries. Only one place in the kernel should be allowed to use the CPUID instruction: the CPUID parser code. ** Implementation Introduce CPUID_LEAF() to build a compact CPUID storage layout in the form: struct leaf_0x0_0 leaf_0x0_0[1]; struct leaf_query_info leaf_0x0_0_info; struct leaf_0x1_0 leaf_0x1_0[1]; struct leaf_query_info leaf_0x0_0_info; struct leaf_0x4_0 leaf_0x4_0[8]; struct leaf_query_info leaf_0x4_0_info; ... where each CPUID leaf 0xN subleaf M query stores its output at the designated leaf_0xN_M[] array and has an associated "CPUID query info" structure. Introduce 'struct cpuid_leaves' to group all the parsed CPUID outputs and their metadata =E2=80=93in the layout above=E2=80=93 in one structure. Def= ine a 'struct cpuid_table' to wrap it, so that global per-table CPUID data can be added later. Embed that 'struct cpuid_table' inside 'struct cpuinfo_x86' to ensure early-boot and per-CPU access through the current CPU's capability structure. Given the data layout above, and assuming a CPU capability structure 'c', a macro can access CPUID(0x7) subleaf 0 parsed query output using the compile time tokenization below: const struct leaf_0x7_0 *l7_0; l7_0 =3D cpuid_subleaf(c, 0x7, 0); | | =E2=94=94=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=90 | =E2=94=94=E2=94=80=E2=94=80=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=90 | * * * &c.cpuid.leaf_0x7_0[0] Similarly, CPUID(0x7) subleaf 1 output can be accessed using the CPP tokenization: const struct leaf_0x7_1 *l7_1; l7_1 =3D cpuid_subleaf(c, 0x7, 1); | | =E2=94=94=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=90 | =E2=94=94=E2=94=80=E2=94=80=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=90 | * * * &c.cpuid.leaf_0x7_1[0] which all translate to a single assembly instruction offset calculation. Use an array of CPUID output storage entries for each leaf/subleaf combination to accommodate leaves which produce the same output format for a large subleaf range. This is typical for CPUID leaves enumerating hierarchical objects; e.g. CPUID(0x4) cache topology enumeration, CPUID(0xd) XSAVE enumeration, and CPUID(0x12) SGX Enclave Page Cache enumeration. In the CPUID_LEAF() data layout above, CPUID(0x4) has 8 storage entries to accomodate the suleaves 0 to 7, which all have the same bitfield's output format. With that, CPUID(0x4) subleaves 0->7 can be accessed using the compile time tokenization: const struct leaf_0x4_0 *l4_0, *l4_1, l4_2; l4_0 =3D cpuid_subleaf_index(c, 0x4, 0); | | =E2=94=94=E2=94=80=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=90 | =E2=94=94=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=90 | * * v &c.cpuid.leaf_0x4_0[0] l4_1 =3D cpuid_subleaf_index(c, 0x4, 1); | | =E2=94=94=E2=94=80=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=90 | =E2=94=94=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=90 | * * v &c.cpuid.leaf_0x4_0[1] l4_2 =3D cpuid_subleaf_index(c, 0x4, 2); | | =E2=94=94=E2=94=80=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=90 | =E2=94=94=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=90 | * * v &c.cpuid.leaf_0x4_0[2] where the indices 0, 1, 2 above can be provided dynamically. This is by design since call-sites hierarchical CPUID enumeration usually passes the CPUID subleaf enumeration index dynamically; e.g., within a for loop. For each of the CPUID leaf/subleaf output storage entries, attach a 'struct leaf_query_info' leaf_0xN_M_info instance. It is to be filled by the CPUID parsing logic filling the CPUID table(s). For now, this info structure has one element: the number of filled slots by the CPUID paraser in the CPUID leaf/subleaf output storage array. ** Call-site APIs Introduce below APIs for CPUID leaves with static subleaves: cpuid_subleaf(_cpuinfo, _leaf, _subleaf) cpuid_leaf(_cpuinfo, _leaf) cpuid_leaf_regs(_cpuinfo, _leaf) And below APIs for CPUID leaves with dynamic subleaves: cpuid_subleaf_count(_cpuinfo, _leaf) cpuid_subleaf_index(_cpuinfo, _leaf, _idx) cpuid_subleaf_index_regs(_cpuinfo, _leaf, _idx) At , add a clear rationale for why call sites should use the above APIs instead of directly invoking CPUID queries. ** Next steps For now, define entries for CPUID(0x0) and CPUID(0x1) in the CPUID table. Generic CPUID parser logic to fill the per-CPU CPUID tables, along with more CPUID leaves support, will be added next. Suggested-by: Thomas Gleixner # CPUID data model Suggested-by: Andrew Cooper # x86-cpuid-db sche= ma Suggested-by: Ingo Molnar # CPUID APIs restructuring Signed-off-by: Ahmed S. Darwish Link: https://lore.kernel.org/lkml/874ixernra.ffs@tglx Link: https://gitlab.com/x86-cpuid.org/x86-cpuid-db --- arch/x86/include/asm/cpuid/api.h | 254 +++++++++++++++++++++++++++++ arch/x86/include/asm/cpuid/types.h | 104 ++++++++++++ arch/x86/include/asm/processor.h | 2 + 3 files changed, 360 insertions(+) diff --git a/arch/x86/include/asm/cpuid/api.h b/arch/x86/include/asm/cpuid/= api.h index 2b9750cc8a75..0c8621d3cea0 100644 --- a/arch/x86/include/asm/cpuid/api.h +++ b/arch/x86/include/asm/cpuid/api.h @@ -289,4 +289,258 @@ static inline bool cpuid_amd_hygon_has_l3_cache(void) return cpuid_edx(0x80000006); } =20 +/* + * 'struct cpuid_leaves' accessors: + * + * For internal-use by the CPUID parser. These macros do not perform any + * sanity checks. + */ + +/** + * __cpuid_leaves_subleaf_idx() - Get parsed CPUID output (without sanity = checks) + * @_leaves: &struct cpuid_leaves instance + * @_leaf: CPUID leaf, in compile-time 0xN format + * @_subleaf: CPUID subleaf, in compile-time decimal format + * @_idx: @_leaf/@_subleaf CPUID output's storage array index. Check + * __CPUID_LEAF() for info on CPUID output storage arrays indexing. + * + * Returns the parsed CPUID output at @_leaves as a d= ata + * type: 'struct leaf_0xN_M', where 0xN is the token provided at @_leaf, a= nd M + * is token provided at @_subleaf. + */ +#define __cpuid_leaves_subleaf_idx(_leaves, _leaf, _subleaf, _idx) \ + ((_leaves)->leaf_ ## _leaf ## _ ## _subleaf)[_idx] + +/** + * __cpuid_leaves_subleaf_0() - Get parsed CPUID output (without sanity ch= ecks) + * @_leaves: &struct cpuid_leaves instance + * @_leaf: CPUID leaf, in compile-time 0xN format + * + * Like __cpuid_leaves_subleaf_idx(), but with subleaf =3D 0 and index =3D= 0. + */ +#define __cpuid_leaves_subleaf_0(_leaves, _leaf) \ + __cpuid_leaves_subleaf_idx(_leaves, _leaf, 0, 0) + +/** + * __cpuid_leaves_subleaf_info() - Get CPUID query info for @_leaf/@_suble= af + * @_leaves: &struct cpuid_leaves instance + * @_leaf: CPUID leaf, in compile-time 0xN format + * @_subleaf: CPUID subleaf, in compile-time decimal format + * + * Returns a pointer to the &struct leaf_query_info instance associated wi= th + * the given @_leaf/@_subleaf pair at the CPUID @_leaves data repository. = See + * __CPUID_LEAF(). + */ +#define __cpuid_leaves_subleaf_info(_leaves, _leaf, _subleaf) \ + ((_leaves)->leaf_ ## _leaf ## _ ## _subleaf ## _ ## info) + +/* + * 'struct cpuid_table' accessors: + * + * For internal-use by the CPUID parser. These macros perform the necessa= ry + * sanity checks by default. + */ + +/** + * __cpuid_table_subleaf_idx() - Get parsed CPUID output (with sanity chec= ks) + * @_table: &struct cpuid_table instance + * @_leaf: CPUID leaf, in compile-time 0xN format + * @_subleaf: CPUID subleaf, in compile-time decimal format + * @_idx: @_leaf/@_subleaf CPUID query output's storage array index. + * See __CPUID_LEAF(). + * + * Return a pointer to the requested parsed CPUID output at @_table, as a + * data type: 'struct leaf_0xN_M', where 0xN is the t= oken + * provided at @_leaf, and M is the token provided at @_subleaf; e.g. 'str= uct + * leaf_0x7_0'. + * + * Returns NULL if the requested CPUID @_leaf/@_subleaf/@_idx query output= is + * not present at @_table. + */ +#define __cpuid_table_subleaf_idx(_table, _leaf, _subleaf, _idx) \ + (((_idx) >=3D __cpuid_leaves_subleaf_info(&((_table)->leaves), _leaf, _su= bleaf).nr_entries) ? \ + NULL : &__cpuid_leaves_subleaf_idx(&((_table)->leaves), _leaf, _subleaf,= _idx)) + +/** + * __cpuid_table_subleaf() - Get parsed CPUID output (with sanity checks) + * @_table: &struct cpuid_table instance + * @_leaf: CPUID leaf, in compile-time 0xN format + * @_subleaf: CPUID subleaf, in compile-time decimal format + * + * Like __cpuid_table_subleaf_idx(), but with CPUID output storage index = =3D 0. + */ +#define __cpuid_table_subleaf(_table, _leaf, _subleaf) \ + __cpuid_table_subleaf_idx(_table, _leaf, _subleaf, 0) + +/* + * External APIs for accessing parsed CPUID data: + * + * Call sites should use below APIs instead of invoking direct CPUID queri= es. + * + * Benefits include: + * + * - Return CPUID output as typed C structures that are auto-generated fro= m a + * centralized database (see data type: 'struct leaf_0xN_M', wh= ere + * 0xN is the token provided at @_leaf, and M is the token provided at + * @_subleaf; e.g. struct leaf_0x7_0. + * + * Returns NULL if the requested CPUID @_leaf/@_subleaf query output is not + * present at the parsed CPUID table inside @_cpuinfo. This can happen if: + * + * - The CPUID table inside @_cpuinfo has not yet been populated. + * - The CPUID table inside @_cpuinfo was populated, but the CPU does not + * implement the requested CPUID @_leaf/@_subleaf combination. + * - The CPUID table inside @_cpuinfo was populated, but the kernel's CPUID + * parser has predetermined that the requested CPUID @_leaf/@_subleaf + * hardware output is invalid or unsupported. + * + * Example usage:: + * + * const struct leaf_0x7_0 *l7_0 =3D cpuid_subleaf(c, 0x7, 0); + * if (!l7_0) { + * // Handle error + * } + * + * const struct leaf_0x7_1 *l7_1 =3D cpuid_subleaf(c, 0x7, 1); + * if (!l7_1) { + * // Handle error + * } + */ +#define cpuid_subleaf(_cpuinfo, _leaf, _subleaf) \ + __cpuid_table_subleaf(&(_cpuinfo)->cpuid, _leaf, _subleaf) + +/** + * cpuid_leaf() - Access parsed CPUID data + * @_cpuinfo: CPU capability structure reference ('struct cpuinfo_x86') + * @_leaf: CPUID leaf, in compile-time 0xN format; e.g. 0x0, 0x2, 0x800000= 00 + * + * Similar to cpuid_subleaf(), but with a CPUID subleaf =3D 0. + * + * Example usage:: + * + * const struct leaf_0x0_0 *l0 =3D cpuid_leaf(c, 0x0); + * if (!l0) { + * // Handle error + * } + * + * const struct leaf_0x80000000_0 *el0 =3D cpuid_leaf(c, 0x80000000); + * if (!el0) { + * // Handle error + * } + */ +#define cpuid_leaf(_cpuinfo, _leaf) \ + cpuid_subleaf(_cpuinfo, _leaf, 0) + +/** + * cpuid_leaf_regs() - Access parsed CPUID data in raw format + * @_cpuinfo: CPU capability structure reference ('struct cpuinfo_x86') + * @_leaf: CPUID leaf, in compile-time 0xN format + * + * Similar to cpuid_leaf(), but returns a raw 'struct cpuid_regs' pointer = to + * the parsed CPUID data instead of a "typed" pointer. + */ +#define cpuid_leaf_regs(_cpuinfo, _leaf) \ + ((struct cpuid_regs *)(cpuid_leaf(_cpuinfo, _leaf))) + +#define __cpuid_assert_leaf_has_dynamic_subleaves(_cpuinfo, _leaf) \ + static_assert(ARRAY_SIZE((_cpuinfo)->cpuid.leaves.leaf_ ## _leaf ## _0) >= 1); + +/** + * cpuid_subleaf_index() - Access parsed CPUID data at runtime subleaf ind= ex + * @_cpuinfo: CPU capability structure reference ('struct cpuinfo_x86') + * @_leaf: CPUID leaf, in compile-time 0xN format; e.g. 0x4, 0x8000001d + * @_idx: Index within CPUID(@_leaf) output storage array. It must be + * smaller than "cpuid_subleaf_count(@_cpuinfo, @_leaf)". Unlike + * @_leaf, this value can be provided dynamically. + * + * For a given leaf/subleaf combination, the CPUID table inside @_cpuinfo + * contains an array of CPUID output storage entries. An array of storage + * entries is used to accommodate CPUID leaves which produce the same outp= ut + * format for a large subleaf range. This is common for CPUID hierarchical + * objects enumeration; e.g., CPUID(0x4) and CPUID(0xd). Check CPUID_LEAF= (). + * + * CPUID leaves that are to be accessed using this macro are specified at + * , 'struct cpuid_leaves', with a CPUID_LEAF() count field + * bigger than 1. A build-time error will be generated otherwise. + * + * Example usage:: + * + * const struct leaf_0x4_0 *l4; + * + * for (int i =3D 0; i < cpuid_subleaf_count(c, 0x4); i++) { + * l4 =3D cpuid_subleaf_index(c, 0x4, i); + * if (!l4) { + * // Handle error + * } + * + * // Access CPUID(0x4, i) data; e.g. l4->cache_type + * } + * + * Beside the standard error situations detailed at cpuid_subleaf(), this + * macro will return NULL if @_idx is out of range. + */ +#define cpuid_subleaf_index(_cpuinfo, _leaf, _idx) \ +({ \ + __cpuid_assert_leaf_has_dynamic_subleaves(_cpuinfo, _leaf); \ + __cpuid_table_subleaf_idx(&(_cpuinfo)->cpuid, _leaf, 0, _idx); \ +}) + +/** + * cpuid_subleaf_index_regs() - Access parsed CPUID data at runtime sublea= f index + * @_cpuinfo: CPU capability structure reference ('struct cpuinfo_x86') + * @_leaf: CPUID leaf, in compile-time 0xN format; e.g. 0x4, 0x8000001d + * @_idx: Index within CPUID(@_leaf) output storage array. It must be + * smaller than "cpuid_subleaf_count(@_cpuinfo, @_leaf)". + * + * Similar to cpuid_subleaf_index(), but returns a raw 'struct cpuid_regs' + * pointer to the parsed CPUID data, instead of a "typed" + * pointer. + */ +#define cpuid_subleaf_index_regs(_cpuinfo, _leaf, _idx) \ + ((struct cpuid_regs *)cpuid_subleaf_index(_cpuinfo, _leaf, _idx)) + +/** + * cpuid_subleaf_count() - Number of valid (filled) subleaves for @_leaf + * @_cpuinfo: CPU capability structure reference ('struct cpuinfo_x86') + * @_leaf: CPUID leaf, in compile-time 0xN format; e.g. 0x4, 0x8000001d + * + * Return the number of subleaves filled by the CPUID parser for @_leaf. C= heck + * cpuid_subleaf_index(). + * + * CPUID leaves that are to be accessed using this macro are specified at + * , 'struct cpuid_leaves', with a CPUID_LEAF() count field + * bigger than 1. A build-time error will be generated otherwise. + */ +#define cpuid_subleaf_count(_cpuinfo, _leaf) \ +({ \ + __cpuid_assert_leaf_has_dynamic_subleaves(_cpuinfo, _leaf); \ + __cpuid_leaves_subleaf_info(&(_cpuinfo)->cpuid.leaves, _leaf, 0).nr_entri= es; \ +}) + #endif /* _ASM_X86_CPUID_API_H */ diff --git a/arch/x86/include/asm/cpuid/types.h b/arch/x86/include/asm/cpui= d/types.h index 8a00364b79de..f1b51ba21ca4 100644 --- a/arch/x86/include/asm/cpuid/types.h +++ b/arch/x86/include/asm/cpuid/types.h @@ -5,6 +5,8 @@ #include #include =20 +#include + /* * Types for raw CPUID access: */ @@ -124,4 +126,106 @@ extern const struct leaf_0x2_table cpuid_0x2_table[25= 6]; */ #define TLB_0x63_2M_4M_ENTRIES 32 =20 +/* + * Types for centralized CPUID tables: + * + * For internal use by the CPUID parser. + */ + +/** + * struct leaf_query_info - Parse info for a CPUID leaf/subleaf query + * @nr_entries: Number of valid output storage entries filled by the CPUID= parser + * + * In a CPUID table (struct cpuid_leaves), each CPUID leaf/subleaf query o= utput + * storage entry from is paired with a unique instanc= e of + * this type. + */ +struct leaf_query_info { + unsigned int nr_entries; +}; + +/** + * __CPUID_LEAF() - Define CPUID output storage and query info entry + * @_name: Struct type name of the CPUID leaf/subleaf (e.g. 'leaf_0x4_0'). + * Such types are defined at , and follow the + * format 'struct leaf_0xN_M', where 0xN is the leaf and M is the + * subleaf. + * @_count: Number of storage entries to allocate for this leaf/subleaf + * + * For the given leaf/subleaf combination, define an array of CPUID output + * storage entries and an associated query info structure =E2=80=94 both r= esiding in a + * 'struct cpuid_leaves' instance. + * + * Use an array of storage entries to accommodate CPUID leaves which produ= ce + * the same output format for a large subleaf range. This is common for + * hierarchical objects enumeration; e.g., CPUID(0x4), CPUID(0xd), and + * CPUID(0x12). + * + * The example invocation for CPUID(0x7) storage, subleaves 0->1: + * + * __CPUID_LEAF(leaf_0x7_0, 1); + * __CPUID_LEAF(leaf_0x7_1, 1); + * + * generates 'struct cpuid_leaves' storage entries in the form:: + * + * struct leaf_0x7_0 leaf_0x7_0[1]; + * struct leaf_query_info leaf_0x7_0_info; + * + * struct leaf_0x7_1 leaf_0x7_1[1]; + * struct leaf_query_info leaf_0x7_1_info; + * + * The example invocation for CPUID(0x4) storage:: + * + * __CPUID_LEAF(leaf_0x4_0, 8); + * + * generates storage entries in the form: + * + * struct leaf_0x4_0 leaf_0x4_0[8]; + * struct leaf_query_info leaf_0x4_0_info; + * + * where the 'leaf_0x4_0[8]' storage array can accommodate the output of + * CPUID(0x4) subleaves 0->7, since they all have the same output format. + */ +#define __CPUID_LEAF(_name, _count) \ + struct _name _name[_count]; \ + struct leaf_query_info _name##_info + +/** + * CPUID_LEAF() - Define a CPUID storage entry in 'struct cpuid_leaves' + * @_leaf: CPUID Leaf number in the 0xN format; e.g., 0x4. + * @_subleaf: Subleaf number in decimal + * @_count: Number of repeated storage entries for this @_leaf/@_subleaf + * + * Convenience wrapper around __CPUID_LEAF(). + */ +#define CPUID_LEAF(_leaf, _subleaf, _count) \ + __CPUID_LEAF(leaf_ ## _leaf ## _ ## _subleaf, _count) + +/* + * struct cpuid_leaves - Structured CPUID data repository + */ +struct cpuid_leaves { + /* leaf subleaf count */ + CPUID_LEAF(0x0, 0, 1); + CPUID_LEAF(0x1, 0, 1); +}; + +/* + * Types for centralized CPUID tables: + * + * For external use. + */ + +/** + * struct cpuid_table - Per-CPU CPUID data repository + * @leaves: CPUID leaf/subleaf queries' output and metadata + * + * Embedded inside 'struct cpuinfo_x86' to provide access to stored, parse= d, + * and sanitized CPUID output per-CPU. Thus removing the need for any dir= ect + * CPUID query by call sites. + */ +struct cpuid_table { + struct cpuid_leaves leaves; +}; + #endif /* _ASM_X86_CPUID_TYPES_H */ diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/proces= sor.h index 910e36b0c00d..88f8ee33bfca 100644 --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -16,6 +16,7 @@ struct vm86; #include #include #include +#include #include #include #include @@ -164,6 +165,7 @@ struct cpuinfo_x86 { char x86_vendor_id[16]; char x86_model_id[64]; struct cpuinfo_topology topo; + struct cpuid_table cpuid; /* in KB - valid for CPUS which support this call: */ unsigned int x86_cache_size; int x86_cache_alignment; /* In bytes */ --=20 2.50.1 From nobody Sat Oct 4 14:35:16 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6F7E22D839D for ; Fri, 15 Aug 2025 07:05:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755241533; cv=none; b=CqHB2f63HqPusJereoGwUctIyc54rDDKQBfTQPfZkC4BUWXJF3rNT1/JN3DsXVtKrvvwYUHvqeHUqo7U4u5v6RxR2afzf62fdz3Zzi8rQ3bkYYLzbJkjjrOx1cMIrNms4ttZCe014Yre9sPcvFsw2hfgbX4beP1I9pbz0YI5xNk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755241533; c=relaxed/simple; bh=+hoL0ZGJs5fowZ2jfZQKzpEP1Y4+AhKTaXDxDF4tuPA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=HnOsGzPyZxPDWOIrsBT3RPa/qVxY6a0ciFAR7Y/cbTrsQPiYcy2TY7OR15c1gUbwI87Cpke92Ha5tr7zgd/JMf8HvrdZDa79wAIAoSu+rv/844P8WnZQMPoEGIVlupxsZEZIQOOJdCUFYcZ320WcUfH/vKyc5g8XzX6O7bjogJs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=Q0r3tQGW; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=rEBfr2jf; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="Q0r3tQGW"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="rEBfr2jf" From: "Ahmed S. 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Peter Anvin" , David Woodhouse , Sean Christopherson , Peter Zijlstra , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v4 08/34] x86/cpuid: Introduce a centralized CPUID parser Date: Fri, 15 Aug 2025 09:02:01 +0200 Message-ID: <20250815070227.19981-9-darwi@linutronix.de> In-Reply-To: <20250815070227.19981-1-darwi@linutronix.de> References: <20250815070227.19981-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Introduce a centralized CPUID parser to populate the per-CPU CPUID tables. To ensures consistent and early availablity of parsed CPUID data, invoke this parser during both early boot and secondary CPUs bring up. Since accessing the CPUID leaf output storage areas at 'struct cpuid_table' requires compile time tokenization, split the parser implementation into two stages: compile time macros for tokenizing the leaf/subleaf output offsets within a CPUID table, and generic runtime code to access and populate the relevant CPUID leaf/subleaf data structures using such offsets. For flexible parsing of CPUID leaf/subleaf outputs, support both generic and leaf-specific CPUID read functions. Suggested-by: Thomas Gleixner Signed-off-by: Ahmed S. Darwish --- arch/x86/include/asm/cpuid/api.h | 9 +++ arch/x86/include/asm/cpuid/types.h | 3 + arch/x86/kernel/cpu/Makefile | 1 + arch/x86/kernel/cpu/common.c | 2 + arch/x86/kernel/cpu/cpuid_parser.c | 121 +++++++++++++++++++++++++++++ arch/x86/kernel/cpu/cpuid_parser.h | 104 +++++++++++++++++++++++++ 6 files changed, 240 insertions(+) create mode 100644 arch/x86/kernel/cpu/cpuid_parser.c create mode 100644 arch/x86/kernel/cpu/cpuid_parser.h diff --git a/arch/x86/include/asm/cpuid/api.h b/arch/x86/include/asm/cpuid/= api.h index 0c8621d3cea0..b5a6e40419b7 100644 --- a/arch/x86/include/asm/cpuid/api.h +++ b/arch/x86/include/asm/cpuid/api.h @@ -5,8 +5,10 @@ #include =20 #include +#include #include =20 +#include #include =20 /* @@ -543,4 +545,11 @@ static inline bool cpuid_amd_hygon_has_l3_cache(void) __cpuid_leaves_subleaf_info(&(_cpuinfo)->cpuid.leaves, _leaf, 0).nr_entri= es; \ }) =20 +/* + * CPUID parser exported APIs: + */ + +void __init cpuid_parser_early_scan_cpu(struct cpuinfo_x86 *c); +void cpuid_parser_scan_cpu(struct cpuinfo_x86 *c); + #endif /* _ASM_X86_CPUID_API_H */ diff --git a/arch/x86/include/asm/cpuid/types.h b/arch/x86/include/asm/cpui= d/types.h index f1b51ba21ca4..320f152675af 100644 --- a/arch/x86/include/asm/cpuid/types.h +++ b/arch/x86/include/asm/cpuid/types.h @@ -32,6 +32,9 @@ enum cpuid_regs_idx { #define CPUID_LEAF_FREQ 0x16 #define CPUID_LEAF_TILE 0x1d =20 +#define CPUID_BASE_START 0x0 +#define CPUID_BASE_END (CPUID_BASE_START + 0xffff) + /* * Types for CPUID(0x2) parsing: */ diff --git a/arch/x86/kernel/cpu/Makefile b/arch/x86/kernel/cpu/Makefile index 1e26179ff18c..b2421cfb59ed 100644 --- a/arch/x86/kernel/cpu/Makefile +++ b/arch/x86/kernel/cpu/Makefile @@ -19,6 +19,7 @@ KCSAN_SANITIZE_common.o :=3D n =20 obj-y :=3D cacheinfo.o scattered.o obj-y +=3D topology_common.o topology_ext.o topology_amd.o +obj-y +=3D cpuid_parser.o obj-y +=3D common.o obj-y +=3D rdrand.o obj-y +=3D match.o diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 34a054181c4d..43582d7e167d 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -1729,6 +1729,7 @@ static void __init early_identify_cpu(struct cpuinfo_= x86 *c) =20 /* cyrix could have cpuid enabled via c_identify()*/ if (cpuid_feature()) { + cpuid_parser_scan_cpu(c); cpu_detect(c); get_cpu_vendor(c); intel_unlock_cpuid_leafs(c); @@ -2109,6 +2110,7 @@ void identify_secondary_cpu(unsigned int cpu) *c =3D boot_cpu_data; c->cpu_index =3D cpu; =20 + cpuid_parser_scan_cpu(c); identify_cpu(c); #ifdef CONFIG_X86_32 enable_sep_cpu(); diff --git a/arch/x86/kernel/cpu/cpuid_parser.c b/arch/x86/kernel/cpu/cpuid= _parser.c new file mode 100644 index 000000000000..80476e578fb8 --- /dev/null +++ b/arch/x86/kernel/cpu/cpuid_parser.c @@ -0,0 +1,121 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Centralized CPUID parser (for populating the system's CPUID tables.) + */ + +#include +#include + +#include +#include +#include + +#include "cpuid_parser.h" + +/* + * Leaf read functions: + */ + +/* + * Default CPUID parser read function + * + * Satisfies the requirements stated at 'struct cpuid_parse_entry'->read(). + */ +static void cpuid_read_generic(const struct cpuid_parse_entry *e, struct c= puid_read_output *output) +{ + for (int i =3D 0; i < e->maxcnt; i++, output->regs++, output->info->nr_en= tries++) + cpuid_read_subleaf(e->leaf, e->subleaf + i, output->regs); +} + +/* + * CPUID parser tables: + * + * Since these tables reference the leaf read functions above, they must be + * defined afterwards. + */ + +static const struct cpuid_parse_entry cpuid_parse_entries[] =3D { + CPUID_PARSE_ENTRIES +}; + +/* + * Leaf-independent parser code: + */ + +static unsigned int cpuid_range_max_leaf(const struct cpuid_table *t, unsi= gned int range) +{ + switch (range) { + case CPUID_BASE_START: return __cpuid_leaves_subleaf_0(&t->leaves, 0x0).m= ax_std_leaf; + default: return 0; + } +} + +static bool +cpuid_range_valid(const struct cpuid_table *t, unsigned int leaf, unsigned= int start, unsigned int end) +{ + if (leaf < start || leaf > end) + return false; + + return leaf =3D=3D start || leaf <=3D cpuid_range_max_leaf(t, start); +} + +static bool cpuid_leaf_in_range(const struct cpuid_table *t, unsigned int = leaf) +{ + return cpuid_range_valid(t, leaf, CPUID_BASE_START, CPUID_BASE_END); +} + +static void +cpuid_fill_table(struct cpuid_table *t, const struct cpuid_parse_entry ent= ries[], unsigned int nr_entries) +{ + const struct cpuid_parse_entry *entry =3D entries; + + for (unsigned int i =3D 0; i < nr_entries; i++, entry++) { + struct cpuid_read_output output =3D { + .regs =3D cpuid_table_query_regs_p(t, entry->regs_offs), + .info =3D cpuid_table_query_info_p(t, entry->info_offs), + }; + + if (!cpuid_leaf_in_range(t, entry->leaf)) + continue; + + WARN_ON_ONCE(output.info->nr_entries !=3D 0); + entry->read(entry, &output); + } +} + +/* + * Exported APIs: + */ + +/** + * cpuid_parser_scan_cpu() - Populate current CPU's CPUID table + * @c: CPU capability structure associated with the current CPU + * + * Populate the CPUID table embedded within @c with parsed CPUID data. Si= nce all CPUID + * instructions are invoked locally, this must be called on the CPU associ= ated with @c. + */ +void cpuid_parser_scan_cpu(struct cpuinfo_x86 *c) +{ + struct cpuid_table *table =3D &c->cpuid; + + /* + * For correctness, clear the CPUID table first. + * + * This is due to the CPUID parser APIs at using leaf->= nr_entries + * as a leaf validity check: non-zero means that the CPUID leaf's cached = output is + * valid. Otherwise, NULL is returned. + * + * For the primary CPU's early boot code, the tables are already zeroed. = For + * secondary CPUs though, their capability structures (containing the CPU= ID table) + * are copied from the primary CPU. This would result in a leaf->nr_entr= ies value + * carry over, unless the table is zeroed first. + * + * Also for CPUID table re-scans, which are triggered by hardware state c= hanges, + * previously valid CPUID leaves can become no longer available and thus = no longer + * parsed (leaving stale leaf "nr_entries" fields behind.) The table mus= t thus be + * also cleared. + */ + memset(table, 0, sizeof(*table)); + + cpuid_fill_table(table, cpuid_parse_entries, ARRAY_SIZE(cpuid_common_pars= e_entries)); +} diff --git a/arch/x86/kernel/cpu/cpuid_parser.h b/arch/x86/kernel/cpu/cpuid= _parser.h new file mode 100644 index 000000000000..48e962106d4a --- /dev/null +++ b/arch/x86/kernel/cpu/cpuid_parser.h @@ -0,0 +1,104 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _ARCH_X86_CPUID_PARSER_H +#define _ARCH_X86_CPUID_PARSER_H + +#include + +/* + * 'struct cpuid_leaves' CPUID query output storage area accessors: + * + * @_leaf: CPUID leaf, in compile-time 0xN format + * @_subleaf: CPUID subleaf, in compile-time decimal format + * + * Since accessing the CPUID leaf output storage areas at 'struct cpuid_le= aves' requires + * compile time tokenization, split the CPUID parser implementation into t= wo stages: + * compile time macros for tokenizing the leaf/subleaf output offsets with= in the CPUID + * table, and generic runtime code to access and populate the relevant CPU= ID leaf/subleaf + * output data structures using such offsets. + * + * That is, the output of the __cpuid_leaves_query_*_offset() macros will= be cached by a + * compile time "parse entry" (see 'struct cpuid_parse_entry'). The runti= me parser code + * will then utilize such offsets by passing them to cpuid_table_query_*_p= () functions. + */ + +#define __cpuid_leaves_query_regs_offset(_leaf, _subleaf) \ + offsetof(struct cpuid_leaves, leaf_ ## _leaf ## _ ## _subleaf) + +#define __cpuid_leaves_query_info_offset(_leaf, _subleaf) \ + offsetof(struct cpuid_leaves, leaf_ ## _leaf ## _ ## _subleaf ## _ ## inf= o) + +#define __cpuid_leaves_query_regs_maxcnt(_leaf, _subleaf) \ + ARRAY_SIZE(((struct cpuid_leaves *)NULL)->leaf_ ## _leaf ## _ ## _subleaf) + +static inline struct cpuid_regs * +cpuid_table_query_regs_p(const struct cpuid_table *t, unsigned long regs_o= ffset) +{ + return (struct cpuid_regs *)((unsigned long)(&t->leaves) + regs_offset); +} + +static inline struct leaf_query_info * +cpuid_table_query_info_p(const struct cpuid_table *t, unsigned long info_o= ffset) +{ + return (struct leaf_query_info *)((unsigned long)(&t->leaves) + info_offs= et); +} + +/** + * struct cpuid_read_output - Output of a CPUID parser read operation + * @regs: Pointer to an array of CPUID outputs, where each array element c= overs the + * full EAX->EDX output range. + * @info: Pointer to query info; for saving the number of filled @regs arr= ay elements. + * + * A CPUID parser read function like cpuid_read_generic() or cpuid_read_0x= N() uses this + * structure to save its CPUID query outputs. Actual storage for @regs an= d @info is provided + * by its caller, and is typically within a CPU's CPUID table (struct cpui= d_table.leaves). + * + * See struct cpuid_parse_entry.read(). + */ +struct cpuid_read_output { + struct cpuid_regs *regs; + struct leaf_query_info *info; +}; + +/** + * struct cpuid_parse_entry - Runtime CPUID parsing context for @leaf/@sub= leaf + * @leaf: Leaf number to be parsed + * @subleaf: Subleaf number to be parsed + * @regs_offs: Offset within 'struct cpuid_leaves' for saving CPUID @leaf/= @subleaf output; to be + * passed to cpuid_table_query_regs_p(). + * @info_offs: Offset within 'struct cpuid_leaves' for accessing @leaf/@su= bleaf parse info; to be + * passed to cpuid_table_query_info_p(). + * @maxcnt: Maximum number of output storage entries available for the @le= af/@subleaf query + * @read: Read function for this entry. It must save the parsed CPUID out= put to the passed + * 'struct cpuid_read_output'->regs registers array of size >=3D @maxcnt.= It must set + * 'struct cpuid_read_output'->info.nr_entries to the actual number of st= orage output + * entries filled. A generic implementation is provided at cpuid_read_ge= neric(). + */ +struct cpuid_parse_entry { + unsigned int leaf; + unsigned int subleaf; + unsigned int regs_offs; + unsigned int info_offs; + unsigned int maxcnt; + void (*read)(const struct cpuid_parse_entry *e, struct cpuid_read_output= *o); +}; + +#define CPUID_PARSE_ENTRY(_leaf, _subleaf, _reader_fn) \ + { \ + .leaf =3D _leaf, \ + .subleaf =3D _subleaf, \ + .regs_offs =3D __cpuid_leaves_query_regs_offset(_leaf, _subleaf), \ + .info_offs =3D __cpuid_leaves_query_info_offset(_leaf, _subleaf), \ + .maxcnt =3D __cpuid_leaves_query_regs_maxcnt(_leaf, _subleaf), \ + .read =3D cpuid_read_ ## _reader_fn, \ + } + +/* + * CPUID parser tables: + */ + +#define CPUID_PARSE_ENTRIES \ + /* Leaf Subleaf Reader function */ \ + CPUID_PARSE_ENTRY(0x0, 0, generic), \ + CPUID_PARSE_ENTRY(0x1, 0, generic), \ + +#endif /* _ARCH_X86_CPUID_PARSER_H */ --=20 2.50.1 From nobody Sat Oct 4 14:35:16 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ACBED2D97A6 for ; Fri, 15 Aug 2025 07:05:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755241536; cv=none; b=NIE0SH+7fip5FQVsCnV0KGkDHkaK+6M6xzE8nsM1ovYMuvm7nKfrW/xd84Kk/gsma1RaO0z7hkQtSXuZ4R7sBZ6LKX3MMRmvkfLciRrwoI1Ocxi7Y9oFppLrog80PoYTuKeWbZARVQplQyVOEdQYNjw9SM1YTTL/+wCD0IDPcOM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755241536; c=relaxed/simple; bh=GZR8RHQZex4Pd9dmQhrZYFm58mezVjJewpqZgR2DRr4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=vE5Bok9MzJRKRVQY5zD3vpjKYwqyXZXCkE1BDJlPH8hzy4inq59vXcEvQcrFLWinyvvU9f/lXjq06YNMJDtPcnjhe0OOafd+0ezZZgHhAEnRCi0toKTwXbLC+jrVj7QhsGBkI2sUH8qqodntNSpNDtrG6EAeylKf8nIQaQlsoS8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=NThzNQd1; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=0wwsp9IG; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="NThzNQd1"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="0wwsp9IG" From: "Ahmed S. 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Peter Anvin" , David Woodhouse , Sean Christopherson , Peter Zijlstra , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v4 09/34] x86/cpu: Use parsed CPUID(0x0) Date: Fri, 15 Aug 2025 09:02:02 +0200 Message-ID: <20250815070227.19981-10-darwi@linutronix.de> In-Reply-To: <20250815070227.19981-1-darwi@linutronix.de> References: <20250815070227.19981-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Use parsed CPUID(0x0) access instead of a direct CPUID query. Signed-off-by: Ahmed S. Darwish --- arch/x86/kernel/cpu/common.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 43582d7e167d..e081f92ddfe9 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -896,11 +896,12 @@ void get_cpu_vendor(struct cpuinfo_x86 *c) =20 void cpu_detect(struct cpuinfo_x86 *c) { - /* Get vendor name */ - cpuid(0x00000000, (unsigned int *)&c->cpuid_level, - (unsigned int *)&c->x86_vendor_id[0], - (unsigned int *)&c->x86_vendor_id[8], - (unsigned int *)&c->x86_vendor_id[4]); + const struct leaf_0x0_0 *l0 =3D cpuid_leaf(c, 0x0); + + c->cpuid_level =3D l0->max_std_leaf; + *(u32 *)&c->x86_vendor_id[0] =3D l0->cpu_vendorid_0; + *(u32 *)&c->x86_vendor_id[4] =3D l0->cpu_vendorid_1; + *(u32 *)&c->x86_vendor_id[8] =3D l0->cpu_vendorid_2; =20 c->x86 =3D 4; /* Intel-defined flags: level 0x00000001 */ --=20 2.50.1 From nobody Sat Oct 4 14:35:16 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9B7532DE216 for ; Fri, 15 Aug 2025 07:05:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755241539; cv=none; b=GjdOZ02pVitAM9P/GApZ6Vxgfnvgo4twftCJ2QuanqOBagVw8cBjw4pTW9aKIR0QDTgANjDbOODyxWyPdCRkF2n/DxksX8VtUuOk7fCiv7498ZtBIPFn9FmLKmff8nR5cc7NKLf2Fq7yovrqVzWbybWeV8pS7qBhMwu5bKQYJiA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755241539; c=relaxed/simple; bh=nQQACpTAwkqcWNfDbknx83g8jF2XxnMfwwW9ZlZCBJ0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Mf7utdLrCjV9w8ci0UcG87Rn9P4WdaiyIa3Prntlanq6HyRb8j27q9kx13H23KYZgJxseXoQbpXQRxgCTDHOPN4Al3razVAsnzE8nWeSFhPnXxE/IXCVNMzetVGxyCWgmkeUHLDDROPDK3IwnDagscCFqSzckBNllv3cq+YstKc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=A82YR3N4; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=JKRjkor/; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="A82YR3N4"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="JKRjkor/" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1755241535; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=iL6tkuAvwHy9mNQV4DTrTWhnS7pBdUouB/PbkHTIZzU=; b=A82YR3N4JQI0dAM+K8FWOR3ib4ILtRsKTWZFu1Or0gnaY34K20NXtkqrTMTkId4Vg5VKIq Nxl+58AxRglHg3gahuX82XQAZtU8/cpdgdr3MOiFBR64Wultahfq3sDbiTWJfDVkns0Zuf Yheiloam4YS6UKrvH6EdB707bONgbHDuee8ASt+++A5wIqDbATT0SfW26s5aovTJtv3O4K /mFBQLvxP52ktMHaWBQZ7kyviuAuyG8+TEHYeigWqtfbygTrjGdBqhnbE21o8MrPiDsFr8 SgNNxh4CufD6jAPhxGPcW16Nh9xOaWmIvOW+opixFwYkHfyT27/iaw57LZDJfA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1755241535; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=iL6tkuAvwHy9mNQV4DTrTWhnS7pBdUouB/PbkHTIZzU=; b=JKRjkor/FzdxOILTVuQCx1Fnbtv6yuRLGYDsqVcQjv0PxqFBVpXudAtU8EgvQx7LU+UaO8 rB9ZC78vXUkx3XDw== To: Borislav Petkov , Ingo Molnar , Dave Hansen Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , David Woodhouse , Sean Christopherson , Peter Zijlstra , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v4 10/34] x86/lib: Add CPUID(0x1) CPU family and model calculation Date: Fri, 15 Aug 2025 09:02:03 +0200 Message-ID: <20250815070227.19981-11-darwi@linutronix.de> In-Reply-To: <20250815070227.19981-1-darwi@linutronix.de> References: <20250815070227.19981-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The x86 library code provides x86_family() and x86_model(). They take raw CPUID(0x1) EAX register output, extract the necessary bitfields with bitwise operations, then calculate out the CPU family and model. In follow-up commits, the x86 code will use parsed CPUID access, along with its auto-generated CPUID leaf data structures and their detailed C99 bitfields. Introduce CPU family and model calculation functions to x86/lib that take the auto-generated 'struct leaf_0x1_0' data type. Refactor the pure CPU family and model calculation logic into internal static functions so that no logic is duplicated. Signed-off-by: Ahmed S. Darwish --- arch/x86/include/asm/cpu.h | 6 ++++++ arch/x86/lib/cpu.c | 41 ++++++++++++++++++++++---------------- 2 files changed, 30 insertions(+), 17 deletions(-) diff --git a/arch/x86/include/asm/cpu.h b/arch/x86/include/asm/cpu.h index ad235dda1ded..90902cd91335 100644 --- a/arch/x86/include/asm/cpu.h +++ b/arch/x86/include/asm/cpu.h @@ -7,7 +7,9 @@ #include #include #include + #include +#include =20 #ifndef CONFIG_SMP #define cpu_physical_id(cpu) boot_cpu_physical_apicid @@ -25,6 +27,10 @@ int mwait_usable(const struct cpuinfo_x86 *); unsigned int x86_family(unsigned int sig); unsigned int x86_model(unsigned int sig); unsigned int x86_stepping(unsigned int sig); + +unsigned int cpuid_family(const struct leaf_0x1_0 *l); +unsigned int cpuid_model(const struct leaf_0x1_0 *l); + #ifdef CONFIG_X86_BUS_LOCK_DETECT extern void __init sld_setup(struct cpuinfo_x86 *c); extern bool handle_user_split_lock(struct pt_regs *regs, long error_code); diff --git a/arch/x86/lib/cpu.c b/arch/x86/lib/cpu.c index 7ad68917a51e..eac217d637ac 100644 --- a/arch/x86/lib/cpu.c +++ b/arch/x86/lib/cpu.c @@ -1,36 +1,43 @@ // SPDX-License-Identifier: GPL-2.0-only #include #include + #include +#include =20 -unsigned int x86_family(unsigned int sig) +static unsigned int __x86_family(unsigned int base_fam, unsigned int ext_f= am) { - unsigned int x86; - - x86 =3D (sig >> 8) & 0xf; + return (base_fam =3D=3D 0xf) ? base_fam + ext_fam : base_fam; +} =20 - if (x86 =3D=3D 0xf) - x86 +=3D (sig >> 20) & 0xff; +static unsigned int +__x86_model(unsigned int family, unsigned int base_model, unsigned int ext= _model) +{ + return (family >=3D 0x6) ? base_model | ext_model << 4 : base_model; +} =20 - return x86; +unsigned int x86_family(unsigned int sig) +{ + return __x86_family((sig >> 8) & 0xf, (sig >> 20) & 0xff); } EXPORT_SYMBOL_GPL(x86_family); =20 -unsigned int x86_model(unsigned int sig) +unsigned int cpuid_family(const struct leaf_0x1_0 *l) { - unsigned int fam, model; - - fam =3D x86_family(sig); - - model =3D (sig >> 4) & 0xf; - - if (fam >=3D 0x6) - model +=3D ((sig >> 16) & 0xf) << 4; + return __x86_family(l->base_family_id, l->ext_family); +} =20 - return model; +unsigned int x86_model(unsigned int sig) +{ + return __x86_model(x86_family(sig), (sig >> 4) & 0xf, (sig >> 16) & 0xf); } EXPORT_SYMBOL_GPL(x86_model); =20 +unsigned int cpuid_model(const struct leaf_0x1_0 *l) +{ + return __x86_model(cpuid_family(l), l->base_model, l->ext_model); +} + unsigned int x86_stepping(unsigned int sig) { return sig & 0xf; --=20 2.50.1 From nobody Sat Oct 4 14:35:16 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2E32C2E1C4B for ; Fri, 15 Aug 2025 07:05:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755241541; cv=none; b=DUWUrM4MBwJKGLKMgBPzSNR6uOaDQsAVOkQfr9Wf4U5kLAcnbSSvI9gMVy8pl0xy8+LEXKy5t1pJgI1iWtGImELegp9tEJbXE/1Pleb0oAsi5bmC8HRyl72JvBEhLTxQAquCN+QRSKfnL2p+zU9ttBEhH5d2BrmRgbwhF0Nzylw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755241541; c=relaxed/simple; bh=+vVBraN4iyBq3O3zercHCT7qDeyXhzXuKKfitkLPY7Q=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=GXbqGhuSg1iyDIu2su2lFJ6RLAowBF7hRtx5c6XHFJpa4pg7D30DjOb7wHQfOmjAMo5ZC7hyuk+wkdr9e0jmgso2BlA+5dx/lcQIlOUiW7pv7kdBJKsurxH9ncjajPOWm/bcS+gVDfP9VLZrHllcoO04e833w3lrWwHD1ipkRGM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=nNdCNjro; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=GCudznR8; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="nNdCNjro"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="GCudznR8" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1755241538; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=RUTnqyEApieND9csbmEnB5DPZyvG6vYjpOqhiqML+ZQ=; b=nNdCNjroWClUbf7kQeJmSCf+dA87LbXDYlPTwEYeWZJ3anxmwHpGv8aSepag6SjlcGBtJr JgxbZEcmM6//PwrDgUK0Su65hruK1TGeMPmFVSBRBUFaBEnfRtUI8/RwKBaJd6oUsmDoAE 7pnoq52r1KS9rW90dC99R0j1Au28KXEDK4tOuFbjXqHYIPXDHSVpTrEYJ4V8S/SNc4bEcf rZhHWWVVVIdV7dq+eHCXDKt81PGETUFhBAdg6tMhdUdVr34WQuudO048Vc9wSAehlUYNSH LrMWYOYdWGhD/26hAHhsZPHcikAE0Xdu20CIWlgyLP/nFsvUirwDdmH0a1N8zg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1755241538; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=RUTnqyEApieND9csbmEnB5DPZyvG6vYjpOqhiqML+ZQ=; b=GCudznR88LPVhex/urx0rPjC9JlpV/yVHea9mQWQEDhf3do3APfpA2i2fCG0BMhViXXysq Vq0Ygf2vxf5VaWAQ== To: Borislav Petkov , Ingo Molnar , Dave Hansen Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , David Woodhouse , Sean Christopherson , Peter Zijlstra , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v4 11/34] x86/cpu: Use parsed CPUID(0x1) Date: Fri, 15 Aug 2025 09:02:04 +0200 Message-ID: <20250815070227.19981-12-darwi@linutronix.de> In-Reply-To: <20250815070227.19981-1-darwi@linutronix.de> References: <20250815070227.19981-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Use parsed CPUID(0x1) access, instead of a direct CPUID query, at early boot CPU detection code. Beside the centralization benefits of the new CPUID model APIs, this allows using the auto-generated leaf data types and their full C99 bitfields instead of performing ugly bitwise operations on CPUID register output. Signed-off-by: Ahmed S. Darwish --- arch/x86/kernel/cpu/common.c | 16 +++++++--------- 1 file changed, 7 insertions(+), 9 deletions(-) diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index e081f92ddfe9..f989c8099490 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -897,6 +897,7 @@ void get_cpu_vendor(struct cpuinfo_x86 *c) void cpu_detect(struct cpuinfo_x86 *c) { const struct leaf_0x0_0 *l0 =3D cpuid_leaf(c, 0x0); + const struct leaf_0x1_0 *l1 =3D cpuid_leaf(c, 0x1); =20 c->cpuid_level =3D l0->max_std_leaf; *(u32 *)&c->x86_vendor_id[0] =3D l0->cpu_vendorid_0; @@ -904,17 +905,14 @@ void cpu_detect(struct cpuinfo_x86 *c) *(u32 *)&c->x86_vendor_id[8] =3D l0->cpu_vendorid_2; =20 c->x86 =3D 4; - /* Intel-defined flags: level 0x00000001 */ - if (c->cpuid_level >=3D 0x00000001) { - u32 junk, tfms, cap0, misc; =20 - cpuid(0x00000001, &tfms, &misc, &junk, &cap0); - c->x86 =3D x86_family(tfms); - c->x86_model =3D x86_model(tfms); - c->x86_stepping =3D x86_stepping(tfms); + if (l1) { + c->x86 =3D cpuid_family(l1); + c->x86_model =3D cpuid_model(l1); + c->x86_stepping =3D l1->stepping; =20 - if (cap0 & (1<<19)) { - c->x86_clflush_size =3D ((misc >> 8) & 0xff) * 8; + if (l1->clflush) { + c->x86_clflush_size =3D l1->clflush_size * 8; c->x86_cache_alignment =3D c->x86_clflush_size; } } --=20 2.50.1 From nobody Sat Oct 4 14:35:16 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 32F362E2DCD for ; Fri, 15 Aug 2025 07:05:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755241545; cv=none; b=WOW6cWY7n0MjEHbZXv/WxjOSoRed6gG2s/0+FGBB37yopajK20Azu1eVgSbPYxZlh5Q5DTgRo+sAaPsKgW0W1vlcXtfCIG/JP28TezOhjoMlZUKp54rBYN9w5pg+YUpZlUONhRb36MOJNHwaPXF2mkj375E3VIIP3as3whIT9YU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755241545; c=relaxed/simple; bh=oV/fZ8mujpFAr6wYDng1io4GmCwn7FzBxgsoYQBBGek=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=hCU1a7mA5zI2BXDZUUHy0HbdQYBmtrX5WD04r1Y6qYhpMGtx8V11HFULgT2sq7mlJcNEh3E+hE2a0Pr75YqDLX5Lr5f6YNRpF4WHpqcokhWOJSYizf59wB+fui40szGAeMmGuAiYHI/dKvHGbRK3PHDh9r+lPRvixthf718d4IM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=t9cCLScj; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=zC1k19Vk; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="t9cCLScj"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="zC1k19Vk" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1755241541; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=0YdLX/IqqO4CKKT2ZUvYFekYqtfCaupjSFTQr8qfc1Y=; b=t9cCLScjHQ3uLSc+w0vq46FX9ql38dAj3ya3z6xPGRzDYBwdh6HvHG3hsMLvDdSJV2Q0Lh PtMPavih33DuTA0KetMuH+eypUZ/fjM0CBRI7DvVpdp56GpYiIb3tJb8ZQqZaqONnfdADc 2+i4cP9/PPLKDop9bWIAyHQNs51yaKwwcgxu7zhrDiYn/7Yxme2SDWIS4VKpvWso4BcTEE ijXyqkaHXimroPNjOnRvZTiEdx6cjo1qQyL7ieZ9VexA2XBuFlR/kwf9XZRD8pm8dxKi/O 3tY5r2tgwltk9mML0oY2zCPJHVoikhOPcFpiFzPpbB+EkExl46ZZvDELUjj8GA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1755241541; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=0YdLX/IqqO4CKKT2ZUvYFekYqtfCaupjSFTQr8qfc1Y=; b=zC1k19Vkf0VgcUL0ZBW5hNTtKCizk2XH6zbaUjxxACt1Wf2TINhao83Mz7g4dK9614mTzi TOw9fqlAP2hyDTDg== To: Borislav Petkov , Ingo Molnar , Dave Hansen Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , David Woodhouse , Sean Christopherson , Peter Zijlstra , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v4 12/34] x86/cpuid: Parse CPUID(0x80000000) Date: Fri, 15 Aug 2025 09:02:05 +0200 Message-ID: <20250815070227.19981-13-darwi@linutronix.de> In-Reply-To: <20250815070227.19981-1-darwi@linutronix.de> References: <20250815070227.19981-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add CPUID parser logic for CPUID(0x80000000). Similar to kernel/head_32.S and kernel/cpu/common.c, verify the CPUID(0x80000000) query output beforehand. This is due to x86-32 machines without an extended CPUID range, where a CPUID(0x80000000) query will just repeat the max-valid standard CPUID leaf output. References: 8a50e5135af0 ("x86-32: Use symbolic constants, safer CPUID when= enabling EFER.NX") References: 67ad24e6d39c ("- pre5: - Rasmus Andersen: add proper...") #= Historical git Suggested-by: Andrew Cooper Suggested-by: Thomas Gleixner Signed-off-by: Ahmed S. Darwish Cc: "H. Peter Anvin" Link: https://lore.kernel.org/r/d4fcfd91-cc92-4b3c-9dd2-56ecd754cecc@citrix= .com --- arch/x86/include/asm/cpuid/types.h | 7 ++++++- arch/x86/kernel/cpu/cpuid_parser.c | 27 ++++++++++++++++++++++++++- arch/x86/kernel/cpu/cpuid_parser.h | 1 + 3 files changed, 33 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/cpuid/types.h b/arch/x86/include/asm/cpui= d/types.h index 320f152675af..d0f0e6a8a457 100644 --- a/arch/x86/include/asm/cpuid/types.h +++ b/arch/x86/include/asm/cpuid/types.h @@ -33,7 +33,11 @@ enum cpuid_regs_idx { #define CPUID_LEAF_TILE 0x1d =20 #define CPUID_BASE_START 0x0 -#define CPUID_BASE_END (CPUID_BASE_START + 0xffff) +#define CPUID_EXT_START 0x80000000 + +#define __CPUID_RANGE_END(idx) ((idx) + 0xffff) +#define CPUID_BASE_END __CPUID_RANGE_END(CPUID_BASE_START) +#define CPUID_EXT_END __CPUID_RANGE_END(CPUID_EXT_START) =20 /* * Types for CPUID(0x2) parsing: @@ -211,6 +215,7 @@ struct cpuid_leaves { /* leaf subleaf count */ CPUID_LEAF(0x0, 0, 1); CPUID_LEAF(0x1, 0, 1); + CPUID_LEAF(0x80000000, 0, 1); }; =20 /* diff --git a/arch/x86/kernel/cpu/cpuid_parser.c b/arch/x86/kernel/cpu/cpuid= _parser.c index 80476e578fb8..be9c8571f886 100644 --- a/arch/x86/kernel/cpu/cpuid_parser.c +++ b/arch/x86/kernel/cpu/cpuid_parser.c @@ -27,6 +27,29 @@ static void cpuid_read_generic(const struct cpuid_parse_= entry *e, struct cpuid_r cpuid_read_subleaf(e->leaf, e->subleaf + i, output->regs); } =20 +static void cpuid_read_0x80000000(const struct cpuid_parse_entry *e, struc= t cpuid_read_output *output) +{ + struct leaf_0x80000000_0 *l =3D (struct leaf_0x80000000_0 *)output->regs; + + cpuid_read_subleaf(e->leaf, e->subleaf, l); + + /* + * Protect against 32-bit CPUs lacking an extended CPUID range: Ensure th= at the + * returned max extended CPUID leaf is in the 0x80000001-0x8000ffff range. + * + * Do not depend on leaving 'info->nr_entries' set as zero, but zero-out = the + * whole leaf output area as well. This is due to the CPUID parser inter= nals + * using the __cpuid_leaves_subleaf_0() API to get the cached max extende= d leaf, + * which does not do any sanity checks, + */ + if ((l->max_ext_leaf & 0xffff0000) !=3D 0x80000000) { + *l =3D (struct leaf_0x80000000_0){ }; + return; + } + + output->info->nr_entries =3D 1; +} + /* * CPUID parser tables: * @@ -46,6 +69,7 @@ static unsigned int cpuid_range_max_leaf(const struct cpu= id_table *t, unsigned i { switch (range) { case CPUID_BASE_START: return __cpuid_leaves_subleaf_0(&t->leaves, 0x0).m= ax_std_leaf; + case CPUID_EXT_START: return __cpuid_leaves_subleaf_0(&t->leaves, 0x800= 00000).max_ext_leaf; default: return 0; } } @@ -61,7 +85,8 @@ cpuid_range_valid(const struct cpuid_table *t, unsigned i= nt leaf, unsigned int s =20 static bool cpuid_leaf_in_range(const struct cpuid_table *t, unsigned int = leaf) { - return cpuid_range_valid(t, leaf, CPUID_BASE_START, CPUID_BASE_END); + return cpuid_range_valid(t, leaf, CPUID_BASE_START, CPUID_BASE_END) || + cpuid_range_valid(t, leaf, CPUID_EXT_START, CPUID_EXT_END); } =20 static void diff --git a/arch/x86/kernel/cpu/cpuid_parser.h b/arch/x86/kernel/cpu/cpuid= _parser.h index 48e962106d4a..c2b78badd67e 100644 --- a/arch/x86/kernel/cpu/cpuid_parser.h +++ b/arch/x86/kernel/cpu/cpuid_parser.h @@ -100,5 +100,6 @@ struct cpuid_parse_entry { /* Leaf Subleaf Reader function */ \ CPUID_PARSE_ENTRY(0x0, 0, generic), \ CPUID_PARSE_ENTRY(0x1, 0, generic), \ + CPUID_PARSE_ENTRY(0x80000000, 0, 0x80000000), =20 #endif /* _ARCH_X86_CPUID_PARSER_H */ --=20 2.50.1 From nobody Sat Oct 4 14:35:16 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 175302E36E1 for ; Fri, 15 Aug 2025 07:05:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755241547; cv=none; b=u5dIUIzDrFz6pPamsa3bmMWRj7aD8CcdB5CeCy+jWNnzY2z3X84VVJpc0XXgD5mM1CVsCAfnxOvpuSIVfUeAeA19r+zyqxWwrB+uvHRVJI+4AA72ic1C6G4oOl6CaFkS9V2vutmQqsEqwJ92JrO9Ev2xLhe9N6FBv/VlsMq8i2Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755241547; c=relaxed/simple; bh=TsepN/EN4yDneUnLhlfnROZ/pgzLY1M8ub/dQ0YSiVo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=DUKpc3nfL3btZAikd0zASp00ADu4xNWkicNWz6m+rGkVKa1z6OvNtpHGumZUPFsZP8mfYu/UeAH5uPVjSXzHkVXVkGreiYg9KDGU+rJxUZ0xoN6UM21SM/1SODGbjhdHSQTQ59zSNgo56CRtt7NuOAqL9eOdbsKjyDNXcVAJPVw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=hSpmWnGd; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=Exq/h+mD; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="hSpmWnGd"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="Exq/h+mD" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1755241544; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=tOnzDrwMeCT8sT2NClHc7gMvrFgWabPLEjgLirDzaDM=; b=hSpmWnGd/JS0DRy2+5AvSwPQpeo6HJREoSkRNNAkyiejyYv5+NSZjAItAuC0S+zCuuymZL ZlJ9PRuZiU+x634j2BHt0rRvq45nESeU5EBUal0085DFy+S+Ph9rE6mNVCCI4ZeJN1seN9 1pxbkTmRAuvtcnL9Gzk2mlbNJIkiuOr0Oo/1/FLE8/pmAB+ih7fM0VASQCAGuZp+vmLDYY vxj1SvDM5ZjuHb2WSnJRYH5WvF9gCrSPhTAibv2Rh5WEC9YIFXLIBZVJedqzzl/rowwTVG FAK6Z+Xz2pkMJhJYAgqBHfEPrpG5BVtov6x2oYG0OgQczNiZtyJ4zvEAcEEd2w== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1755241544; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=tOnzDrwMeCT8sT2NClHc7gMvrFgWabPLEjgLirDzaDM=; b=Exq/h+mDarBWc3rot0ymYTrkTtoHDW/2Y1uG7u4dHr68816GTu7MR1TTR3mz5x8wrGxUpF 3A6TN5a38EoKwLBQ== To: Borislav Petkov , Ingo Molnar , Dave Hansen Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , David Woodhouse , Sean Christopherson , Peter Zijlstra , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v4 13/34] x86/cpu: Use parsed CPUID(0x80000000) Date: Fri, 15 Aug 2025 09:02:06 +0200 Message-ID: <20250815070227.19981-14-darwi@linutronix.de> In-Reply-To: <20250815070227.19981-1-darwi@linutronix.de> References: <20250815070227.19981-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Use parsed CPUID(0x80000000) access instead of a direct CPUID query. The affected code has the check: (eax & 0xffff0000) =3D=3D 0x80000000 to protect against Intel 32-bit CPUs that lack extended CPUID support. A similar check is already done at the CPUID(0x80000000) scanner read function at cpuid_parser.c: /* * Protect against 32-bit CPUs lacking extended CPUID support: Max * extended CPUID leaf must be in the 0x80000001-0x8000ffff range. */ if ((l->max_ext_leaf & 0xffff0000) !=3D 0x80000000) { // Handle error } Thus, just check that the parsed CPUID macro: cpuid_leaf(c, 0x80000000) does not return NULL, thus providing a sanity check similar to the original code. Signed-off-by: Ahmed S. Darwish --- arch/x86/kernel/cpu/common.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index f989c8099490..6b5a4dd2f33e 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -971,6 +971,7 @@ static void init_speculation_control(struct cpuinfo_x86= *c) =20 void get_cpu_cap(struct cpuinfo_x86 *c) { + const struct leaf_0x80000000_0 *el0; u32 eax, ebx, ecx, edx; =20 /* Intel-defined flags: level 0x00000001 */ @@ -1006,12 +1007,8 @@ void get_cpu_cap(struct cpuinfo_x86 *c) c->x86_capability[CPUID_D_1_EAX] =3D eax; } =20 - /* - * Check if extended CPUID leaves are implemented: Max extended - * CPUID leaf must be in the 0x80000001-0x8000ffff range. - */ - eax =3D cpuid_eax(0x80000000); - c->extended_cpuid_level =3D ((eax & 0xffff0000) =3D=3D 0x80000000) ? eax = : 0; + el0 =3D cpuid_leaf(c, 0x80000000); + c->extended_cpuid_level =3D (el0) ? el0->max_ext_leaf : 0; =20 if (c->extended_cpuid_level >=3D 0x80000001) { cpuid(0x80000001, &eax, &ebx, &ecx, &edx); --=20 2.50.1 From nobody Sat Oct 4 14:35:16 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EC7022D1F5E for ; Fri, 15 Aug 2025 07:05:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755241550; cv=none; b=Z6B8r01U7cMBh8ipdOaCnLz3HFdOUTgUX1PGE/jX8ICq34V/Yt1qCFzqv7Yx6SAED6ytZxePMQK3+oms8B4MwFvccIHLwznNoNDCK+RgeTbrLAyE7MXFSP3xyfWl+8YuAbAkfvwW63vYHia4lXQi5BPHugZREl/uDp5DwpQlzSg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755241550; c=relaxed/simple; bh=KjXnRCgG+3JjYSr6lZ6UGTlRo7eGOmxnmQ+my1w1n+E=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=IFXs7qIUYslGLGImGqj+cpZWmsG5rb6FfVI9D1kVTczMk1frw0Zh+O7Y5VWimvb52THIZK8Tz34kzVJH44+W7o9cX0UBfaLB60XOC/WXXw/GI3x9UO7AseUOvd0uV9txND24/h+s7I1DuvQEt5PK+JKmmvMBUGONMmgQqXKRsXE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=o8Yae4uF; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=2Iuo87uj; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="o8Yae4uF"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="2Iuo87uj" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1755241547; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=44qPXyYhlclQe+A2g0zv80/SvaG5TaAv4fQg2ML/Ylw=; b=o8Yae4uFLfTjP0mXXIbwv2sid1oGZCpAHHbOci6W26BUIwbDR7sy5jHqjJQhXazPzHr9q4 R8KD94ZGp5VW/678ZaFQIHVDTZONbRLXaZv89aEbbdBdKlXRJ9XtRCJhV6EMCRd/E5FU2c n4boryXxCDuDVanUNFLCL9hXCMHXvY3zNfeBCcN8s3/XLRLgh973ewt/UMU9riai2RKIpU cP1aPCejozESxKg0SxNPbo5oTM6gEcrXUTzuaEg17eCvGgOKUfo+7eGk6uvqc9VN1/dwjN AsHUmONRQF+O3itVQo1NvWYnJlLd0lEfe6wdgJfCHAy9IIfv+1uAZK91b20/3A== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1755241547; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=44qPXyYhlclQe+A2g0zv80/SvaG5TaAv4fQg2ML/Ylw=; b=2Iuo87ujOTusjDqd3HHzQz+awjtgwr24gEzHCTFHtZK3TMjCF5EVClvJQNtHgazucLaXtq 7f20S5aO7swN00AA== To: Borislav Petkov , Ingo Molnar , Dave Hansen Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , David Woodhouse , Sean Christopherson , Peter Zijlstra , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v4 14/34] x86/cpuid: Introduce a CPUID leaf x86 vendor table Date: Fri, 15 Aug 2025 09:02:07 +0200 Message-ID: <20250815070227.19981-15-darwi@linutronix.de> In-Reply-To: <20250815070227.19981-1-darwi@linutronix.de> References: <20250815070227.19981-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" For the CPUID parser, introduce a table listing vendor-specific CPUID leaves. Not all CPUID leaves should be queried on all x86 vendors, so the parser will only enumerate such leaves if the boot machine's x86 vendor is listed as supported. This provides the following benefits: (a) Even when a CPUID leaf falls within the CPU's standard or extended maximum leaf range, querying architecturally unsupported and reserved CPUID leaves may trigger new kernel boot behaviors or subtle bugs, especially on legacy machines. (b) Associating x86 vendor information with CPUID leaves will enable the CPUID parser to emit (lightweight) error messages when malformed CPUID leaf output is detected. This is due to the parser now being more certain that the queried leaf is valid on the machine. (c) Attaching x86 vendor information to CPUID leaves will relieve call-sites, especially drivers, from ugly x86 vendor checks before querying a CPUID leaf. If the CPUID parsers API like cpuid_leaf() or cpuid_subleaf() return NULL, it willy simply implies the leaf is simply unavailable (or should not be queried) on the current machine. Split the CPUID parsing table into an "early boot" table and a standard one. The early boot phase parses only CPUID(0x0) and CPUID(0x1), where they will be needed to identify the CPU's x86 vendor. Once the kernel saves the vendor info to the CPU's capability structure, invoke the CPUID parser again to parse the rest of the CPUID leaves. In that second phase, the parser assumes that "boot_cpu_data.x86_vendor" is valid and uses it for CPUID leaf x86 vendor validity checks. For each vendor-specific CPUID leaf, build its list of matching x86 vendors using CPP varargs. Encoding this as bitflags was not doable, since the x86 vendor IDs are just raw monotonic numbers from 0 (Intel) to 11 (Vortex). Keep the CPUID parser's vendor-specific leaf table empty for now. Leaves like CPUID(0x2), CPUID(0x4), CPUID(0x16), and CPUID(0x8000001d) will be added to the vendor table once their support is actually added to the parser. Signed-off-by: Ahmed S. Darwish --- arch/x86/kernel/cpu/common.c | 3 +- arch/x86/kernel/cpu/cpuid_parser.c | 108 ++++++++++++++++++++++++----- arch/x86/kernel/cpu/cpuid_parser.h | 51 +++++++++++++- 3 files changed, 142 insertions(+), 20 deletions(-) diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 6b5a4dd2f33e..048b285e7741 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -1725,9 +1725,10 @@ static void __init early_identify_cpu(struct cpuinfo= _x86 *c) =20 /* cyrix could have cpuid enabled via c_identify()*/ if (cpuid_feature()) { - cpuid_parser_scan_cpu(c); + cpuid_parser_early_scan_cpu(c); cpu_detect(c); get_cpu_vendor(c); + cpuid_parser_scan_cpu(c); intel_unlock_cpuid_leafs(c); get_cpu_cap(c); setup_force_cpu_cap(X86_FEATURE_CPUID); diff --git a/arch/x86/kernel/cpu/cpuid_parser.c b/arch/x86/kernel/cpu/cpuid= _parser.c index be9c8571f886..84d70a432212 100644 --- a/arch/x86/kernel/cpu/cpuid_parser.c +++ b/arch/x86/kernel/cpu/cpuid_parser.c @@ -12,6 +12,10 @@ =20 #include "cpuid_parser.h" =20 +static const struct cpuid_vendor_entry cpuid_vendor_entries[] =3D { + CPUID_VENDOR_ENTRIES +}; + /* * Leaf read functions: */ @@ -55,10 +59,24 @@ static void cpuid_read_0x80000000(const struct cpuid_pa= rse_entry *e, struct cpui * * Since these tables reference the leaf read functions above, they must be * defined afterwards. + * + * At early boot, only leaves at CPUID_EARLY_PARSE_ENTRIES should be parse= d. */ =20 -static const struct cpuid_parse_entry cpuid_parse_entries[] =3D { - CPUID_PARSE_ENTRIES +static const struct cpuid_parse_entry cpuid_early_parse_entries[] =3D { + CPUID_EARLY_PARSE_ENTRIES +}; + +static const struct cpuid_parse_entry cpuid_common_parse_entries[] =3D { + CPUID_COMMON_PARSE_ENTRIES +}; + +static const struct { + const struct cpuid_parse_entry *table; + int nr_entries; +} cpuid_parser_phases[] =3D { + { cpuid_early_parse_entries, ARRAY_SIZE(cpuid_early_parse_entries) }, + { cpuid_common_parse_entries, ARRAY_SIZE(cpuid_common_parse_entries) }, }; =20 /* @@ -89,6 +107,32 @@ static bool cpuid_leaf_in_range(const struct cpuid_tabl= e *t, unsigned int leaf) cpuid_range_valid(t, leaf, CPUID_EXT_START, CPUID_EXT_END); } =20 +static bool cpuid_leaf_matches_vendor(unsigned int leaf, u8 cpu_vendor) +{ + const struct cpuid_parse_entry *p =3D cpuid_early_parse_entries; + const struct cpuid_vendor_entry *v =3D cpuid_vendor_entries; + + /* Leaves in the early boot parser table are vendor agnostic */ + for (int i =3D 0; i < ARRAY_SIZE(cpuid_early_parse_entries); i++, p++) + if (p->leaf =3D=3D leaf) + return true; + + /* Leaves in the vendor table must pass a CPU vendor check */ + for (int i =3D 0; i < ARRAY_SIZE(cpuid_vendor_entries); i++, v++) { + if (v->leaf !=3D leaf) + continue; + + for (unsigned int j =3D 0; j < v->nvendors; j++) + if (cpu_vendor =3D=3D v->vendors[j]) + return true; + + return false; + } + + /* Remaining leaves are vendor agnostic */ + return true; +} + static void cpuid_fill_table(struct cpuid_table *t, const struct cpuid_parse_entry ent= ries[], unsigned int nr_entries) { @@ -103,28 +147,21 @@ cpuid_fill_table(struct cpuid_table *t, const struct = cpuid_parse_entry entries[] if (!cpuid_leaf_in_range(t, entry->leaf)) continue; =20 + if (!cpuid_leaf_matches_vendor(entry->leaf, boot_cpu_data.x86_vendor)) + continue; + WARN_ON_ONCE(output.info->nr_entries !=3D 0); entry->read(entry, &output); } } =20 -/* - * Exported APIs: - */ - -/** - * cpuid_parser_scan_cpu() - Populate current CPU's CPUID table - * @c: CPU capability structure associated with the current CPU - * - * Populate the CPUID table embedded within @c with parsed CPUID data. Si= nce all CPUID - * instructions are invoked locally, this must be called on the CPU associ= ated with @c. - */ -void cpuid_parser_scan_cpu(struct cpuinfo_x86 *c) +static void __cpuid_parser_scan_cpu(struct cpuinfo_x86 *c, bool early_boot) { + int nphases =3D early_boot ? 1 : ARRAY_SIZE(cpuid_parser_phases); struct cpuid_table *table =3D &c->cpuid; =20 /* - * For correctness, clear the CPUID table first. + * After early boot, clear the CPUID table first. * * This is due to the CPUID parser APIs at using leaf->= nr_entries * as a leaf validity check: non-zero means that the CPUID leaf's cached = output is @@ -140,7 +177,44 @@ void cpuid_parser_scan_cpu(struct cpuinfo_x86 *c) * parsed (leaving stale leaf "nr_entries" fields behind.) The table mus= t thus be * also cleared. */ - memset(table, 0, sizeof(*table)); + if (!early_boot) + memset(table, 0, sizeof(*table)); + + for (int i =3D 0; i < nphases; i++) + cpuid_fill_table(table, cpuid_parser_phases[i].table, cpuid_parser_phase= s[i].nr_entries); +} + +/* + * Exported APIs: + */ + +/** + * cpuid_parser_scan_cpu() - Populate the current CPU's CPUID table + * @c: CPU capability structure for the current CPU + * + * Populate the CPUID table embedded within @c with parsed CPUID data. Sin= ce all CPUID + * instructions are invoked locally, this must be run on the CPU associate= d with @c. + * + * cpuid_parser_early_scan_cpu() must've been called, at least once, befor= ehand. + */ +void cpuid_parser_scan_cpu(struct cpuinfo_x86 *c) +{ + __cpuid_parser_scan_cpu(c, false); +} =20 - cpuid_fill_table(table, cpuid_parse_entries, ARRAY_SIZE(cpuid_common_pars= e_entries)); +/** + * cpuid_parser_early_scan_cpu() - Populate primary CPU's CPUID table on e= arly boot + * @c: CPU capability structure associated with the current CPU + * + * Populate the CPUID table embedded within @c with parsed CPUID data. + * + * This must be called at early boot, so that the boot code can identify t= he CPU's + * x86 vendor. Only CPUID(0x0) and CPUID(0x1) are parsed. + * + * After saving the x86 vendor info in the boot CPU's capability structure, + * cpuid_parser_scan_cpu() must be called to complete the CPU's CPUID tabl= e. + */ +void __init cpuid_parser_early_scan_cpu(struct cpuinfo_x86 *c) +{ + __cpuid_parser_scan_cpu(c, true); } diff --git a/arch/x86/kernel/cpu/cpuid_parser.h b/arch/x86/kernel/cpu/cpuid= _parser.h index c2b78badd67e..5d7a05e4b9cd 100644 --- a/arch/x86/kernel/cpu/cpuid_parser.h +++ b/arch/x86/kernel/cpu/cpuid_parser.h @@ -96,10 +96,57 @@ struct cpuid_parse_entry { * CPUID parser tables: */ =20 -#define CPUID_PARSE_ENTRIES \ +/* + * Early-boot CPUID leaves (to be parsed before x86 vendor detection) + * + * These leaves must be parsed at early boot to identify the x86 vendor. T= he + * parser treats them as universally valid across all vendors. + * + * At early boot, only leaves in this table must be parsed. For all other + * leaves, the CPUID parser will assume that "boot_cpu_data.x86_vendor" is + * properly set beforehand. + * + * Note: If these entries are to be modified, please adapt the kernel-doc = of + * cpuid_parser_early_scan_cpu() accordingly. + */ +#define CPUID_EARLY_PARSE_ENTRIES \ /* Leaf Subleaf Reader function */ \ CPUID_PARSE_ENTRY(0x0, 0, generic), \ CPUID_PARSE_ENTRY(0x1, 0, generic), \ - CPUID_PARSE_ENTRY(0x80000000, 0, 0x80000000), + +/* + * Common CPUID leaves + * + * These leaves can be parsed once basic x86 vendor detection is in place. + * Further vendor-agnostic leaves, which are not needed at early boot, are= also + * listed here. + * + * For vendor-specific leaves, a matching entry must be added to the CPUID= leaf + * vendor table later defined. Leaves which are here, but without a matchi= ng + * vendor entry, are treated by the CPUID parser as valid for all x86 vend= ors. + */ +#define CPUID_COMMON_PARSE_ENTRIES \ + /* Leaf Subleaf Reader function */ \ + CPUID_PARSE_ENTRY(0x80000000, 0, 0x80000000), \ + +/* + * CPUID leaf vendor table: + */ + +struct cpuid_vendor_entry { + unsigned int leaf; + u8 vendors[X86_VENDOR_NUM]; + u8 nvendors; +}; + +#define CPUID_VENDOR_ENTRY(_leaf, ...) \ + { \ + .leaf =3D _leaf, \ + .vendors =3D { __VA_ARGS__ }, \ + .nvendors =3D (sizeof((u8[]){__VA_ARGS__})/sizeof(u8)), \ + } + +#define CPUID_VENDOR_ENTRIES \ + /* Leaf Vendor list */ \ =20 #endif /* _ARCH_X86_CPUID_PARSER_H */ --=20 2.50.1 From nobody Sat Oct 4 14:35:16 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E923D2E5427 for ; Fri, 15 Aug 2025 07:05:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755241555; cv=none; b=Pt8NEEQsC5c55Y3SAEM0LQqcxo1uRabHOg3G51wcaNH8PDPCGvMXXh2wgYwE4RKOQaAAzN+5fUSZbEAG8VcCX+N554Je+qoRVDscGKeEV1csBt/MUG1umP9lN4bvZ5E1Zkzrq6LFrJq6x4E1d0FYV4SeTxzyPdA3gk3Gog4BXJM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755241555; c=relaxed/simple; bh=PyVA86oM4856fHuH2OtWGqH1muetJmQk14kCXYD++WU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=OdvDTKasfAbZ9MnuoDQB/wxom0WPSoayQUVSCNhq4tai4D4h3IiHQwo5cJ8UGnyg3qu0yTffbqWtJ+zZ3Xgaj63+1ojAX7hWkJvQ/A5VCDKs3S0SATGTdvRhzUIMoEpBDGIQyebRyKpPVpmnh43ZXfJFRzbwaUR5j7/GhO/LQnU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=k1CXdkOr; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=2WeGBUwL; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="k1CXdkOr"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="2WeGBUwL" From: "Ahmed S. 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Peter Anvin" , David Woodhouse , Sean Christopherson , Peter Zijlstra , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v4 15/34] x86/cpuid: Introduce CPUID parser debugfs interface Date: Fri, 15 Aug 2025 09:02:08 +0200 Message-ID: <20250815070227.19981-16-darwi@linutronix.de> In-Reply-To: <20250815070227.19981-1-darwi@linutronix.de> References: <20250815070227.19981-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Introduce the debugfs files 'x86/cpuid/[0-ncpus]' to dump each CPU's cached CPUID table. For each cached CPUID leaf/subleaf, invoke the CPUID instruction on the target CPU and compare the hardware result against the cached values. Mark any mismatched cached CPUID output value with an asterisk. This should help with tricky bug reports in the future, if/when the cached CPUID tables get unexpectedly out of sync with actual hardware state. It also simplifies the development and testing of adding new CPUID leaves to the CPUID parser. Note, expose cpuid_parse_phases[] via "cpuid_parser.h" to allow the debugfs code to traverse and dump the parsed CPUID data. Signed-off-by: Ahmed S. Darwish --- arch/x86/kernel/cpu/Makefile | 2 +- arch/x86/kernel/cpu/cpuid_debugfs.c | 108 ++++++++++++++++++++++++++++ arch/x86/kernel/cpu/cpuid_parser.c | 9 ++- arch/x86/kernel/cpu/cpuid_parser.h | 12 ++++ 4 files changed, 125 insertions(+), 6 deletions(-) create mode 100644 arch/x86/kernel/cpu/cpuid_debugfs.c diff --git a/arch/x86/kernel/cpu/Makefile b/arch/x86/kernel/cpu/Makefile index b2421cfb59ed..4e032ad851c7 100644 --- a/arch/x86/kernel/cpu/Makefile +++ b/arch/x86/kernel/cpu/Makefile @@ -61,7 +61,7 @@ obj-$(CONFIG_X86_LOCAL_APIC) +=3D perfctr-watchdog.o obj-$(CONFIG_HYPERVISOR_GUEST) +=3D vmware.o hypervisor.o mshyperv.o obj-$(CONFIG_ACRN_GUEST) +=3D acrn.o =20 -obj-$(CONFIG_DEBUG_FS) +=3D debugfs.o +obj-$(CONFIG_DEBUG_FS) +=3D debugfs.o cpuid_debugfs.o =20 obj-$(CONFIG_X86_BUS_LOCK_DETECT) +=3D bus_lock.o =20 diff --git a/arch/x86/kernel/cpu/cpuid_debugfs.c b/arch/x86/kernel/cpu/cpui= d_debugfs.c new file mode 100644 index 000000000000..62aa92f7d226 --- /dev/null +++ b/arch/x86/kernel/cpu/cpuid_debugfs.c @@ -0,0 +1,108 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * CPUID parser debugfs entries: x86/cpuid/[0-ncpus] + * + * Dump each CPU's cached CPUID table and compare its values against curre= nt + * CPUID output on that CPU. Mark changed entries with an asterisk. + */ + +#include +#include +#include +#include + +#include +#include +#include + +#include "cpuid_parser.h" + +static void cpuid_this_cpu(void *info) +{ + struct cpuid_regs *regs =3D info; + + __cpuid(®s->eax, ®s->ebx, ®s->ecx, ®s->edx); +} + +static void +cpuid_show_leaf(struct seq_file *m, uintptr_t cpu_id, const struct cpuid_p= arse_entry *entry, + const struct leaf_query_info *info, const struct cpuid_regs *cached) +{ + for (int j =3D 0; j < info->nr_entries; j++) { + u32 subleaf =3D entry->subleaf + j; + struct cpuid_regs regs =3D { + .eax =3D entry->leaf, + .ecx =3D subleaf, + }; + int ret; + + seq_printf(m, "Leaf 0x%08x, subleaf %u:\n", entry->leaf, subleaf); + + ret =3D smp_call_function_single(cpu_id, cpuid_this_cpu, ®s, true); + if (ret) { + seq_printf(m, "Failed to invoke CPUID on CPU %lu: %d\n\n", cpu_id, ret); + continue; + } + + seq_printf(m, " cached: %cEAX=3D0x%08x %cEBX=3D0x%08x %cECX=3D0x%= 08x %cEDX=3D0x%08x\n", + cached[j].eax =3D=3D regs.eax ? ' ' : '*', cached[j].eax, + cached[j].ebx =3D=3D regs.ebx ? ' ' : '*', cached[j].ebx, + cached[j].ecx =3D=3D regs.ecx ? ' ' : '*', cached[j].ecx, + cached[j].edx =3D=3D regs.edx ? ' ' : '*', cached[j].edx); + seq_printf(m, " actual: EAX=3D0x%08x EBX=3D0x%08x ECX=3D0x%08x= EDX=3D0x%08x\n", + regs.eax, regs.ebx, regs.ecx, regs.edx); + } +} + +static void __cpuid_debug_show(struct seq_file *m, uintptr_t cpu_id, + const struct cpuid_parse_entry *entry, int nr_entries) +{ + const struct cpuinfo_x86 *c =3D per_cpu_ptr(&cpu_info, cpu_id); + const struct cpuid_table *t =3D &c->cpuid; + + for (int i =3D 0; i < nr_entries; i++, entry++) { + const struct leaf_query_info *qi =3D cpuid_table_query_info_p(t, entry->= info_offs); + const struct cpuid_regs *qr =3D cpuid_table_query_regs_p(t, entry->regs_= offs); + + cpuid_show_leaf(m, cpu_id, entry, qi, qr); + } +} + +static int cpuid_debug_show(struct seq_file *m, void *p) +{ + uintptr_t cpu_id =3D (uintptr_t)m->private; + + for (int i =3D 0; i < cpuid_parser_nphases; i++) + __cpuid_debug_show(m, cpu_id, cpuid_parser_phases[i].table, cpuid_parser= _phases[i].nr_entries); + + return 0; +} + +static int cpuid_debug_open(struct inode *inode, struct file *file) +{ + return single_open(file, cpuid_debug_show, inode->i_private); +} + +static const struct file_operations cpuid_ops =3D { + .open =3D cpuid_debug_open, + .read =3D seq_read, + .llseek =3D seq_lseek, + .release =3D single_release, +}; + +static __init int cpuid_init_debugfs(void) +{ + struct dentry *dir; + uintptr_t cpu_id; + char cpu_name[24]; + + dir =3D debugfs_create_dir("cpuid", arch_debugfs_dir); + + for_each_possible_cpu(cpu_id) { + scnprintf(cpu_name, sizeof(cpu_name), "%lu", cpu_id); + debugfs_create_file(cpu_name, 0444, dir, (void *)cpu_id, &cpuid_ops); + } + + return 0; +} +late_initcall(cpuid_init_debugfs); diff --git a/arch/x86/kernel/cpu/cpuid_parser.c b/arch/x86/kernel/cpu/cpuid= _parser.c index 84d70a432212..3942ea2526f2 100644 --- a/arch/x86/kernel/cpu/cpuid_parser.c +++ b/arch/x86/kernel/cpu/cpuid_parser.c @@ -71,14 +71,13 @@ static const struct cpuid_parse_entry cpuid_common_pars= e_entries[] =3D { CPUID_COMMON_PARSE_ENTRIES }; =20 -static const struct { - const struct cpuid_parse_entry *table; - int nr_entries; -} cpuid_parser_phases[] =3D { +const struct cpuid_parser_phase cpuid_parser_phases[] =3D { { cpuid_early_parse_entries, ARRAY_SIZE(cpuid_early_parse_entries) }, { cpuid_common_parse_entries, ARRAY_SIZE(cpuid_common_parse_entries) }, }; =20 +const int cpuid_parser_nphases =3D ARRAY_SIZE(cpuid_parser_phases); + /* * Leaf-independent parser code: */ @@ -157,7 +156,7 @@ cpuid_fill_table(struct cpuid_table *t, const struct cp= uid_parse_entry entries[] =20 static void __cpuid_parser_scan_cpu(struct cpuinfo_x86 *c, bool early_boot) { - int nphases =3D early_boot ? 1 : ARRAY_SIZE(cpuid_parser_phases); + int nphases =3D early_boot ? 1 : cpuid_parser_nphases; struct cpuid_table *table =3D &c->cpuid; =20 /* diff --git a/arch/x86/kernel/cpu/cpuid_parser.h b/arch/x86/kernel/cpu/cpuid= _parser.h index 5d7a05e4b9cd..1be5c323d5eb 100644 --- a/arch/x86/kernel/cpu/cpuid_parser.h +++ b/arch/x86/kernel/cpu/cpuid_parser.h @@ -129,6 +129,18 @@ struct cpuid_parse_entry { /* Leaf Subleaf Reader function */ \ CPUID_PARSE_ENTRY(0x80000000, 0, 0x80000000), \ =20 +/* + * CPUID parser tables repository: + */ + +struct cpuid_parser_phase { + const struct cpuid_parse_entry *table; + int nr_entries; +}; + +extern const struct cpuid_parser_phase cpuid_parser_phases[]; +extern const int cpuid_parser_nphases; + /* * CPUID leaf vendor table: */ --=20 2.50.1 From nobody Sat Oct 4 14:35:16 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D8FA12D29AA for ; Fri, 15 Aug 2025 07:05:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755241556; cv=none; b=iFR7DJBv6jsuLwL9TU+2DutbUEb2lg0hXGNG0f4XyLzX5mZGzp0ofc4QEybyzpo60OsYSd7oJwUzK5JyJzO8Q7KvdkLdSRniigEH2Y63FREAegnc2yteVJ6lPsFKx+7Ewrrv26vphgdZcsmb+bsKIk3bk2+IEY3JBOARRV4vErg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755241556; c=relaxed/simple; bh=/VE63AtxVVj73KkvZcEIf/zdUBoXijIRRqYaialVL7o=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=kDwF+agXbpuh6O9pdRnMnlLK3sOpYsYBOGk4aDZyQQaFOygjQJwV5Bg8TBrgCIuSGXhZRMOKmJa/sV5XM+Ob91/Hj24DA3Pb47ycTHE65mqk3d9+QTM/jSU3gOZJ0GRYfgD1QAwbi8e4VIImuzVVwmSnzUnwQ5MKIiJEXB2vols= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=iCx4OQM7; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=npkJut/e; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="iCx4OQM7"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="npkJut/e" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1755241553; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=TMgezEz1RsvC1uFOjiCB0IYTpuqnq6yks4w29vKpSDM=; b=iCx4OQM7lx9jUy0QLYn02JDIbV+5ZB93nyT7smALSj+VxOvJmCjWFR2DuJrzhz02JMqGVp WzU2UCYnco1DKfBa83k85FLunS9OFGDll0yFLuYTn6PVJU6FRy4KK3iUOQf5By+mwo0pqn CmzAufFrGXF75m83+kh1AcAf9+/GJowYouA3wxd6lR5hqZT5T0OY2AJHPSIiArru3F18ku KsZC7nK1DFnfUfJZgMS4AC8bbQEx8fbHiE9gl0VVBrA/ism0923zsch6D+vqKDtfibpmyH tlanUS1flVJ1sq5hG69V5f2PA1a12Y0dZG7RVrDhuqaPRQRRR09ognoXAmyiSw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1755241553; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=TMgezEz1RsvC1uFOjiCB0IYTpuqnq6yks4w29vKpSDM=; b=npkJut/ebDeEIDeVIJ1sXN93Z489B8/qIOxZe7OKCy4f74CxZolbOUtA4M6CLG2fRatuZ8 /xCLcyHTBl6c7ZAg== To: Borislav Petkov , Ingo Molnar , Dave Hansen Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , David Woodhouse , Sean Christopherson , Peter Zijlstra , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v4 16/34] x86/cpuid: Parse CPUID(0x2) Date: Fri, 15 Aug 2025 09:02:09 +0200 Message-ID: <20250815070227.19981-17-darwi@linutronix.de> In-Reply-To: <20250815070227.19981-1-darwi@linutronix.de> References: <20250815070227.19981-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add CPUID(0x2) support to the CPUID parser. Query CPUID(0x2) only for Intel, Centaur, and Zhaoxin. Such vendor information was extracted from the kernel's boot code, given that kernel/cpu/cacheinfo.c :: init_intel_cacheinfo() is called by kernel/cpu/intel.c cpu_dev.c_x86_vendor =3D X86_VENDOR_INTEL kernel/cpu/centaur.c cpu_dev.c_x86_vendor =3D X86_VENDOR_CENTAUR kernel/cpu/zhaoxin.c cpu_dev.c_x86_vendor =3D X86_VENDOR_ZHAOXIN At the CPUID leaf output table, keep CPUID(0x2) marked as invalidif the whole leaf, or all of its output registers separately, were malformed. Note, the cpuid_leaf_0x2() logic at will be removed once all CPUID(0x2) call sites are transformed to the new CPUID model. References: fe78079ec07f ("x86/cpu: Introduce and use CPUID leaf 0x2 parsin= g helpers") Signed-off-by: Ahmed S. Darwish --- arch/x86/include/asm/cpuid/types.h | 1 + arch/x86/kernel/cpu/cpuid_parser.c | 35 ++++++++++++++++++++++++++++++ arch/x86/kernel/cpu/cpuid_parser.h | 2 ++ 3 files changed, 38 insertions(+) diff --git a/arch/x86/include/asm/cpuid/types.h b/arch/x86/include/asm/cpui= d/types.h index d0f0e6a8a457..7bbf0671cb95 100644 --- a/arch/x86/include/asm/cpuid/types.h +++ b/arch/x86/include/asm/cpuid/types.h @@ -215,6 +215,7 @@ struct cpuid_leaves { /* leaf subleaf count */ CPUID_LEAF(0x0, 0, 1); CPUID_LEAF(0x1, 0, 1); + CPUID_LEAF(0x2, 0, 1); CPUID_LEAF(0x80000000, 0, 1); }; =20 diff --git a/arch/x86/kernel/cpu/cpuid_parser.c b/arch/x86/kernel/cpu/cpuid= _parser.c index 3942ea2526f2..f3dffdd43779 100644 --- a/arch/x86/kernel/cpu/cpuid_parser.c +++ b/arch/x86/kernel/cpu/cpuid_parser.c @@ -31,6 +31,41 @@ static void cpuid_read_generic(const struct cpuid_parse_= entry *e, struct cpuid_r cpuid_read_subleaf(e->leaf, e->subleaf + i, output->regs); } =20 +static void cpuid_read_0x2(const struct cpuid_parse_entry *e, struct cpuid= _read_output *output) +{ + union leaf_0x2_regs *regs =3D (union leaf_0x2_regs *)output->regs; + struct leaf_0x2_0 *l =3D (struct leaf_0x2_0 *)output->regs; + int invalid_regs =3D 0; + + /* + * All Intel CPUs must report an iteration count of 1. For broken hardwa= re, + * keep the leaf marked as invalid at the CPUID table. + */ + cpuid_read_subleaf(e->leaf, e->subleaf, l); + if (l->iteration_count !=3D 0x01) + return; + + /* + * The most significant bit (MSB) of each CPUID(0x2) register must be cle= ar. + * If a register is malformed, replace its 1-byte descriptors with NULL. + */ + for (int i =3D 0; i < 4; i++) { + if (regs->reg[i].invalid) { + regs->regv[i] =3D 0; + invalid_regs++; + } + } + + /* + * If all of the CPUID(0x2) output registers were malformed, keep the leaf + * marked as invalid at the CPUID table. + */ + if (invalid_regs =3D=3D 4) + return; + + output->info->nr_entries =3D 1; +} + static void cpuid_read_0x80000000(const struct cpuid_parse_entry *e, struc= t cpuid_read_output *output) { struct leaf_0x80000000_0 *l =3D (struct leaf_0x80000000_0 *)output->regs; diff --git a/arch/x86/kernel/cpu/cpuid_parser.h b/arch/x86/kernel/cpu/cpuid= _parser.h index 1be5c323d5eb..0e3ac9a7700d 100644 --- a/arch/x86/kernel/cpu/cpuid_parser.h +++ b/arch/x86/kernel/cpu/cpuid_parser.h @@ -127,6 +127,7 @@ struct cpuid_parse_entry { */ #define CPUID_COMMON_PARSE_ENTRIES \ /* Leaf Subleaf Reader function */ \ + CPUID_PARSE_ENTRY(0x2, 0, 0x2), \ CPUID_PARSE_ENTRY(0x80000000, 0, 0x80000000), \ =20 /* @@ -160,5 +161,6 @@ struct cpuid_vendor_entry { =20 #define CPUID_VENDOR_ENTRIES \ /* Leaf Vendor list */ \ + CPUID_VENDOR_ENTRY(0x2, X86_VENDOR_INTEL, X86_VENDOR_CENTAUR, X86_VENDOR= _ZHAOXIN),\ =20 #endif /* _ARCH_X86_CPUID_PARSER_H */ --=20 2.50.1 From nobody Sat Oct 4 14:35:16 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 612422E54D9 for ; Fri, 15 Aug 2025 07:05:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755241561; cv=none; b=n6IRUJ24Xp3BKs2DXkrkVIBoOq+JIYN0cJ+DMCMtM+FHoyUQqdEPPjGGH3NvXCyVc/8v6X3Ao24ANyuNo19OUCWVWotcJpazIl3GJVRRw83+RrMRyvgIBOWEYEXVxOyOavQnLlNcsuSCzneoEMQcuFe4/MgTdkvBc8B5LvQY57w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755241561; c=relaxed/simple; bh=3sQ9xVRZdQttfg4JY5cFzs7tV82zFAHsRAFdqgF+bzE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=s7dpFz7W1HVvXW6mVmdJKSJAKCZBNUpo41SDUbxnjFDL49LuY+X97RPqVfyQWrJjCoOeDIrZqUaSZ6hHLXiTSWoNgDeXsfTrq8yAag/gy/8adDIvK+EqKsqvCHOgrE5HIjcXl+v1m+3MHOb5c5X5OIT9SrF4ORe7EMwzcaSu/dM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=aySKjT47; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=EXNy8kTb; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="aySKjT47"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="EXNy8kTb" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1755241556; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=7ArmXJNOuP+8K8NlkOZ1FWJcqOliXbq1/hLPTGJXSCU=; b=aySKjT47QGllfHd2NvpsBTgNLhAz1A9Z94BYoA8HBeUdT+9I3SfBWu5AXja4X0RsUZL1Zc vfOPoQPTHR617k+XWtg02p3/ISWreBvO0VN/1hcCTju+UtxAUAPfDl9ItUDjuWK7HhGKGt sdQWL+C6UBGy+06MqBx49JKusO2FwE0C9goREpik/AiGIROoxaeqM44+zh9nFgU48APhhq kPPiVDCkZZ8jUSeh1AtEYFoqefIz6RHuIoCfs1u/UgoIN6WcpzLTYJp1HnlOT5yT7jL5h5 PZlWItB8NT1xNIvsGmajmc6pRPT0omKWDvA4keB2jJxDTWMJvnQvBg+iFudevQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1755241556; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=7ArmXJNOuP+8K8NlkOZ1FWJcqOliXbq1/hLPTGJXSCU=; b=EXNy8kTbLU+PcyemRiVLHa62yRvd2wH+C5NIcGLM//J4jb8Lsh1ZXElyXUrNV29GUf3fTx ggDAeIUpJW+8g/Aw== To: Borislav Petkov , Ingo Molnar , Dave Hansen Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , David Woodhouse , Sean Christopherson , Peter Zijlstra , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v4 17/34] x86/cpuid: Warn once on invalid CPUID(0x2) iteration count Date: Fri, 15 Aug 2025 09:02:10 +0200 Message-ID: <20250815070227.19981-18-darwi@linutronix.de> In-Reply-To: <20250815070227.19981-1-darwi@linutronix.de> References: <20250815070227.19981-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The CPUID(0x2) output includes a "query count" byte. That byte was supposed to specify the number of repeated CPUID(0x2) subleaf 0 queries needed to extract all of the CPU's cache and TLB descriptors. Per current Intel manuals, all CPUs supporting this leaf "will always" return an iteration count of 1. Since the CPUID parser ignores any CPUID(0x2) output with an invalid iteration count, lightly warn once about this in the kernel log. Do not emit a warning if any of the CPUID(0x2) output registers EAX->EDX, or even all of them, are invalid; i.e., their most significant bit is set. Such a case is both architecturally defined and legitimate. References: b5969494c8d8 ("x86/cpu: Remove CPUID leaf 0x2 parsing loop") Suggested-by: Ingo Molnar Signed-off-by: Ahmed S. Darwish Link: https://lore.kernel.org/lkml/aBnmy_Bmf-H0wxqz@gmail.com --- arch/x86/kernel/cpu/cpuid_parser.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/x86/kernel/cpu/cpuid_parser.c b/arch/x86/kernel/cpu/cpuid= _parser.c index f3dffdd43779..c340ad6eca3d 100644 --- a/arch/x86/kernel/cpu/cpuid_parser.c +++ b/arch/x86/kernel/cpu/cpuid_parser.c @@ -3,6 +3,8 @@ * Centralized CPUID parser (for populating the system's CPUID tables.) */ =20 +#define pr_fmt(fmt) "x86/cpuid: " fmt + #include #include =20 @@ -42,8 +44,11 @@ static void cpuid_read_0x2(const struct cpuid_parse_entr= y *e, struct cpuid_read_ * keep the leaf marked as invalid at the CPUID table. */ cpuid_read_subleaf(e->leaf, e->subleaf, l); - if (l->iteration_count !=3D 0x01) + if (l->iteration_count !=3D 0x01) { + pr_warn_once("Ignoring CPUID(0x2) due to invalid iteration count =3D %d", + l->iteration_count); return; + } =20 /* * The most significant bit (MSB) of each CPUID(0x2) register must be cle= ar. --=20 2.50.1 From nobody Sat Oct 4 14:35:16 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 64B8C29A303 for ; Fri, 15 Aug 2025 07:06:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755241562; cv=none; b=Qr2/xeUUdvBwonHpTzDiHXEQwIi+0NCfru2cAGJqgTBGYVYyxdK7Ol3m1saOx8xcoMhD1FreeChQAHQG1QGyp+S2QG53byBM3fgDtO/RhxdTqsKyzCQjx3KmswZ4UWr8lubBSyNi9IFedI+iIQKpK0OeAVZlNaORk3vS9NSC3fA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755241562; c=relaxed/simple; bh=0CZoe1jqaOgC4GCxjGCKMxxpTSYNuXAPnqxxDkDU2wA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=GqL6prpvU79rRayESA6Kwva1jq9CZhmrgLhpfPK4y5oYZIqdJD5ZvJrvep36wfaR4hgGrmHyqwdVad6QFoviOFdXHxY5B8bzGZFJVS5WROr/N2EhfHfoynLqMDvev5r/N1nYK0Mpc4U2DLY8hHtlkNSJ5Ehz4fFTgeZb7nhrF4g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=OGKMAvtA; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=EwZ3bJrY; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="OGKMAvtA"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="EwZ3bJrY" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1755241559; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=vUh9DNE9z8dPvy+AypGRO/TNpdxYUzBpKnMNKbc3pcE=; b=OGKMAvtAZqNWkHrYdsEBUKkIcNP0gwEsKdIs3M9AV6LmFuP6zFvl/RwVPl5iXZA0IwUjzs oX9EQZVqXvALMlDdSQy+ZiBX/0YQYXyeqYCJkFoS2k+0beMnfIz8TLaT5tUbtqqIKnDNQD dhoFeMVV2MNTCnbDJBXRPjzTF+pD7mZJUgzFbYzjrwYxQ69+jXNuVFsNYSHeKX1y0RNmwz qKz7hzBO4yHFN/e6AMXVgc4YIHo+1teQHKz5y/6EHjSnGZYArhlE25R75hxZjkwJtT8GBR kQ3twT3wf2dw2ZKFghtX1jqPZUpSmCBx75GBb4vpAWHlCQio+zZbGORq0AdmVw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1755241559; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=vUh9DNE9z8dPvy+AypGRO/TNpdxYUzBpKnMNKbc3pcE=; b=EwZ3bJrYNpN0PQ1OZecEz94WGGnRLYqNJmy/hurE7hrcuao7dQ349k19kjFdOqLBaJlhrr EdSrWhp/oIS7ToBA== To: Borislav Petkov , Ingo Molnar , Dave Hansen Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , David Woodhouse , Sean Christopherson , Peter Zijlstra , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v4 18/34] x86/cpuid: Introduce parsed CPUID(0x2) API Date: Fri, 15 Aug 2025 09:02:11 +0200 Message-ID: <20250815070227.19981-19-darwi@linutronix.de> In-Reply-To: <20250815070227.19981-1-darwi@linutronix.de> References: <20250815070227.19981-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a new iterator macro, for_each_parsed_cpuid_0x2_desc(), for retrieving parsed CPUID(0x2) entries as 1-byte descriptors. Unlike the existing for_each_cpuid_0x2_desc() macro, which operates on directly retrieved CPUID data, the new one takes its input from the centralized CPUID parser. That is, it is expected to be used as: const struct leaf_0x2_table *desc; const struct cpuid_regs *regs; u8 *ptr; regs =3D cpuid_leaf_regs(c, 0x2); // Parsed CPUID access for_each_parsed_cpuid_0x2_desc(regs, ptr, desc) { ... } which should replace the older method: const struct leaf_0x2_table *desc; union leaf_0x2_regs regs; u8 *ptr; cpuid_leaf_0x2(®s); // Direct CPUID access for_each_leaf_0x2_desc(regs, ptr, desc) { ... } In the new macro, assert that the passed 'regs' is the same size as a 'union leaf_0x2_regs'. This is necessary since the macro internally casts 'regs' to that union in order to iterate over the CPUID(0x2) output as a 1-byte array. A size equivalence assert is used, instead of a typeof() check, to give callers the freedom to either pass a 'struct cpuid_regs' pointer or a 'struct leaf_0x2_0' pointer, both as returned by the parsed CPUID API at . That size comparison matches what other kernel CPUID APIs do; e.g. cpuid_read() and cpuid_read_subleaf() at . Note, put the size equivalence check inside a GNU statement expression, ({..}), so that it can be placed inside the macro's loop initialization. Signed-off-by: Ahmed S. Darwish --- arch/x86/include/asm/cpuid/api.h | 43 ++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/arch/x86/include/asm/cpuid/api.h b/arch/x86/include/asm/cpuid/= api.h index b5a6e40419b7..b125e492d239 100644 --- a/arch/x86/include/asm/cpuid/api.h +++ b/arch/x86/include/asm/cpuid/api.h @@ -545,6 +545,49 @@ static inline bool cpuid_amd_hygon_has_l3_cache(void) __cpuid_leaves_subleaf_info(&(_cpuinfo)->cpuid.leaves, _leaf, 0).nr_entri= es; \ }) =20 +/* + * Convenience leaf-specific functions (using parsed CPUID data): + */ + +/* + * CPUID(0x2) + */ + +/** + * for_each_parsed_cpuid_0x2_desc() - Iterator for parsed CPUID(0x2) descr= iptors + * @_regs: Leaf 0x2 register output, as returned by cpuid_leaf_regs() + * @_ptr: u8 pointer, for macro internal use only + * @_desc: Pointer to parsed descriptor information at each iteration + * + * Loop over the 1-byte descriptors in the passed CPUID(0x2) output regist= ers + * @_regs. Provide the parsed information for each descriptor through @_d= esc. + * + * To handle cache-specific descriptors, switch on @_desc->c_type. For TLB + * descriptors, switch on @_desc->t_type. + * + * Example usage for cache descriptors:: + * + * const struct leaf_0x2_table *desc; + * struct cpuid_regs *regs; + * u8 *ptr; + * + * regs =3D cpuid_leaf_regs(c, 0x2); + * if (!regs) { + * // Handle error + * } + * + * for_each_parsed_cpuid_0x2_desc(regs, ptr, desc) { + * switch (desc->c_type) { + * ... + * } + * } + */ +#define for_each_parsed_cpuid_0x2_desc(_regs, _ptr, _desc) \ + for (({ static_assert(sizeof(*_regs) =3D=3D sizeof(union leaf_0x2_regs));= }), \ + _ptr =3D &((union leaf_0x2_regs *)(_regs))->desc[1]; \ + _ptr < &((union leaf_0x2_regs *)(_regs))->desc[16] && (_desc =3D &cp= uid_0x2_table[*_ptr]);\ + _ptr++) + /* * CPUID parser exported APIs: */ --=20 2.50.1 From nobody Sat Oct 4 14:35:16 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 49D182E7F22 for ; Fri, 15 Aug 2025 07:06:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755241565; cv=none; b=ttRZWz3943qu1C5dvgDdiLaAbkAFVr3jhqDtYyURQw0Cr6MAaZjgSeg2YQh41AfCZjTyC7DHGU2Adau01oHple5DocIIH1emaLMUYQZxOlqiALXuMhhsQ1yFrqDergjk1auPcq1UchXRQbTN3q7bH2pS90vJFLOd6c7JdzWBe8s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755241565; c=relaxed/simple; bh=CPwt7tAmjsTsX1vXCApyLVizG83Rn5+DAyoFNbGuJjo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=m+MFRcjqf5KzXjTLrZHmtCLSgDR2Da+flEWcIeoaXlmFga8y7Zpsd7ejPWRSGctYxgmBFBL7adYJSXDehj2NdRLK+QhqeYQnYJCNYVqWKw2yYVJUvB9Fd+NAfDcXC1QHqZduJ9PjypxuMpPvJukM6IpsK417YOD8HDQiD2+LMOY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=OgBzUVga; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=2stfjP2H; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="OgBzUVga"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="2stfjP2H" From: "Ahmed S. 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Peter Anvin" , David Woodhouse , Sean Christopherson , Peter Zijlstra , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v4 19/34] x86/cpu: Use parsed CPUID(0x2) Date: Fri, 15 Aug 2025 09:02:12 +0200 Message-ID: <20250815070227.19981-20-darwi@linutronix.de> In-Reply-To: <20250815070227.19981-1-darwi@linutronix.de> References: <20250815070227.19981-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Use parsed CPUID(0x2) access instead of direct CPUID queries. Remove the max standard CPUID level check since the NULL check of cpuid_leaf_regs()'s result is equivalent. Signed-off-by: Ahmed S. Darwish --- arch/x86/kernel/cpu/intel.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index 076eaa41b8c8..5eab9135b144 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -710,14 +710,14 @@ static void intel_tlb_lookup(const struct leaf_0x2_ta= ble *desc) static void intel_detect_tlb(struct cpuinfo_x86 *c) { const struct leaf_0x2_table *desc; - union leaf_0x2_regs regs; + struct cpuid_regs *regs; u8 *ptr; =20 - if (c->cpuid_level < 2) + regs =3D cpuid_leaf_regs(c, 0x2); + if (!regs) return; =20 - cpuid_leaf_0x2(®s); - for_each_cpuid_0x2_desc(regs, ptr, desc) + for_each_parsed_cpuid_0x2_desc(regs, ptr, desc) intel_tlb_lookup(desc); } =20 --=20 2.50.1 From nobody Sat Oct 4 14:35:16 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F12A12E889D for ; Fri, 15 Aug 2025 07:06:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755241569; cv=none; b=CGzq0qlXU9x42F6KLp9lI1kHQIGje7SRABfeyOmG3Ywjq8CfKzU3Zsu9+W6CS1zhtJPGQEbzEKgm8PcVYpr/o+m8f0n0KzaPsHUTONypSxHDASu5c37OEyYCUL1CpEHCRxa21sOD97G+qYd12sb+zXC6c5Iao5gMHtU9WnY4zrA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755241569; c=relaxed/simple; bh=3JgGac+wLi2t8hgJ5cs7uHeU+da7Ttsi4FfXEQS7jEY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=NCOEonZKYfWPnIGJ8OTLnoPouiHCi7bIEgYbEYWkflmaY69CAueVgJNtBDIICZ3yPXRZ++YIWX/Bz8uCfujZEGafkOJTgVBnIzmLTiLN9ViJWadL081N41g/vIzObmO/oIz6pig8NVM8nqfauQr9qbfp7R6nop9Spc035ZYnW9Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=wYD+Hi3/; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=cg4GvD4D; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="wYD+Hi3/"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="cg4GvD4D" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1755241565; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=MRQM0gtExWMEhiBSKGLu87ejkMzs1S3UQSqE31gfaWw=; b=wYD+Hi3/DjUEie8GboVIY0w45CtbfO2Ff/Zw4/Pq9M46fNjMOHReqha6nKJbE7M1ZLL8oG +PiZFNNPJRuEgdrwaUthQq6vty1jTZjThkNdqVdVCWjw+S7tgGC212dh/3GxD1uhQEKj9O J4w/AQnoAzYyIdn6Xu4fxOM3lTzB0TQpdGE4O/4vWny1VeM4Dej5oJTdX3YbNQjdAd33nP 7/29NjuDXOS/1oYsofYhe4ySYheWHNUTveBLXMlbPR0HgDdS4JwHSK+qs/f/oQp0NceeWy dH20rDU3QBfq6qOv2FRx3QayVcF6i8x3NbnogOntdFo6vchbOtk0ds72RsIzNw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1755241565; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=MRQM0gtExWMEhiBSKGLu87ejkMzs1S3UQSqE31gfaWw=; b=cg4GvD4Doqt7AYXnLzbVK/KdQfyDD8GfwdlmNOopfdiG8JMfjxerF3c5d7edCmQsz8+FfD ujzIFddsHRgHRLDA== To: Borislav Petkov , Ingo Molnar , Dave Hansen Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , David Woodhouse , Sean Christopherson , Peter Zijlstra , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v4 20/34] x86/cacheinfo: Use parsed CPUID(0x2) Date: Fri, 15 Aug 2025 09:02:13 +0200 Message-ID: <20250815070227.19981-21-darwi@linutronix.de> In-Reply-To: <20250815070227.19981-1-darwi@linutronix.de> References: <20250815070227.19981-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Use parsed CPUID(0x2) access instead of direct CPUID queries. Remove the max standard CPUID level check since the NULL check of cpuid_leaf_regs()'s result is equivalent. Signed-off-by: Ahmed S. Darwish --- arch/x86/kernel/cpu/cacheinfo.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinf= o.c index adfa7e8bb865..39cd6db4f702 100644 --- a/arch/x86/kernel/cpu/cacheinfo.c +++ b/arch/x86/kernel/cpu/cacheinfo.c @@ -382,14 +382,14 @@ static void intel_cacheinfo_0x2(struct cpuinfo_x86 *c) { unsigned int l1i =3D 0, l1d =3D 0, l2 =3D 0, l3 =3D 0; const struct leaf_0x2_table *desc; - union leaf_0x2_regs regs; + struct cpuid_regs *regs; u8 *ptr; =20 - if (c->cpuid_level < 2) + regs =3D cpuid_leaf_regs(c, 0x2); + if (!regs) return; =20 - cpuid_leaf_0x2(®s); - for_each_cpuid_0x2_desc(regs, ptr, desc) { + for_each_parsed_cpuid_0x2_desc(regs, ptr, desc) { switch (desc->c_type) { case CACHE_L1_INST: l1i +=3D desc->c_size; break; case CACHE_L1_DATA: l1d +=3D desc->c_size; break; --=20 2.50.1 From nobody Sat Oct 4 14:35:16 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EAE3E2D3726 for ; Fri, 15 Aug 2025 07:06:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755241572; cv=none; b=pNTb7BZFuciwGST3oh7vwIyE5EvXdUNPkPhcV4FWrIk69orzh2zEVWxUAnbc84HVjhUVkBBtttQCvYR3l9IOP0VzsIwGBzWL2+FcWC88YOxFELWUrTaqP5EWNRYB9//qTT3nwH3hQJnuNDJyz7d0qBlX1Lmx6KZTyT19JCGp8Rs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755241572; c=relaxed/simple; bh=WnfbRPGtzLUFs3KRv7m7E97+zrD4D9mfA4GQ+6CbflM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=qtMfSYZqKJH8CheGXjPw/7yIbrxMe0Lb8h2nBVcDFwqIvjJZRpR7RTpHFQV91McJu1mQXcJypzui+kKHo0TGiKdFM5zzBdpYXXw2Ai8BM0I7vmHS9YwvfxoiSfJ7DsUku9i9Oi6E4YMCccavamR9BNPWNEWaAcLdKhtIMjpb4JE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=eKZ3G/V/; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=XC/1PxJi; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="eKZ3G/V/"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="XC/1PxJi" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1755241569; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ckafa6qGRrSy2xIMkp0+kG6pmMOuCSppcj32NSzi0cw=; b=eKZ3G/V/vQbaPb4PtmAdXlt0qWbc4jmeg17oSfgXrdDVpN2FEwFrTXGGjSFb56cnU1nqTs hREy7kfv5y7I7lVj4+JrnRDAHBioJGe/UYjCo2/YfJO73oxO1qdU/6J8SfgCM4iJKjakWx IDPICgoGcwvKBh1ymUhkl2PGVcO4ErKVClirVvzcQIIj8FX7dmINh72AegQNq3ws0QuU0r KyggVP1e4Fc9VCFUFDFvyY2qLxdgQuXYx5TvnhXSm3Ubwy8t4a6ZN6/jAoRSNEeHJfU/oO qnZ1fRClN15lcN8aXdlzpWL/0sm9S1PvSU1gED79SQG/yyVDhLo6eako8RVEtg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1755241569; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ckafa6qGRrSy2xIMkp0+kG6pmMOuCSppcj32NSzi0cw=; b=XC/1PxJi6pEk24M49ucDRDiYuU+4sgYQYD3SqfUjgWTgCOUt+Vk8f2gd2lU0K/oGlmqZnR Q7ufXGCVsjecwjCg== To: Borislav Petkov , Ingo Molnar , Dave Hansen Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , David Woodhouse , Sean Christopherson , Peter Zijlstra , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v4 21/34] x86/cpuid: Remove direct CPUID(0x2) query API Date: Fri, 15 Aug 2025 09:02:14 +0200 Message-ID: <20250815070227.19981-22-darwi@linutronix.de> In-Reply-To: <20250815070227.19981-1-darwi@linutronix.de> References: <20250815070227.19981-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" All call sites at x86/cpu and x86/cacheinfo has been switched from direct CPUID(0x2) access to parsed CPUID access. Remove the direct CPUID(0x2) query APIs at : cpuid_leaf_0x2() for_each_cpuid_0x2_desc() Rename the iterator macro: for_each_parsed_cpuid_0x2_desc() back to: for_each_cpuid_0x2_desc() since the "for_each_parsed_.." name and was just chosen to accommodate the transition from direct CPUID(0x2) access to parsed access. Signed-off-by: Ahmed S. Darwish --- arch/x86/include/asm/cpuid/api.h | 75 ++------------------------------ arch/x86/kernel/cpu/cacheinfo.c | 2 +- arch/x86/kernel/cpu/intel.c | 2 +- 3 files changed, 5 insertions(+), 74 deletions(-) diff --git a/arch/x86/include/asm/cpuid/api.h b/arch/x86/include/asm/cpuid/= api.h index b125e492d239..146498d5dbfa 100644 --- a/arch/x86/include/asm/cpuid/api.h +++ b/arch/x86/include/asm/cpuid/api.h @@ -213,75 +213,6 @@ static inline u32 cpuid_base_hypervisor(const char *si= g, u32 leaves) return 0; } =20 -/* - * CPUID(0x2) parsing: - */ - -/** - * cpuid_leaf_0x2() - Return sanitized CPUID(0x2) register output - * @regs: Output parameter - * - * Query CPUID(0x2) and store its output in @regs. Force set any - * invalid 1-byte descriptor returned by the hardware to zero (the NULL - * cache/TLB descriptor) before returning it to the caller. - * - * Use for_each_cpuid_0x2_desc() to iterate over the register output in - * parsed form. - */ -static inline void cpuid_leaf_0x2(union leaf_0x2_regs *regs) -{ - cpuid_read(0x2, regs); - - /* - * All Intel CPUs must report an iteration count of 1. In case - * of bogus hardware, treat all returned descriptors as NULL. - */ - if (regs->desc[0] !=3D 0x01) { - for (int i =3D 0; i < 4; i++) - regs->regv[i] =3D 0; - return; - } - - /* - * The most significant bit (MSB) of each register must be clear. - * If a register is invalid, replace its descriptors with NULL. - */ - for (int i =3D 0; i < 4; i++) { - if (regs->reg[i].invalid) - regs->regv[i] =3D 0; - } -} - -/** - * for_each_cpuid_0x2_desc() - Iterator for parsed CPUID(0x2) descriptors - * @_regs: CPUID(0x2) register output, as returned by cpuid_leaf_0x2() - * @_ptr: u8 pointer, for macro internal use only - * @_desc: Pointer to the parsed CPUID(0x2) descriptor at each iteration - * - * Loop over the 1-byte descriptors in the passed CPUID(0x2) output regist= ers - * @_regs. Provide the parsed information for each descriptor through @_d= esc. - * - * To handle cache-specific descriptors, switch on @_desc->c_type. For TLB - * descriptors, switch on @_desc->t_type. - * - * Example usage for cache descriptors:: - * - * const struct leaf_0x2_table *desc; - * union leaf_0x2_regs regs; - * u8 *ptr; - * - * cpuid_leaf_0x2(®s); - * for_each_cpuid_0x2_desc(regs, ptr, desc) { - * switch (desc->c_type) { - * ... - * } - * } - */ -#define for_each_cpuid_0x2_desc(_regs, _ptr, _desc) \ - for (_ptr =3D &(_regs).desc[1]; \ - _ptr < &(_regs).desc[16] && (_desc =3D &cpuid_0x2_table[*_ptr]); \ - _ptr++) - /* * CPUID(0x80000006) parsing: */ @@ -554,7 +485,7 @@ static inline bool cpuid_amd_hygon_has_l3_cache(void) */ =20 /** - * for_each_parsed_cpuid_0x2_desc() - Iterator for parsed CPUID(0x2) descr= iptors + * for_each_cpuid_0x2_desc() - Iterator for parsed CPUID(0x2) descriptors * @_regs: Leaf 0x2 register output, as returned by cpuid_leaf_regs() * @_ptr: u8 pointer, for macro internal use only * @_desc: Pointer to parsed descriptor information at each iteration @@ -576,13 +507,13 @@ static inline bool cpuid_amd_hygon_has_l3_cache(void) * // Handle error * } * - * for_each_parsed_cpuid_0x2_desc(regs, ptr, desc) { + * for_each_cpuid_0x2_desc(regs, ptr, desc) { * switch (desc->c_type) { * ... * } * } */ -#define for_each_parsed_cpuid_0x2_desc(_regs, _ptr, _desc) \ +#define for_each_cpuid_0x2_desc(_regs, _ptr, _desc) \ for (({ static_assert(sizeof(*_regs) =3D=3D sizeof(union leaf_0x2_regs));= }), \ _ptr =3D &((union leaf_0x2_regs *)(_regs))->desc[1]; \ _ptr < &((union leaf_0x2_regs *)(_regs))->desc[16] && (_desc =3D &cp= uid_0x2_table[*_ptr]);\ diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinf= o.c index 39cd6db4f702..f837ccdec116 100644 --- a/arch/x86/kernel/cpu/cacheinfo.c +++ b/arch/x86/kernel/cpu/cacheinfo.c @@ -389,7 +389,7 @@ static void intel_cacheinfo_0x2(struct cpuinfo_x86 *c) if (!regs) return; =20 - for_each_parsed_cpuid_0x2_desc(regs, ptr, desc) { + for_each_cpuid_0x2_desc(regs, ptr, desc) { switch (desc->c_type) { case CACHE_L1_INST: l1i +=3D desc->c_size; break; case CACHE_L1_DATA: l1d +=3D desc->c_size; break; diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index 5eab9135b144..06c249110c8b 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -717,7 +717,7 @@ static void intel_detect_tlb(struct cpuinfo_x86 *c) if (!regs) return; =20 - for_each_parsed_cpuid_0x2_desc(regs, ptr, desc) + for_each_cpuid_0x2_desc(regs, ptr, desc) intel_tlb_lookup(desc); } =20 --=20 2.50.1 From nobody Sat Oct 4 14:35:16 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D3A732EAB65 for ; Fri, 15 Aug 2025 07:06:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755241575; cv=none; b=uczK/jzTMCQRaUDWkjLq2whOexJRM3tASluCaUjQQKqLIqOtnOiBN/2rG62J7Xlhi3ZWzuiZL6iZFw2Qq2DKnXMQ+bYDdyEbiaqxBi96mmkuaOxmXKJ7QWUEXe9Z14T9wJ6jSXBD5AWsG3es1DqZkuBJ6I3LJOPouxt3ehb5/Oc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755241575; c=relaxed/simple; bh=HTpRnqlKso/FXDrHqiIJ8nvmJi4tgHXFOk46HUFzkTE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=GWLkJrhDahA1nwK7zSVDs626AGSmBDhfY7o1ceGH95hwVOEuCcap1LYDmEbmei6V1ed8PlGY8fkQqc3691ttX2qFlQvG2ddXHQWS5zcokrat+WfxB8rdvCOzcea9Y0S/JDsV3vf/kY6vlcIfZ9ww6OndfW94Pi0xue04M14Aq8Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=SNRFyEu6; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=6vTVAVmw; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="SNRFyEu6"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="6vTVAVmw" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1755241572; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=a5stZDyoyjR3gb+Wxf514suR2rNmBwiWAX20aFG4VoA=; b=SNRFyEu6Trq0tL/lIEuYKqgtZe5NmbbVTah+qGSYMHv/Fj3/KEMITJdX+mSbBfTGlZwfHl YArFVcKfqHi5cKxMaVr00UeWFOuGaD8zWY+qp19ADtr9NDpgZRCd1DCDgZkQZ+od8MAyxH 078OwWH8jLrEfPTVBUS2mfEbzXcvQ3cF+DyVcGtmbJKdFIzT6p8Wz+ZGFTLaog4L6SeaEa X1+6UHv/vHmMbOxAfeikvCxWGOw3imzXnY4icNDOvG+PcN07qeq686FwzRvM/MbdHEc6+J AMgbnsM21rp4GB9gheJJrUlXlgbdomjgFpRWCcTjHppPwiOL4MPIqwFswYIb2w== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1755241572; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=a5stZDyoyjR3gb+Wxf514suR2rNmBwiWAX20aFG4VoA=; b=6vTVAVmwNnnA2WhhfozmqKT0dG1ubZnQRY8b+cvOMtr1YtR4FNfLyom0GpL5AJrjPzxkUR 49KzTBdKpeMgyYAQ== To: Borislav Petkov , Ingo Molnar , Dave Hansen Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , David Woodhouse , Sean Christopherson , Peter Zijlstra , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v4 22/34] x86/cpuid: Parse 'deterministic cache parameters' CPUID leaves Date: Fri, 15 Aug 2025 09:02:15 +0200 Message-ID: <20250815070227.19981-23-darwi@linutronix.de> In-Reply-To: <20250815070227.19981-1-darwi@linutronix.de> References: <20250815070227.19981-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add CPUID(0x4) and CPUID(0x8000001d) support to the CPUID parser. Query CPUID(0x4) only for Intel, Centaur, and Zhaoxin as these are the only x86 vendors where it is supported. Query CPUID(0x8000001d) only for AMD and Hygon. Define a single output parsing function for both CPUID leaves, as both have the same subleaf cache enumeration logic. Introduce the macro __define_cpuid_read_function() to avoid code duplication between the CPUID parser default read function, cpuid_read_generic(), and the new CPUID(0x4)/CPUID(0x8000001d) parsing logic. Signed-off-by: Ahmed S. Darwish --- arch/x86/include/asm/cpuid/types.h | 2 ++ arch/x86/kernel/cpu/cpuid_parser.c | 37 +++++++++++++++++++++++++----- arch/x86/kernel/cpu/cpuid_parser.h | 4 ++++ 3 files changed, 37 insertions(+), 6 deletions(-) diff --git a/arch/x86/include/asm/cpuid/types.h b/arch/x86/include/asm/cpui= d/types.h index 7bbf0671cb95..89c399629e58 100644 --- a/arch/x86/include/asm/cpuid/types.h +++ b/arch/x86/include/asm/cpuid/types.h @@ -216,7 +216,9 @@ struct cpuid_leaves { CPUID_LEAF(0x0, 0, 1); CPUID_LEAF(0x1, 0, 1); CPUID_LEAF(0x2, 0, 1); + CPUID_LEAF(0x4, 0, 8); CPUID_LEAF(0x80000000, 0, 1); + CPUID_LEAF(0x8000001d, 0, 8); }; =20 /* diff --git a/arch/x86/kernel/cpu/cpuid_parser.c b/arch/x86/kernel/cpu/cpuid= _parser.c index c340ad6eca3d..60da1e452831 100644 --- a/arch/x86/kernel/cpu/cpuid_parser.c +++ b/arch/x86/kernel/cpu/cpuid_parser.c @@ -22,17 +22,36 @@ static const struct cpuid_vendor_entry cpuid_vendor_ent= ries[] =3D { * Leaf read functions: */ =20 -/* - * Default CPUID parser read function +/** + * __define_cpuid_parser_read_function() - Generate a CPUID parser leaf re= ad function + * @suffix: Generated function name suffix (full name becomes: cpuid_read_= @suffix()) + * @_leaf_t: Type to cast the CPUID query output storage pointer + * @_leaf: Name of the CPUID query storage pointer + * @_break_c: Condition to break the CPUID parsing loop, which may referen= ce @_leaf, and + * where @_leaf stores each iteration's CPUID query output. * * Satisfies the requirements stated at 'struct cpuid_parse_entry'->read(). + * Define a CPUID parser read function according to the requirements state= d at + * 'struct cpuid_parse_entry'->read(). */ -static void cpuid_read_generic(const struct cpuid_parse_entry *e, struct c= puid_read_output *output) -{ - for (int i =3D 0; i < e->maxcnt; i++, output->regs++, output->info->nr_en= tries++) - cpuid_read_subleaf(e->leaf, e->subleaf + i, output->regs); +#define __define_cpuid_parser_read_function(suffix, _leaf_t, _leaf, _break= _c) \ +static void \ +cpuid_read_##suffix(const struct cpuid_parse_entry *e, struct cpuid_read_o= utput *output) \ +{ \ + struct _leaf_t *_leaf =3D (struct _leaf_t *)output->regs; \ + \ + for (int i =3D 0; i < e->maxcnt; i++, _leaf++, output->info->nr_entries++= ) { \ + cpuid_read_subleaf(e->leaf, e->subleaf + i, _leaf); \ + if (_break_c) \ + break; \ + } \ } =20 +/* + * Default CPUID parser read function + */ +__define_cpuid_parser_read_function(generic, cpuid_regs, ignored, false); + static void cpuid_read_0x2(const struct cpuid_parse_entry *e, struct cpuid= _read_output *output) { union leaf_0x2_regs *regs =3D (union leaf_0x2_regs *)output->regs; @@ -71,6 +90,12 @@ static void cpuid_read_0x2(const struct cpuid_parse_entr= y *e, struct cpuid_read_ output->info->nr_entries =3D 1; } =20 +/* + * Shared read function for Intel CPUID(0x4) and AMD CPUID(0x8000001d), as= both have + * the same subleaf enumeration logic and registers output format. + */ +__define_cpuid_parser_read_function(deterministic_cache, leaf_0x4_0, l, l-= >cache_type =3D=3D 0); + static void cpuid_read_0x80000000(const struct cpuid_parse_entry *e, struc= t cpuid_read_output *output) { struct leaf_0x80000000_0 *l =3D (struct leaf_0x80000000_0 *)output->regs; diff --git a/arch/x86/kernel/cpu/cpuid_parser.h b/arch/x86/kernel/cpu/cpuid= _parser.h index 0e3ac9a7700d..15ad37b0b3b2 100644 --- a/arch/x86/kernel/cpu/cpuid_parser.h +++ b/arch/x86/kernel/cpu/cpuid_parser.h @@ -128,7 +128,9 @@ struct cpuid_parse_entry { #define CPUID_COMMON_PARSE_ENTRIES \ /* Leaf Subleaf Reader function */ \ CPUID_PARSE_ENTRY(0x2, 0, 0x2), \ + CPUID_PARSE_ENTRY(0x4, 0, deterministic_cache), \ CPUID_PARSE_ENTRY(0x80000000, 0, 0x80000000), \ + CPUID_PARSE_ENTRY(0x8000001d, 0, deterministic_cache), \ =20 /* * CPUID parser tables repository: @@ -162,5 +164,7 @@ struct cpuid_vendor_entry { #define CPUID_VENDOR_ENTRIES \ /* Leaf Vendor list */ \ CPUID_VENDOR_ENTRY(0x2, X86_VENDOR_INTEL, X86_VENDOR_CENTAUR, X86_VENDOR= _ZHAOXIN),\ + CPUID_VENDOR_ENTRY(0x4, X86_VENDOR_INTEL, X86_VENDOR_CENTAUR, X86_VENDOR= _ZHAOXIN),\ + CPUID_VENDOR_ENTRY(0x8000001d, X86_VENDOR_AMD, X86_VENDOR_HYGON), \ =20 #endif /* _ARCH_X86_CPUID_PARSER_H */ --=20 2.50.1 From nobody Sat Oct 4 14:35:16 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 71E672EAB8A for ; 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Peter Anvin" , David Woodhouse , Sean Christopherson , Peter Zijlstra , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v4 23/34] x86/cacheinfo: Pass a 'struct cpuinfo_x86' refrence to CPUID(0x4) code Date: Fri, 15 Aug 2025 09:02:16 +0200 Message-ID: <20250815070227.19981-24-darwi@linutronix.de> In-Reply-To: <20250815070227.19981-1-darwi@linutronix.de> References: <20250815070227.19981-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Prepare the CPUID(0x4) cache topology code for using parsed CPUID APIs instead of invoking direct CPUID queries. Since such an API requires a 'struct cpuinfo_x86' reference, trickle it from the 's populate_cache_leaves() x86 implementation down to fill_cpuid4_info() and its Intel-specific CPUID(0x4) code. No functional change intended. Suggested-by: Ingo Molnar Signed-off-by: Ahmed S. Darwish Link: https://lore.kernel.org/lkml/aBnEBbDATdE2LTGU@gmail.com --- arch/x86/kernel/cpu/cacheinfo.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinf= o.c index f837ccdec116..0ed5dd6d29ef 100644 --- a/arch/x86/kernel/cpu/cacheinfo.c +++ b/arch/x86/kernel/cpu/cacheinfo.c @@ -252,7 +252,7 @@ static int amd_fill_cpuid4_info(int index, struct _cpui= d4_info *id4) return cpuid4_info_fill_done(id4, eax, ebx, ecx); } =20 -static int intel_fill_cpuid4_info(int index, struct _cpuid4_info *id4) +static int intel_fill_cpuid4_info(struct cpuinfo_x86 *unused, int index, s= truct _cpuid4_info *id4) { union _cpuid4_leaf_eax eax; union _cpuid4_leaf_ebx ebx; @@ -264,13 +264,13 @@ static int intel_fill_cpuid4_info(int index, struct _= cpuid4_info *id4) return cpuid4_info_fill_done(id4, eax, ebx, ecx); } =20 -static int fill_cpuid4_info(int index, struct _cpuid4_info *id4) +static int fill_cpuid4_info(struct cpuinfo_x86 *c, int index, struct _cpui= d4_info *id4) { u8 cpu_vendor =3D boot_cpu_data.x86_vendor; =20 return (cpu_vendor =3D=3D X86_VENDOR_AMD || cpu_vendor =3D=3D X86_VENDOR_= HYGON) ? amd_fill_cpuid4_info(index, id4) : - intel_fill_cpuid4_info(index, id4); + intel_fill_cpuid4_info(c, index, id4); } =20 static int find_num_cache_leaves(struct cpuinfo_x86 *c) @@ -434,7 +434,7 @@ static bool intel_cacheinfo_0x4(struct cpuinfo_x86 *c) struct _cpuid4_info id4 =3D {}; int ret; =20 - ret =3D intel_fill_cpuid4_info(i, &id4); + ret =3D intel_fill_cpuid4_info(c, i, &id4); if (ret < 0) continue; =20 @@ -618,13 +618,14 @@ int populate_cache_leaves(unsigned int cpu) { struct cpu_cacheinfo *this_cpu_ci =3D get_cpu_cacheinfo(cpu); struct cacheinfo *ci =3D this_cpu_ci->info_list; + struct cpuinfo_x86 *c =3D &cpu_data(cpu); u8 cpu_vendor =3D boot_cpu_data.x86_vendor; struct amd_northbridge *nb =3D NULL; struct _cpuid4_info id4 =3D {}; int idx, ret; =20 for (idx =3D 0; idx < this_cpu_ci->num_leaves; idx++) { - ret =3D fill_cpuid4_info(idx, &id4); + ret =3D fill_cpuid4_info(c, idx, &id4); if (ret) return ret; =20 --=20 2.50.1 From nobody Sat Oct 4 14:35:16 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2E7F82ECEBD for ; Fri, 15 Aug 2025 07:06:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755241581; cv=none; b=RLzIVmJRgw02a+cMiWFQxX2Au7mTtjihjLlBWVEXt+V/y5MHMz2Xu34AVlAaUTIrx2z5mGfn/EacNwDp3u00t8k7i8TYt5MhWpq3TFn9HI80ieE+xcIw5Q5vYF4EuAo9+l0tmLYPKJvGO3YLfte7ekZex3+7nCORRY8aG9vNC1A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755241581; c=relaxed/simple; bh=1bQLfxXqh1CwSbXgVMwxFWBKJRDveyXkZBq3qbFKTzQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=g39qVESxmt5t8GO71xiQH+TsI6NrifdnRXli687hwmSf327wETlF+LbQaOQA/BpCZrQkCUB7D1V9Zv0grvwvi1yeI0ifR1029j5hVi4uNk+zerK5jTQmxWGG9sEFjjDlUExVXLm8T/LnDKwfka+YeEq8IGj+Wo+Lz+Rl8yuT7CI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=k3a/CrTB; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=aDzYZi+C; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="k3a/CrTB"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="aDzYZi+C" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1755241578; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=6Noe1a4ffiSo4b1qvItz/7pAR08IUgOzYvkqRHJ67WY=; b=k3a/CrTBn9EUD2azdQbHPg8mSERZxNi7ZOB8U/L5f3y1bsWWWGrDccFMynIGU+o1PEhA/b 54txAeMvyH/vKiAsxCzI3aGwxsYyPASn07Iqt6Y1Q1h9eDvmGEouhDnEPikcVk34ZLoImM DH1eDrXwsAl6EFhq6zNYqqbXd/jjIHSuutd+I4N592EkFjBxoOSNGi/691GHsly7RTFpn4 rnG2Jh1xX9laWJUneiTx2VF5lanf6HhPE9ExLVHiP0vrurX9vIAqrHuToDT7o0wY+V9AHZ xKioJ8Z24G7lLP7iyrXsfmXnvyL5y95ezmsvRHIj2yTnLDVZH1hJIIUQLwGGQw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1755241578; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=6Noe1a4ffiSo4b1qvItz/7pAR08IUgOzYvkqRHJ67WY=; b=aDzYZi+ClVBy/8mscwbmxf6coLB8zjFYwnvrGt2j8mKORzYlMbuTBn1thPzPY9lMrgWdvO 8WVzicliv6WbmDAw== To: Borislav Petkov , Ingo Molnar , Dave Hansen Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , David Woodhouse , Sean Christopherson , Peter Zijlstra , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v4 24/34] x86/cacheinfo: Use parsed CPUID(0x4) Date: Fri, 15 Aug 2025 09:02:17 +0200 Message-ID: <20250815070227.19981-25-darwi@linutronix.de> In-Reply-To: <20250815070227.19981-1-darwi@linutronix.de> References: <20250815070227.19981-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Refactor the Intel CPUID(0x4) cacheinfo logic to use parsed CPUID access instead of issuing direct CPUID queries. Use the parsed CPUID access macro: cpuid_subleaf_count(c, 0x4) to determine the number of Intel CPUID(0x4) cache leaves instead of calling find_num_cache_leaves(), which internally issues direct CPUID queries. Since find_num_cache_leaves() is no longer needed for Intel code paths, make it AMD-specific. Rename it to amd_find_num_cache_leaves() and remove its Intel CPUID(0x4) logic. Adjust the AMD paths accordingly. Signed-off-by: Ahmed S. Darwish --- arch/x86/kernel/cpu/cacheinfo.c | 31 ++++++++++++++----------------- 1 file changed, 14 insertions(+), 17 deletions(-) diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinf= o.c index 0ed5dd6d29ef..07f0883f9fbe 100644 --- a/arch/x86/kernel/cpu/cacheinfo.c +++ b/arch/x86/kernel/cpu/cacheinfo.c @@ -252,16 +252,14 @@ static int amd_fill_cpuid4_info(int index, struct _cp= uid4_info *id4) return cpuid4_info_fill_done(id4, eax, ebx, ecx); } =20 -static int intel_fill_cpuid4_info(struct cpuinfo_x86 *unused, int index, s= truct _cpuid4_info *id4) +static int intel_fill_cpuid4_info(struct cpuinfo_x86 *c, int index, struct= _cpuid4_info *id4) { - union _cpuid4_leaf_eax eax; - union _cpuid4_leaf_ebx ebx; - union _cpuid4_leaf_ecx ecx; - u32 ignored; - - cpuid_count(4, index, &eax.full, &ebx.full, &ecx.full, &ignored); + const struct cpuid_regs *regs =3D cpuid_subleaf_index_regs(c, 0x4, index); =20 - return cpuid4_info_fill_done(id4, eax, ebx, ecx); + return cpuid4_info_fill_done(id4, + (union _cpuid4_leaf_eax)(regs->eax), + (union _cpuid4_leaf_ebx)(regs->ebx), + (union _cpuid4_leaf_ecx)(regs->ecx)); } =20 static int fill_cpuid4_info(struct cpuinfo_x86 *c, int index, struct _cpui= d4_info *id4) @@ -273,17 +271,16 @@ static int fill_cpuid4_info(struct cpuinfo_x86 *c, in= t index, struct _cpuid4_inf intel_fill_cpuid4_info(c, index, id4); } =20 -static int find_num_cache_leaves(struct cpuinfo_x86 *c) +static int amd_find_num_cache_leaves(struct cpuinfo_x86 *c) { - unsigned int eax, ebx, ecx, edx, op; union _cpuid4_leaf_eax cache_eax; + unsigned int eax, ebx, ecx, edx; int i =3D -1; =20 - /* Do a CPUID(op) loop to calculate num_cache_leaves */ - op =3D (c->x86_vendor =3D=3D X86_VENDOR_AMD || c->x86_vendor =3D=3D X86_V= ENDOR_HYGON) ? 0x8000001d : 4; + /* Do a CPUID(0x8000001d) loop to calculate num_cache_leaves */ do { ++i; - cpuid_count(op, i, &eax, &ebx, &ecx, &edx); + cpuid_count(0x8000001d, i, &eax, &ebx, &ecx, &edx); cache_eax.full =3D eax; } while (cache_eax.split.type !=3D CTYPE_NULL); return i; @@ -313,7 +310,7 @@ void cacheinfo_amd_init_llc_id(struct cpuinfo_x86 *c, u= 16 die_id) * of threads sharing the L3 cache. */ u32 eax, ebx, ecx, edx, num_sharing_cache =3D 0; - u32 llc_index =3D find_num_cache_leaves(c) - 1; + u32 llc_index =3D amd_find_num_cache_leaves(c) - 1; =20 cpuid_count(0x8000001d, llc_index, &eax, &ebx, &ecx, &edx); if (eax) @@ -344,7 +341,7 @@ void init_amd_cacheinfo(struct cpuinfo_x86 *c) struct cpu_cacheinfo *ci =3D get_cpu_cacheinfo(c->cpu_index); =20 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) - ci->num_leaves =3D find_num_cache_leaves(c); + ci->num_leaves =3D amd_find_num_cache_leaves(c); else if (c->extended_cpuid_level >=3D 0x80000006) ci->num_leaves =3D (cpuid_edx(0x80000006) & 0xf000) ? 4 : 3; } @@ -353,7 +350,7 @@ void init_hygon_cacheinfo(struct cpuinfo_x86 *c) { struct cpu_cacheinfo *ci =3D get_cpu_cacheinfo(c->cpu_index); =20 - ci->num_leaves =3D find_num_cache_leaves(c); + ci->num_leaves =3D amd_find_num_cache_leaves(c); } =20 static void intel_cacheinfo_done(struct cpuinfo_x86 *c, unsigned int l3, @@ -425,7 +422,7 @@ static bool intel_cacheinfo_0x4(struct cpuinfo_x86 *c) * that the number of leaves has been previously initialized. */ if (!ci->num_leaves) - ci->num_leaves =3D find_num_cache_leaves(c); + ci->num_leaves =3D cpuid_subleaf_count(c, 0x4); =20 if (!ci->num_leaves) return false; --=20 2.50.1 From nobody Sat Oct 4 14:35:16 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 73A1A2F066F for ; Fri, 15 Aug 2025 07:06:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755241585; cv=none; b=LgcaWVaDBGOYPnUCd2oOTJVOSR1FmpeDxtjKyUefJ2n1lwAcHmc1EBRftu1ZFW+9n/JCygFX2WjDbtFCw/ABw8vI3YbGRjn0V7JbJieZIAhsAitIx7KFeGNXfXpgMew15OKy+4VBgL2WbKITkDdgMhHSTiHvn0Q+8UGWuJ+Q01o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755241585; c=relaxed/simple; bh=DZaNyXZwF6QJrY7kYXtD41G19i6Aj2kj2FFuvkzGCtQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=EtsY6VRereQf+Dgew2gCyHsrIJIJ4HLkqd7G30YfASMTlqbCX++ie48Q1XAQ2ACowaz+3xjvgL4uBhkxVGGWnhiHwI2Da2RI4q9GMK5a2zK89whKAAC9H8TBT5xtM2ofGWuWnxw9trehNcQ6X80mbN7eXbCwNDg5asF+SVv/DpY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=OBYZpJHU; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=alQYVgNu; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="OBYZpJHU"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="alQYVgNu" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1755241581; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ck8n2iu9wBuqWyXuhhdwn6cyyCj6+svMidjYuMlpF5Y=; b=OBYZpJHUI1FnXJRpJObZorINiU7mIxZC03F+c2C/mx2jYEq14Sb+6M45mWM0yjYpMPzjia 3Us2AfoV8MUteowSD5UBq0Hs7FcHmIh2uRbb4tCL2kkVYmbCVq4X8WLTpVzbqcN4SNxusw oIZhwHDkXJgSgWWvsCLZ6/sZkGgsJ6KefltsC8qkCdd5f8TqEPpriblIMwRD6SLdpGS0K2 SP14q/lHmT2wOkTg8If4dLALL0pEjILOImYDs09vpV1UhsA1y9jFnXdpnEcTgsg1G5KXFU QC5+7m1nuj97wPaldC/lY0mjSESu5jMjGq0GPunmg/KtaXadQIsDOS6R3XeXCA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1755241581; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ck8n2iu9wBuqWyXuhhdwn6cyyCj6+svMidjYuMlpF5Y=; b=alQYVgNuG9QI/SJuWyZ0WPtE3vqeLWWzm+uKce090nXkNmF2J6UAv57CCbnWfSXRdvLPFz ReMGgtJUfFZOlyDw== To: Borislav Petkov , Ingo Molnar , Dave Hansen Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , David Woodhouse , Sean Christopherson , Peter Zijlstra , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v4 25/34] x86/cacheinfo: Use parsed CPUID(0x8000001d) Date: Fri, 15 Aug 2025 09:02:18 +0200 Message-ID: <20250815070227.19981-26-darwi@linutronix.de> In-Reply-To: <20250815070227.19981-1-darwi@linutronix.de> References: <20250815070227.19981-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Refactor the AMD CPUID(0x8000001d) cacheinfo logic to use the parsed CPUID API instead of issuing direct CPUID queries. Beside CPUID data centralization benefits, this allows using the auto-generated 'struct cpuid_0x8000001d_0' data type with its full C99 bitfields instead of doing ugly bitwise operations. Since parsed CPUID access requires a 'struct cpuinfo_x86' reference, trickle it down to relevant functions. Use the parsed CPUID API: cpuid_subleaf_count(c, 0x8000001d) to find the number of cache leaves, thus replacing amd_find_num_cache_leaves() and its direct CPUID queries. Drop that function entirely as it is no longer needed. For now, keep using the 'union _cpuid4_leaf_eax/ebx/ecx' structures as they are required by the AMD CPUID(0x4) emulation code paths. A follow up commit will replace them with equivalents. Note, for below code: cpuid_count(0x8000001d, llc_index, &eax, &ebx, &ecx, &edx); if (eax) num_sharing_cache =3D ((eax >> 14) & 0xfff) + 1; if (num_sharing_cache) { int index_msb =3D get_count_order(num_sharing_cache); ... } it is replaced with: const struct leaf_0x8000001d_0 *leaf =3D cpuid_subleaf_index(c, 0x8000001d, llc_index); if (leaf) { int index_msb =3D get_count_order(l->num_threads_sharing + 1); ... } The "if (leaf)" check is sufficient since the parsed CPUID API returns NULL if the leaf is out of range (> max CPU extended leaf) or if the 'llc_index' is out of range. An out of range LLC index is equivalent to "EAX.cache_type =3D=3D 0" in the original code, making the logic match. Signed-off-by: Ahmed S. Darwish --- arch/x86/kernel/cpu/cacheinfo.c | 47 +++++++++++---------------------- 1 file changed, 16 insertions(+), 31 deletions(-) diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinf= o.c index 07f0883f9fbe..05a3fbd0d849 100644 --- a/arch/x86/kernel/cpu/cacheinfo.c +++ b/arch/x86/kernel/cpu/cacheinfo.c @@ -237,16 +237,19 @@ static int cpuid4_info_fill_done(struct _cpuid4_info = *id4, union _cpuid4_leaf_ea return 0; } =20 -static int amd_fill_cpuid4_info(int index, struct _cpuid4_info *id4) +static int amd_fill_cpuid4_info(struct cpuinfo_x86 *c, int index, struct _= cpuid4_info *id4) { union _cpuid4_leaf_eax eax; union _cpuid4_leaf_ebx ebx; union _cpuid4_leaf_ecx ecx; - u32 ignored; =20 - if (boot_cpu_has(X86_FEATURE_TOPOEXT) || boot_cpu_data.x86_vendor =3D=3D = X86_VENDOR_HYGON) - cpuid_count(0x8000001d, index, &eax.full, &ebx.full, &ecx.full, &ignored= ); - else + if (boot_cpu_has(X86_FEATURE_TOPOEXT) || boot_cpu_data.x86_vendor =3D=3D = X86_VENDOR_HYGON) { + const struct cpuid_regs *regs =3D cpuid_subleaf_index_regs(c, 0x8000001d= , index); + + eax.full =3D regs->eax; + ebx.full =3D regs->ebx; + ecx.full =3D regs->ecx; + } else legacy_amd_cpuid4(index, &eax, &ebx, &ecx); =20 return cpuid4_info_fill_done(id4, eax, ebx, ecx); @@ -267,25 +270,10 @@ static int fill_cpuid4_info(struct cpuinfo_x86 *c, in= t index, struct _cpuid4_inf u8 cpu_vendor =3D boot_cpu_data.x86_vendor; =20 return (cpu_vendor =3D=3D X86_VENDOR_AMD || cpu_vendor =3D=3D X86_VENDOR_= HYGON) ? - amd_fill_cpuid4_info(index, id4) : + amd_fill_cpuid4_info(c, index, id4) : intel_fill_cpuid4_info(c, index, id4); } =20 -static int amd_find_num_cache_leaves(struct cpuinfo_x86 *c) -{ - union _cpuid4_leaf_eax cache_eax; - unsigned int eax, ebx, ecx, edx; - int i =3D -1; - - /* Do a CPUID(0x8000001d) loop to calculate num_cache_leaves */ - do { - ++i; - cpuid_count(0x8000001d, i, &eax, &ebx, &ecx, &edx); - cache_eax.full =3D eax; - } while (cache_eax.split.type !=3D CTYPE_NULL); - return i; -} - /* * AMD/Hygon CPUs may have multiple LLCs if L3 caches exist. */ @@ -309,15 +297,12 @@ void cacheinfo_amd_init_llc_id(struct cpuinfo_x86 *c,= u16 die_id) * Newer families: LLC ID is calculated from the number * of threads sharing the L3 cache. */ - u32 eax, ebx, ecx, edx, num_sharing_cache =3D 0; - u32 llc_index =3D amd_find_num_cache_leaves(c) - 1; - - cpuid_count(0x8000001d, llc_index, &eax, &ebx, &ecx, &edx); - if (eax) - num_sharing_cache =3D ((eax >> 14) & 0xfff) + 1; + u32 llc_index =3D cpuid_subleaf_count(c, 0x8000001d) - 1; + const struct leaf_0x8000001d_0 *leaf =3D + cpuid_subleaf_index(c, 0x8000001d, llc_index); =20 - if (num_sharing_cache) { - int index_msb =3D get_count_order(num_sharing_cache); + if (leaf) { + int index_msb =3D get_count_order(leaf->num_threads_sharing + 1); =20 c->topo.llc_id =3D c->topo.apicid >> index_msb; } @@ -341,7 +326,7 @@ void init_amd_cacheinfo(struct cpuinfo_x86 *c) struct cpu_cacheinfo *ci =3D get_cpu_cacheinfo(c->cpu_index); =20 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) - ci->num_leaves =3D amd_find_num_cache_leaves(c); + ci->num_leaves =3D cpuid_subleaf_count(c, 0x8000001d); else if (c->extended_cpuid_level >=3D 0x80000006) ci->num_leaves =3D (cpuid_edx(0x80000006) & 0xf000) ? 4 : 3; } @@ -350,7 +335,7 @@ void init_hygon_cacheinfo(struct cpuinfo_x86 *c) { struct cpu_cacheinfo *ci =3D get_cpu_cacheinfo(c->cpu_index); =20 - ci->num_leaves =3D amd_find_num_cache_leaves(c); + ci->num_leaves =3D cpuid_subleaf_count(c, 0x8000001d); } =20 static void intel_cacheinfo_done(struct cpuinfo_x86 *c, unsigned int l3, --=20 2.50.1 From nobody Sat Oct 4 14:35:16 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7137E2F0C6E for ; Fri, 15 Aug 2025 07:06:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755241588; cv=none; b=jNJzx92uZKqjaKvFeArwm/aU6xMAf3oTUnm3Al6O1eWoAVMsnuSv4v99hdqzecFyWAadPLwKE/dX+GKiPMm5HqduHkXeHOz+4yuiWlZDYg//aelj04O1+adWur5Oh+Pztk9cltiUbx9A4Frt1KtCQZrvt6kEQI1jbUKoHTlq+44= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755241588; c=relaxed/simple; bh=gyZUptt2IsQjhqA3X3eQEHnOC/AsGsXLCm7Asp25vY4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=USpW4DrZmAf12+ewKaRb05idmG5OUxDHy5d4iTZmLZHdCR3B+6QN/aghTxIi5YdNC3yX7hJ54nt4iPtTZ+sA/Uo4FP36OFWAmguhHxBq7HRwGuVR6HZ372dUw7ZhWhqgrmdDilw+1A7bQ6UPZzTQqROF10QQHqUb1QN6hwxVRPc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=Wp1knzp5; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=6B/beOud; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="Wp1knzp5"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="6B/beOud" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1755241585; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=K/n8oqd98dT0SIV4CQd/E9sGuMKHx/eiHVyLEDEKobY=; b=Wp1knzp5SC3gZMfQZRtzyULH3xatJ1xYUkEoF9PnCIcBELrK/sTisO0CahW9g7M0bgFcyD DUx85f0Rp0MAJzw3AG/MrjFUtX8qbZbAw8AplFDTvxqrs1EHdhvlTFIY9WtZK9tIZg5rJ5 RD2oiJkg9j+aZjXDZj6ihxxCM/JaT6EcxQlI/8wNBwQNf82EDIZfBi29aKuruznJDWSdZf L2xmY3GN6owZ7Z8dTPxH9zYPvMCPJz/hEj/CApUHfYPp39VtWll881cVPM1CckiKo6602Z 8xbKbhu/NRrEIexczUZDXfvmfFSrqZtcHjbsY4wNOr/fA6JHyn2KswhWEND/Vw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1755241585; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=K/n8oqd98dT0SIV4CQd/E9sGuMKHx/eiHVyLEDEKobY=; b=6B/beOudd1S0F/26O24xl9MYB191U+356FZBeuYoOfZ0lXibog7VGZNJtGFf/xhU61Lw+5 MwXSXeLPf6ZFsYAA== To: Borislav Petkov , Ingo Molnar , Dave Hansen Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , David Woodhouse , Sean Christopherson , Peter Zijlstra , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v4 26/34] x86/cpuid: Parse CPUID(0x80000005) and CPUID(0x80000006) Date: Fri, 15 Aug 2025 09:02:19 +0200 Message-ID: <20250815070227.19981-27-darwi@linutronix.de> In-Reply-To: <20250815070227.19981-1-darwi@linutronix.de> References: <20250815070227.19981-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Parse AMD cacheinfo CPUID(0x80000005) and CPUID(0x80000006), if available, using the generic CPUID parser read function cpuid_read_generic(). The x86/cacheinfo AMD CPUID(0x4)-emulation logic will be swithced next to the parsed CPUID table APIs instead of invoking direct CPUID queries. Signed-off-by: Ahmed S. Darwish --- arch/x86/include/asm/cpuid/types.h | 2 ++ arch/x86/kernel/cpu/cpuid_parser.h | 2 ++ 2 files changed, 4 insertions(+) diff --git a/arch/x86/include/asm/cpuid/types.h b/arch/x86/include/asm/cpui= d/types.h index 89c399629e58..63d2569e2821 100644 --- a/arch/x86/include/asm/cpuid/types.h +++ b/arch/x86/include/asm/cpuid/types.h @@ -218,6 +218,8 @@ struct cpuid_leaves { CPUID_LEAF(0x2, 0, 1); CPUID_LEAF(0x4, 0, 8); CPUID_LEAF(0x80000000, 0, 1); + CPUID_LEAF(0x80000005, 0, 1); + CPUID_LEAF(0x80000006, 0, 1); CPUID_LEAF(0x8000001d, 0, 8); }; =20 diff --git a/arch/x86/kernel/cpu/cpuid_parser.h b/arch/x86/kernel/cpu/cpuid= _parser.h index 15ad37b0b3b2..1d0d1a3c2bb8 100644 --- a/arch/x86/kernel/cpu/cpuid_parser.h +++ b/arch/x86/kernel/cpu/cpuid_parser.h @@ -130,6 +130,8 @@ struct cpuid_parse_entry { CPUID_PARSE_ENTRY(0x2, 0, 0x2), \ CPUID_PARSE_ENTRY(0x4, 0, deterministic_cache), \ CPUID_PARSE_ENTRY(0x80000000, 0, 0x80000000), \ + CPUID_PARSE_ENTRY(0x80000005, 0, generic), \ + CPUID_PARSE_ENTRY(0x80000006, 0, generic), \ CPUID_PARSE_ENTRY(0x8000001d, 0, deterministic_cache), \ =20 /* --=20 2.50.1 From nobody Sat Oct 4 14:35:16 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9A58E2D4B47 for ; Fri, 15 Aug 2025 07:06:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755241591; cv=none; b=i2s/1mWh6RmDbCDifAIOsGvGHOTE9mG3+Lal+q4pX8oGiU8wN231U+uvE7c17yrOtTLpqLXutz8S4bUuoVnOarUlR8tczhm/O1Nj9Egqfb6s8qlJuOAXy+5bwPvHWX5YFAl27ZV9iV++SAYGVH+gsA88ejh/m6KKetoLcRGLJlA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755241591; c=relaxed/simple; bh=Pbim+W4KEsGWKZRll0MMC9INMR+z3YujOPQVRqhZjcE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=V18xR35ioJU1T6YT2JvIRfqz9iEB5gmRrAWmEl7KhT+OMg+knbETZ1Ct09trAHq59uaL8Vc5ZyKIu+tHV3fOV+vFmbdWvAX6odBjBBKTi8+OQdWhRTc8HtY8Uq2hSyCYPlVU8HdpxOMuc/QS/d7N7Ib3aC10Dhq0ALIMhO0C4m4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=wk/F43WV; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=FSWAfWTB; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="wk/F43WV"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="FSWAfWTB" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1755241588; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=fKodWqS89bkJbrjSyijjgnP3lshjRZuhJblg8zu3sqw=; b=wk/F43WVYcfBZAwYyhpHd+RHaIzAcvwNnKw3efpPboTs/wdO7JtYeaX7qLiBmqStkETtmF Lcy6lyfo3J6JQuS77LDurT6RrxtfjyZBsRDKTarg9ACqaIBoufGuzufgVaAFIzs04WzDw3 YQ1W0icNfUQ/MxEvYcwZouvhuYAqiufZ3aIQzY9P80PWG5HPm+CP0cs52nxAG4gNlc2jqp l07IvkYGxL081Zw1zXvq0B6UvolmTNJTBjvvLs1gfVE4GpTLJxAVXEknIka2TROJZ40NMi fJ3dC6VE0iHGx/9JHBGL2HhbyJOiasf5dhxHzcio40t8MwIUgMgpAjWrsacsOA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1755241588; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=fKodWqS89bkJbrjSyijjgnP3lshjRZuhJblg8zu3sqw=; b=FSWAfWTBRsZHnDj0Jx8B80PcFQ7Kaunyd92fwBNJ0+9006ZlqrChy8Gp2NCKvzUVJv9Rex qO4VYIOVZLUjuLAg== To: Borislav Petkov , Ingo Molnar , Dave Hansen Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , David Woodhouse , Sean Christopherson , Peter Zijlstra , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v4 27/34] x86/cacheinfo: Use auto-generated data types Date: Fri, 15 Aug 2025 09:02:20 +0200 Message-ID: <20250815070227.19981-28-darwi@linutronix.de> In-Reply-To: <20250815070227.19981-1-darwi@linutronix.de> References: <20250815070227.19981-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" For the AMD CPUID(0x4) emulation logic, use the auto-generated data type: struct leaf_0x4_0 instead of the manually-defined: union _cpuid4_leaf_{eax,ebx,ecx} ones. Remove such unions entirely as they are no longer used. Signed-off-by: Ahmed S. Darwish Link: https://gitlab.com/x86-cpuid.org/x86-cpuid-db --- arch/x86/kernel/cpu/cacheinfo.c | 130 +++++++++++--------------------- 1 file changed, 42 insertions(+), 88 deletions(-) diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinf= o.c index 05a3fbd0d849..f0540cba4bd4 100644 --- a/arch/x86/kernel/cpu/cacheinfo.c +++ b/arch/x86/kernel/cpu/cacheinfo.c @@ -41,39 +41,8 @@ enum _cache_type { CTYPE_UNIFIED =3D 3 }; =20 -union _cpuid4_leaf_eax { - struct { - enum _cache_type type :5; - unsigned int level :3; - unsigned int is_self_initializing :1; - unsigned int is_fully_associative :1; - unsigned int reserved :4; - unsigned int num_threads_sharing :12; - unsigned int num_cores_on_die :6; - } split; - u32 full; -}; - -union _cpuid4_leaf_ebx { - struct { - unsigned int coherency_line_size :12; - unsigned int physical_line_partition :10; - unsigned int ways_of_associativity :10; - } split; - u32 full; -}; - -union _cpuid4_leaf_ecx { - struct { - unsigned int number_of_sets :32; - } split; - u32 full; -}; - struct _cpuid4_info { - union _cpuid4_leaf_eax eax; - union _cpuid4_leaf_ebx ebx; - union _cpuid4_leaf_ecx ecx; + struct leaf_0x4_0 regs; unsigned int id; unsigned long size; }; @@ -148,17 +117,14 @@ static const unsigned short assocs[] =3D { static const unsigned char levels[] =3D { 1, 1, 2, 3 }; static const unsigned char types[] =3D { 1, 2, 3, 3 }; =20 -static void legacy_amd_cpuid4(int index, union _cpuid4_leaf_eax *eax, - union _cpuid4_leaf_ebx *ebx, union _cpuid4_leaf_ecx *ecx) +static void legacy_amd_cpuid4(int index, struct leaf_0x4_0 *regs) { unsigned int dummy, line_size, lines_per_tag, assoc, size_in_kb; union l1_cache l1i, l1d, *l1; union l2_cache l2; union l3_cache l3; =20 - eax->full =3D 0; - ebx->full =3D 0; - ecx->full =3D 0; + *regs =3D (struct leaf_0x4_0){ }; =20 cpuid(0x80000005, &dummy, &dummy, &l1d.val, &l1i.val); cpuid(0x80000006, &dummy, &dummy, &l2.val, &l3.val); @@ -204,65 +170,53 @@ static void legacy_amd_cpuid4(int index, union _cpuid= 4_leaf_eax *eax, return; } =20 - eax->split.is_self_initializing =3D 1; - eax->split.type =3D types[index]; - eax->split.level =3D levels[index]; - eax->split.num_threads_sharing =3D 0; - eax->split.num_cores_on_die =3D topology_num_cores_per_package(); + regs->cache_self_init =3D 1; + regs->cache_type =3D types[index]; + regs->cache_level =3D levels[index]; + regs->num_threads_sharing =3D 0; + regs->num_cores_on_die =3D topology_num_cores_per_package(); =20 if (assoc =3D=3D AMD_CPUID4_FULLY_ASSOCIATIVE) - eax->split.is_fully_associative =3D 1; + regs->fully_associative =3D 1; =20 - ebx->split.coherency_line_size =3D line_size - 1; - ebx->split.ways_of_associativity =3D assoc - 1; - ebx->split.physical_line_partition =3D lines_per_tag - 1; - ecx->split.number_of_sets =3D (size_in_kb * 1024) / line_size / - (ebx->split.ways_of_associativity + 1) - 1; + regs->cache_linesize =3D line_size - 1; + regs->cache_nways =3D assoc - 1; + regs->cache_npartitions =3D lines_per_tag - 1; + regs->cache_nsets =3D (size_in_kb * 1024) / line_size / + (regs->cache_nways + 1) - 1; } =20 -static int cpuid4_info_fill_done(struct _cpuid4_info *id4, union _cpuid4_l= eaf_eax eax, - union _cpuid4_leaf_ebx ebx, union _cpuid4_leaf_ecx ecx) +static int cpuid4_info_fill_done(struct _cpuid4_info *id4, const struct le= af_0x4_0 *regs) { - if (eax.split.type =3D=3D CTYPE_NULL) + if (regs->cache_type =3D=3D CTYPE_NULL) return -EIO; =20 - id4->eax =3D eax; - id4->ebx =3D ebx; - id4->ecx =3D ecx; - id4->size =3D (ecx.split.number_of_sets + 1) * - (ebx.split.coherency_line_size + 1) * - (ebx.split.physical_line_partition + 1) * - (ebx.split.ways_of_associativity + 1); + id4->regs =3D *regs; + id4->size =3D (regs->cache_nsets + 1) * + (regs->cache_linesize + 1) * + (regs->cache_npartitions + 1) * + (regs->cache_nways + 1); =20 return 0; } =20 static int amd_fill_cpuid4_info(struct cpuinfo_x86 *c, int index, struct _= cpuid4_info *id4) { - union _cpuid4_leaf_eax eax; - union _cpuid4_leaf_ebx ebx; - union _cpuid4_leaf_ecx ecx; + struct leaf_0x4_0 regs; =20 - if (boot_cpu_has(X86_FEATURE_TOPOEXT) || boot_cpu_data.x86_vendor =3D=3D = X86_VENDOR_HYGON) { - const struct cpuid_regs *regs =3D cpuid_subleaf_index_regs(c, 0x8000001d= , index); - - eax.full =3D regs->eax; - ebx.full =3D regs->ebx; - ecx.full =3D regs->ecx; - } else - legacy_amd_cpuid4(index, &eax, &ebx, &ecx); + if (boot_cpu_has(X86_FEATURE_TOPOEXT) || boot_cpu_data.x86_vendor =3D=3D = X86_VENDOR_HYGON) + regs =3D *(struct leaf_0x4_0 *)cpuid_subleaf_index(c, 0x8000001d, index); + else + legacy_amd_cpuid4(index, ®s); =20 - return cpuid4_info_fill_done(id4, eax, ebx, ecx); + return cpuid4_info_fill_done(id4, ®s); } =20 static int intel_fill_cpuid4_info(struct cpuinfo_x86 *c, int index, struct= _cpuid4_info *id4) { - const struct cpuid_regs *regs =3D cpuid_subleaf_index_regs(c, 0x4, index); + const struct leaf_0x4_0 *regs =3D cpuid_subleaf_index(c, 0x4, index); =20 - return cpuid4_info_fill_done(id4, - (union _cpuid4_leaf_eax)(regs->eax), - (union _cpuid4_leaf_ebx)(regs->ebx), - (union _cpuid4_leaf_ecx)(regs->ecx)); + return cpuid4_info_fill_done(id4, regs); } =20 static int fill_cpuid4_info(struct cpuinfo_x86 *c, int index, struct _cpui= d4_info *id4) @@ -388,7 +342,7 @@ static unsigned int calc_cache_topo_id(struct cpuinfo_x= 86 *c, const struct _cpui unsigned int num_threads_sharing; int index_msb; =20 - num_threads_sharing =3D 1 + id4->eax.split.num_threads_sharing; + num_threads_sharing =3D 1 + id4->regs.num_threads_sharing; index_msb =3D get_count_order(num_threads_sharing); return c->topo.apicid & ~((1 << index_msb) - 1); } @@ -420,11 +374,11 @@ static bool intel_cacheinfo_0x4(struct cpuinfo_x86 *c) if (ret < 0) continue; =20 - switch (id4.eax.split.level) { + switch (id4.regs.cache_level) { case 1: - if (id4.eax.split.type =3D=3D CTYPE_DATA) + if (id4.regs.cache_type =3D=3D CTYPE_DATA) l1d =3D id4.size / 1024; - else if (id4.eax.split.type =3D=3D CTYPE_INST) + else if (id4.regs.cache_type =3D=3D CTYPE_INST) l1i =3D id4.size / 1024; break; case 2: @@ -485,7 +439,7 @@ static int __cache_amd_cpumap_setup(unsigned int cpu, i= nt index, } else if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { unsigned int apicid, nshared, first, last; =20 - nshared =3D id4->eax.split.num_threads_sharing + 1; + nshared =3D id4->regs.num_threads_sharing + 1; apicid =3D cpu_data(cpu).topo.apicid; first =3D apicid - (apicid % nshared); last =3D first + nshared - 1; @@ -532,7 +486,7 @@ static void __cache_cpumap_setup(unsigned int cpu, int = index, } =20 ci =3D this_cpu_ci->info_list + index; - num_threads_sharing =3D 1 + id4->eax.split.num_threads_sharing; + num_threads_sharing =3D 1 + id4->regs.num_threads_sharing; =20 cpumask_set_cpu(cpu, &ci->shared_cpu_map); if (num_threads_sharing =3D=3D 1) @@ -559,13 +513,13 @@ static void ci_info_init(struct cacheinfo *ci, const = struct _cpuid4_info *id4, { ci->id =3D id4->id; ci->attributes =3D CACHE_ID; - ci->level =3D id4->eax.split.level; - ci->type =3D cache_type_map[id4->eax.split.type]; - ci->coherency_line_size =3D id4->ebx.split.coherency_line_size + 1; - ci->ways_of_associativity =3D id4->ebx.split.ways_of_associativity + 1; + ci->level =3D id4->regs.cache_level; + ci->type =3D cache_type_map[id4->regs.cache_type]; + ci->coherency_line_size =3D id4->regs.cache_linesize + 1; + ci->ways_of_associativity =3D id4->regs.cache_nways + 1; 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arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="TtwoLzcY"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="0Xs6MTqr" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1755241591; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=7MbUpNCHbqyQqmKyKn+T+8R1ajdTUWhmTfxbsEkvhu8=; b=TtwoLzcYQJvA+oEPx1cwzSo5Xb48/ApTnnSV209npeaLG9hgV27Ubul8v0rUWwBUMUNucE 9qhKtbyCQCR98Hrlmk5KqTM0RLndYaepcLvRYVqMq6AiDdcAf/kWd7cLXpc6n3xZpq3co7 NwUYntWOzKgpdNJqNIYeTTYvX+QrsxAf2LNrTQ55v0bNsjYBl4OvFXl0NHHKJRBE68SzOS NexQLegYopd/07VRQmve3XeaLGagvAk0UmQ+OP1XhI7rQZ1P3feMF0ZrVxDb2nJu85i+Ky +7rdZty3iSZlDBDCJxIB0dEw1UhUUQP67mA8VdMDhQzyViHpou14IDYzeHZKFQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1755241591; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=7MbUpNCHbqyQqmKyKn+T+8R1ajdTUWhmTfxbsEkvhu8=; b=0Xs6MTqrp63NLaQ6Z4Jc0GNLO1MLD00+h6POAw6K1d7/+JqVwT12DUp/rjUF2xHhQzl27Y OaIz5jcXgSY42gDg== To: Borislav Petkov , Ingo Molnar , Dave Hansen Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , David Woodhouse , Sean Christopherson , Peter Zijlstra , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v4 28/34] x86/cacheinfo: Use parsed CPUID(0x80000005) and CPUID(0x80000006) Date: Fri, 15 Aug 2025 09:02:21 +0200 Message-ID: <20250815070227.19981-29-darwi@linutronix.de> In-Reply-To: <20250815070227.19981-1-darwi@linutronix.de> References: <20250815070227.19981-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" For the AMD CPUID(0x4)-emulation logic, use parsed CPUID(0x80000005) and CPUID(0x80000006) APID access instead of invoking direct CPUID queries. Beside centralizing CPUID access, this allows using the auto-generated 'struct leaf_0x80000005_0' and 'struct leaf_0x80000006_0' data types. Remove the 'union {l1,l2,l3}_cache' definitions as they are no longer needed. Note, the expression: ci->num_leaves =3D (cpuid_edx(0x80000006) & 0xf000) ? 4 : 3; is replaced with: ci->num_leaves =3D cpuid_leaf(c, 0x80000006)->l3_assoc ? 4 : 3; which is the same logic, since the 'l3_assoc' bitfield is 4 bits wide at EDX offset 12. Per AMD manuals, an L3 associativity of zero implies the absence of an L3 cache on the CPU. While at it, separate the 'Fallback AMD CPUID(0x4) emulation' comment from the '@AMD_L2_L3_INVALID_ASSOC' one, since the former acts as a source code section header. Signed-off-by: Ahmed S. Darwish --- arch/x86/kernel/cpu/cacheinfo.c | 105 ++++++++++++-------------------- 1 file changed, 40 insertions(+), 65 deletions(-) diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinf= o.c index f0540cba4bd4..de8e7125eedd 100644 --- a/arch/x86/kernel/cpu/cacheinfo.c +++ b/arch/x86/kernel/cpu/cacheinfo.c @@ -56,47 +56,17 @@ static const enum cache_type cache_type_map[] =3D { }; =20 /* - * Fallback AMD CPUID(0x4) emulation + * Fallback AMD CPUID(0x4) emulation: * AMD CPUs with TOPOEXT can just use CPUID(0x8000001d) - * + */ + +/* * @AMD_L2_L3_INVALID_ASSOC: cache info for the respective L2/L3 cache sho= uld * be determined from CPUID(0x8000001d) instead of CPUID(0x80000006). */ - #define AMD_CPUID4_FULLY_ASSOCIATIVE 0xffff #define AMD_L2_L3_INVALID_ASSOC 0x9 =20 -union l1_cache { - struct { - unsigned line_size :8; - unsigned lines_per_tag :8; - unsigned assoc :8; - unsigned size_in_kb :8; - }; - unsigned int val; -}; - -union l2_cache { - struct { - unsigned line_size :8; - unsigned lines_per_tag :4; - unsigned assoc :4; - unsigned size_in_kb :16; - }; - unsigned int val; -}; - -union l3_cache { - struct { - unsigned line_size :8; - unsigned lines_per_tag :4; - unsigned assoc :4; - unsigned res :2; - unsigned size_encoded :14; - }; - unsigned int val; -}; - /* L2/L3 associativity mapping */ static const unsigned short assocs[] =3D { [1] =3D 1, @@ -117,50 +87,52 @@ static const unsigned short assocs[] =3D { static const unsigned char levels[] =3D { 1, 1, 2, 3 }; static const unsigned char types[] =3D { 1, 2, 3, 3 }; =20 -static void legacy_amd_cpuid4(int index, struct leaf_0x4_0 *regs) +static void legacy_amd_cpuid4(struct cpuinfo_x86 *c, int index, struct lea= f_0x4_0 *regs) { - unsigned int dummy, line_size, lines_per_tag, assoc, size_in_kb; - union l1_cache l1i, l1d, *l1; - union l2_cache l2; - union l3_cache l3; + const struct leaf_0x80000005_0 *el5 =3D cpuid_leaf(c, 0x80000005); + const struct leaf_0x80000006_0 *el6 =3D cpuid_leaf(c, 0x80000006); + const struct cpuid_regs *el5_raw =3D (const struct cpuid_regs *)el5; + unsigned int line_size, lines_per_tag, assoc, size_in_kb; =20 *regs =3D (struct leaf_0x4_0){ }; =20 - cpuid(0x80000005, &dummy, &dummy, &l1d.val, &l1i.val); - cpuid(0x80000006, &dummy, &dummy, &l2.val, &l3.val); - - l1 =3D &l1d; switch (index) { - case 1: - l1 =3D &l1i; - fallthrough; case 0: - if (!l1->val) + if (!el5 || !el5_raw->ecx) return; =20 - assoc =3D (l1->assoc =3D=3D 0xff) ? AMD_CPUID4_FULLY_ASSOCIATIVE : l1->= assoc; - line_size =3D l1->line_size; - lines_per_tag =3D l1->lines_per_tag; - size_in_kb =3D l1->size_in_kb; + assoc =3D el5->l1_dcache_assoc; + line_size =3D el5->l1_dcache_line_size; + lines_per_tag =3D el5->l1_dcache_nlines; + size_in_kb =3D el5->l1_dcache_size_kb; + break; + case 1: + if (!el5 || !el5_raw->edx) + return; + + assoc =3D el5->l1_icache_assoc; + line_size =3D el5->l1_icache_line_size; + lines_per_tag =3D el5->l1_icache_nlines; + size_in_kb =3D el5->l1_icache_size_kb; break; case 2: - if (!l2.assoc || l2.assoc =3D=3D AMD_L2_L3_INVALID_ASSOC) + if (!el6 || !el6->l2_assoc || el6->l2_assoc =3D=3D AMD_L2_L3_INVALID_ASS= OC) return; =20 /* Use x86_cache_size as it might have K7 errata fixes */ - assoc =3D assocs[l2.assoc]; - line_size =3D l2.line_size; - lines_per_tag =3D l2.lines_per_tag; + assoc =3D assocs[el6->l2_assoc]; + line_size =3D el6->l2_line_size; + lines_per_tag =3D el6->l2_nlines; size_in_kb =3D __this_cpu_read(cpu_info.x86_cache_size); break; case 3: - if (!l3.assoc || l3.assoc =3D=3D AMD_L2_L3_INVALID_ASSOC) + if (!el6 || !el6->l3_assoc || el6->l3_assoc =3D=3D AMD_L2_L3_INVALID_ASS= OC) return; =20 - assoc =3D assocs[l3.assoc]; - line_size =3D l3.line_size; - lines_per_tag =3D l3.lines_per_tag; - size_in_kb =3D l3.size_encoded * 512; + assoc =3D assocs[el6->l3_assoc]; + line_size =3D el6->l3_line_size; + lines_per_tag =3D el6->l3_nlines; + size_in_kb =3D el6->l3_size_range * 512; if (boot_cpu_has(X86_FEATURE_AMD_DCM)) { size_in_kb =3D size_in_kb >> 1; assoc =3D assoc >> 1; @@ -170,6 +142,10 @@ static void legacy_amd_cpuid4(int index, struct leaf_0= x4_0 *regs) return; } =20 + /* For L1d and L1i caches, 0xff is the full associativity marker */ + if ((index =3D=3D 0 || index =3D=3D 1) && assoc =3D=3D 0xff) + assoc =3D AMD_CPUID4_FULLY_ASSOCIATIVE; + regs->cache_self_init =3D 1; regs->cache_type =3D types[index]; regs->cache_level =3D levels[index]; @@ -207,7 +183,7 @@ static int amd_fill_cpuid4_info(struct cpuinfo_x86 *c, = int index, struct _cpuid4 if (boot_cpu_has(X86_FEATURE_TOPOEXT) || boot_cpu_data.x86_vendor =3D=3D = X86_VENDOR_HYGON) regs =3D *(struct leaf_0x4_0 *)cpuid_subleaf_index(c, 0x8000001d, index); else - legacy_amd_cpuid4(index, ®s); + legacy_amd_cpuid4(c, index, ®s); =20 return cpuid4_info_fill_done(id4, ®s); } @@ -279,10 +255,9 @@ void init_amd_cacheinfo(struct cpuinfo_x86 *c) { struct cpu_cacheinfo *ci =3D get_cpu_cacheinfo(c->cpu_index); =20 - if (boot_cpu_has(X86_FEATURE_TOPOEXT)) - ci->num_leaves =3D cpuid_subleaf_count(c, 0x8000001d); - else if (c->extended_cpuid_level >=3D 0x80000006) - ci->num_leaves =3D (cpuid_edx(0x80000006) & 0xf000) ? 4 : 3; + ci->num_leaves =3D boot_cpu_has(X86_FEATURE_TOPOEXT) ? + cpuid_subleaf_count(c, 0x8000001d) : + cpuid_leaf(c, 0x80000006)->l3_assoc ? 4 : 3; } =20 void init_hygon_cacheinfo(struct cpuinfo_x86 *c) --=20 2.50.1 From nobody Sat Oct 4 14:35:16 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 826322F3C3E for ; Fri, 15 Aug 2025 07:06:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755241600; cv=none; b=btqIHN64KfcyRBrhJO1/Xc6+lGuQAfNSh51qUZ9jMUL0GFcm+SXyC0u3HEidWRmXYU6JAKz0c4YHWgmGRo1ggnvu7wt8dRygApBPEEbQN+6/Af67in5FN+sjRh/tIN5GsKQyn3Hk310rAY7M4og5yWl+uY9XOfjwUTcOinVMA7o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755241600; c=relaxed/simple; bh=WKaUMiTigG+J8bPwvdvUyuQgyZRABi8qx0MrNSsQ4S8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=HLCxxwJDy5lpKDpINWEoQz5A6hx7d9DxrMghdgc/3qEjRjh3Id1TRORKVjkoNPKkyHwTmDENxea1d0SZoeaLb0Sg79nuVRq8JKieh+0pdLqYorF/c9p5btDDtWf20QNBuJryC/fPzkKcFnonboZx5tpoM1TismgL7sl2k0ZvbbM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=xtXiwRaB; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=OS4JaMiV; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="xtXiwRaB"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="OS4JaMiV" From: "Ahmed S. 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Peter Anvin" , David Woodhouse , Sean Christopherson , Peter Zijlstra , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v4 29/34] x86/amd_nb: Trickle down 'struct cpuinfo_x86' reference Date: Fri, 15 Aug 2025 09:02:22 +0200 Message-ID: <20250815070227.19981-30-darwi@linutronix.de> In-Reply-To: <20250815070227.19981-1-darwi@linutronix.de> References: <20250815070227.19981-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Prepare cpuid_amd_hygon_has_l3_cache(), which is internally a CPUID(0x80000006) call site, for using the parsed CPUID API instead of invoking direct CPUID queries. Since such an API requires a 'struct cpuinfo_x86' reference, trickle it down from the start of the amd_nb initcall. Note, accessing the CPUID tables at initcall_5 using this_cpu_ptr() should be safe, since the 'struct cpuinfo_x86' per-CPU presentation is finalized at arch/x86/kernel/cpu/common.c :: arch_cpu_finalize_init(). Meanwhile, at kernel init/main.c, do_initcalls() are done much later. Signed-off-by: Ahmed S. Darwish --- arch/x86/kernel/amd_nb.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/amd_nb.c b/arch/x86/kernel/amd_nb.c index c1acead6227a..a8809778b208 100644 --- a/arch/x86/kernel/amd_nb.c +++ b/arch/x86/kernel/amd_nb.c @@ -16,6 +16,7 @@ =20 #include #include +#include =20 static u32 *flush_words; =20 @@ -58,7 +59,7 @@ struct amd_northbridge *node_to_amd_nb(int node) } EXPORT_SYMBOL_GPL(node_to_amd_nb); =20 -static int amd_cache_northbridges(void) +static int amd_cache_northbridges(struct cpuinfo_x86 *c) { struct amd_northbridge *nb; u16 i; @@ -315,11 +316,13 @@ static __init void fix_erratum_688(void) =20 static __init int init_amd_nbs(void) { + struct cpuinfo_x86 *c =3D this_cpu_ptr(&cpu_info); + if (boot_cpu_data.x86_vendor !=3D X86_VENDOR_AMD && boot_cpu_data.x86_vendor !=3D X86_VENDOR_HYGON) return 0; =20 - amd_cache_northbridges(); + amd_cache_northbridges(c); amd_cache_gart(); =20 fix_erratum_688(); --=20 2.50.1 From nobody Sat Oct 4 14:35:16 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 88A432F5486 for ; Fri, 15 Aug 2025 07:06:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755241604; cv=none; b=LGRr4Uq4PVxhWE5QvRIKljKbWqpr4rRBf7LTMsogqwE9zX1+mEt+MZyMcbUJbJsOLPZfEn/XL9ashnFPCXa1aRNhIuGUEAisOLxiYtTyt9IUUQDjyg4vnv8upHejypbS8bg2qqjKcrsMu8gEwYw4LtYr524umYM+FiA4EKOG9zE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755241604; c=relaxed/simple; bh=x5qUMW4GdlHy0LzY544cVlmo8eWHiePuSyCNxjssRmk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Q9E3sky/MVdun5dIPoD/EallcZjIH5nyyqHp8H4T+kSwMaFOIsRNXbMTGFaP2fYE5GYJySYNkuF3nrMpBdusvk6QR8EMnvfqTFzMcwZ9LRe5ZyEXo2R9cz59sBPWJov4/YR58MPiwEKZ4FhfPl1ULqRRrcPQ/aJud3OXRJQV8qc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=EEwjOhjR; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=0OU7cMKE; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="EEwjOhjR"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="0OU7cMKE" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1755241600; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=VI3pBTP8Fjxnacw5/XwagN7sVbZPPDUg06qzVEnLfao=; b=EEwjOhjRDun4/Op48j7WI2XghxYxX0ctzg4nUGO3ftmP9V4PIQMDYFAI9feHN4EjncezpZ xT2LBII85mqX+C9QOioCVl3GtJyOMV97F9NJiKg7OrF/oHLg5G/KMgIIS6UZribnuP3K3d OHiLvH6WMa5eHGGwK2X/iZYeHWbj3ACiXpSBGxHBghymgrGtCjTp2kes/eK7MtEoAcCb3t PWk3h46AcDZAokcQiWdTxJ+LB8cCze0LBabtVxWA2PiU6gGTPawAI7v/fjkt2G5IqN5NDY Yc59HB5+Zo03uP2Qtbg1/AkwtdVMjV/iCqIkNU1WatDswaEh4hD9R9wUawjJmg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1755241600; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=VI3pBTP8Fjxnacw5/XwagN7sVbZPPDUg06qzVEnLfao=; b=0OU7cMKEB6zIOfAVjVXIRau51vMk8fv5Y4+8rikQPqcTyzfWRy0U12pho+q4i2jR/yJbA1 5aJHAVS99aEyQeCA== To: Borislav Petkov , Ingo Molnar , Dave Hansen Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , David Woodhouse , Sean Christopherson , Peter Zijlstra , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v4 30/34] x86/cpuid: Use parsed CPUID(0x80000006) Date: Fri, 15 Aug 2025 09:02:23 +0200 Message-ID: <20250815070227.19981-31-darwi@linutronix.de> In-Reply-To: <20250815070227.19981-1-darwi@linutronix.de> References: <20250815070227.19981-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" For cpuid_amd_hygon_has_l3_cache(), use parsed CPUID access instead of a direct CPUID query. The new API offers centralization benefits and avoids bit fiddling at call sites. For testing L3 cache availability, just check if the EDX.l3_assoc output is not zero. Per AMD manuals, an L3 associativity of zero implies the absence of an L3 cache on the CPU. Note, since this function is now using parsed CPUID API, move it under the section: 'Convenience leaf-specific functions (using parsed CPUID data)' Signed-off-by: Ahmed S. Darwish --- arch/x86/include/asm/cpuid/api.h | 18 +++++++++--------- arch/x86/kernel/amd_nb.c | 2 +- arch/x86/kernel/cpu/cacheinfo.c | 6 +++--- 3 files changed, 13 insertions(+), 13 deletions(-) diff --git a/arch/x86/include/asm/cpuid/api.h b/arch/x86/include/asm/cpuid/= api.h index 146498d5dbfa..d4e50e394e0b 100644 --- a/arch/x86/include/asm/cpuid/api.h +++ b/arch/x86/include/asm/cpuid/api.h @@ -213,15 +213,6 @@ static inline u32 cpuid_base_hypervisor(const char *si= g, u32 leaves) return 0; } =20 -/* - * CPUID(0x80000006) parsing: - */ - -static inline bool cpuid_amd_hygon_has_l3_cache(void) -{ - return cpuid_edx(0x80000006); -} - /* * 'struct cpuid_leaves' accessors: * @@ -519,6 +510,15 @@ static inline bool cpuid_amd_hygon_has_l3_cache(void) _ptr < &((union leaf_0x2_regs *)(_regs))->desc[16] && (_desc =3D &cp= uid_0x2_table[*_ptr]);\ _ptr++) =20 +/* + * CPUID(0x80000006) + */ + +static inline bool cpuid_amd_hygon_has_l3_cache(struct cpuinfo_x86 *c) +{ + return cpuid_leaf(c, 0x80000006)->l3_assoc; +} + /* * CPUID parser exported APIs: */ diff --git a/arch/x86/kernel/amd_nb.c b/arch/x86/kernel/amd_nb.c index a8809778b208..a5d022e15a6b 100644 --- a/arch/x86/kernel/amd_nb.c +++ b/arch/x86/kernel/amd_nb.c @@ -94,7 +94,7 @@ static int amd_cache_northbridges(struct cpuinfo_x86 *c) if (amd_gart_present()) amd_northbridges.flags |=3D AMD_NB_GART; =20 - if (!cpuid_amd_hygon_has_l3_cache()) + if (!cpuid_amd_hygon_has_l3_cache(c)) return 0; =20 /* diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinf= o.c index de8e7125eedd..dc28ffdbdc7f 100644 --- a/arch/x86/kernel/cpu/cacheinfo.c +++ b/arch/x86/kernel/cpu/cacheinfo.c @@ -210,7 +210,7 @@ static int fill_cpuid4_info(struct cpuinfo_x86 *c, int = index, struct _cpuid4_inf =20 void cacheinfo_amd_init_llc_id(struct cpuinfo_x86 *c, u16 die_id) { - if (!cpuid_amd_hygon_has_l3_cache()) + if (!cpuid_amd_hygon_has_l3_cache(c)) return; =20 if (c->x86 < 0x17) { @@ -241,7 +241,7 @@ void cacheinfo_amd_init_llc_id(struct cpuinfo_x86 *c, u= 16 die_id) =20 void cacheinfo_hygon_init_llc_id(struct cpuinfo_x86 *c) { - if (!cpuid_amd_hygon_has_l3_cache()) + if (!cpuid_amd_hygon_has_l3_cache(c)) return; =20 /* @@ -257,7 +257,7 @@ void init_amd_cacheinfo(struct cpuinfo_x86 *c) =20 ci->num_leaves =3D boot_cpu_has(X86_FEATURE_TOPOEXT) ? cpuid_subleaf_count(c, 0x8000001d) : - cpuid_leaf(c, 0x80000006)->l3_assoc ? 4 : 3; + cpuid_amd_hygon_has_l3_cache(c) ? 4 : 3; } =20 void init_hygon_cacheinfo(struct cpuinfo_x86 *c) --=20 2.50.1 From nobody Sat Oct 4 14:35:16 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 14BFB2F60BF for ; Fri, 15 Aug 2025 07:06:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755241607; cv=none; b=MZZ2NPNtR5VPeAbtkz/rUEpBcu1byjGWH7Ta2AJlN7hk0Tr7z5DMEpppxUQcoljcyecInZZtLI7MW3JgJDZl+gKgKtAmEY/e5v7an/1kxgvODUk77tfBrK44/aZpCwL2d/BtnreZ4aw7K70krIW8IFDVwku/Sn7SBwinp9CnoUQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755241607; c=relaxed/simple; bh=T2jnn7H6An6ZppQ8C2g482EY7glbALuRPrTUlZ2ModI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=WeriwiZbdDwl3FEEAa0ZD4sAfJVkoHxLrceElS1cybOOWYQWb2Y4KrXPLeJNK6mr6v4BgyddcAXywDQ8zCWTD/gFwg5KswgYx0UO8+2UZDyQDVcHrXetNYYz32w70rtP/s3JT+Pa23Th00NDykita2pwZeUwhmFPpd/O+7IiHPs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=n0QHX90g; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=81YNADR+; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="n0QHX90g"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="81YNADR+" From: "Ahmed S. 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Peter Anvin" , David Woodhouse , Sean Christopherson , Peter Zijlstra , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v4 31/34] x86/cpu: Rescan CPUID table after PSN disable Date: Fri, 15 Aug 2025 09:02:24 +0200 Message-ID: <20250815070227.19981-32-darwi@linutronix.de> In-Reply-To: <20250815070227.19981-1-darwi@linutronix.de> References: <20250815070227.19981-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" On Pentium-III and Transmeta CPUs, disabling the CPUID(0x3) Processor Serial Number (PSN) can affect the maximum valid CPUID standard leaf. Rescan the CPU's CPUID table in that case, not to have stale cached data. Use parsed CPUID(0x0) access, instead of direct CPUID query, afterwards. Rename squash_the_stupid_serial_number() to disable_cpu_serial_number() and explain the rational for disabling the CPU's PSN. Signed-off-by: Ahmed S. Darwish --- arch/x86/kernel/cpu/common.c | 20 +++++++++++++------- 1 file changed, 13 insertions(+), 7 deletions(-) diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 048b285e7741..64038637bf4a 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -328,15 +328,17 @@ bool cpuid_feature(void) return flag_is_changeable_p(X86_EFLAGS_ID); } =20 -static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) +/* + * For privacy concerns, disable legacy Intel and Transmeta CPUID(0x3) + * feature, Processor Serial Number, by default. + */ +static void disable_cpu_serial_number(struct cpuinfo_x86 *c) { unsigned long lo, hi; =20 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr) return; =20 - /* Disable processor serial number: */ - rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); lo |=3D 0x200000; wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); @@ -344,8 +346,12 @@ static void squash_the_stupid_serial_number(struct cpu= info_x86 *c) pr_notice("CPU serial number disabled.\n"); clear_cpu_cap(c, X86_FEATURE_PN); =20 - /* Disabling the serial number may affect the cpuid level */ - c->cpuid_level =3D cpuid_eax(0); + /* + * Disabling CPUID(0x3) might have affected the maximum standard + * CPUID level. Rescan the CPU's CPUID table afterwards. + */ + cpuid_parser_scan_cpu(c); + c->cpuid_level =3D cpuid_leaf(c, 0x0)->max_std_leaf; } =20 static int __init x86_serial_nr_setup(char *s) @@ -355,7 +361,7 @@ static int __init x86_serial_nr_setup(char *s) } __setup("serialnumber", x86_serial_nr_setup); #else -static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) +static inline void disable_cpu_serial_number(struct cpuinfo_x86 *c) { } #endif @@ -1982,7 +1988,7 @@ static void identify_cpu(struct cpuinfo_x86 *c) bus_lock_init(); =20 /* Disable the PN if appropriate */ - squash_the_stupid_serial_number(c); + disable_cpu_serial_number(c); =20 /* Set up SMEP/SMAP/UMIP */ setup_smep(c); --=20 2.50.1 From nobody Sat Oct 4 14:35:16 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6D5D02F49FA for ; Fri, 15 Aug 2025 07:06:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755241610; cv=none; b=EIp/gxCu55IeDz8/R+1F4c8eTWUFZRY8ZN5WhOV/FX2IDRfsuvMjoRK+X+QTsPAk2r0rO4DcjouLEYH+ugMTpz5JL/ODX5H8vxq9Ei4V2+gvozlS45CrUISln1q2zDWUgL0/7WUKCOic61iAB3gS2PxgAdGQbCJB6NdNaQcQTW8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755241610; c=relaxed/simple; bh=bs6ID0keeNxIWVK/mx/m/477rleOKy/Zl9acDnCWP6I=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=hh7tfjhCnvV4qDxp+5s90QYLEJFD5QvooYCXpT7lJlVOmdSLOJYO9ykqBARi++dL7oAE5R8uKnn+gRCCSDSBFYCM3JSJRgcpVvzyyD1kkTwHwlcL0A92t1OLlbkrpn6BqdA+0w0b+k8QXgGfiwq8u46XDN//qzPzybiexiRxM7o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=oBZXma/e; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=Oy/hprgt; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="oBZXma/e"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="Oy/hprgt" From: "Ahmed S. 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Peter Anvin" , David Woodhouse , Sean Christopherson , Peter Zijlstra , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v4 32/34] x86/cpu: Rescan CPUID table after unlocking full CPUID range Date: Fri, 15 Aug 2025 09:02:25 +0200 Message-ID: <20250815070227.19981-33-darwi@linutronix.de> In-Reply-To: <20250815070227.19981-1-darwi@linutronix.de> References: <20250815070227.19981-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Intel CPUs have an MSR bit to limit CPUID enumeration to leaf two, which can be set by old BIOSen before booting Linux. Rescan the CPUID table after unlocking the CPU's full CPUID range. Use parsed CPUID(0x0) access, instead of a direct CPUID query, afterwards. References: 066941bd4eeb ("x86: unmask CPUID levels on Intel CPUs") References: 0c2f6d04619e ("x86/topology/intel: Unlock CPUID before evaluati= ng anything") Signed-off-by: Ahmed S. Darwish --- arch/x86/kernel/cpu/intel.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index 06c249110c8b..fe4d1cf479c2 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -192,11 +192,14 @@ void intel_unlock_cpuid_leafs(struct cpuinfo_x86 *c) return; =20 /* - * The BIOS can have limited CPUID to leaf 2, which breaks feature - * enumeration. Unlock it and update the maximum leaf info. + * Intel CPUs have an MSR bit to limit CPUID enumeration to CPUID(0x2), + * which can be set by old BIOSes before booting Linux. If enabled, + * unlock the CPU's full CPUID range and rescan its CPUID table. */ - if (msr_clear_bit(MSR_IA32_MISC_ENABLE, MSR_IA32_MISC_ENABLE_LIMIT_CPUID_= BIT) > 0) - c->cpuid_level =3D cpuid_eax(0); + if (msr_clear_bit(MSR_IA32_MISC_ENABLE, MSR_IA32_MISC_ENABLE_LIMIT_CPUID_= BIT) > 0) { + cpuid_parser_scan_cpu(c); + c->cpuid_level =3D cpuid_leaf(c, 0x0)->max_std_leaf; + } } =20 static void early_init_intel(struct cpuinfo_x86 *c) --=20 2.50.1 From nobody Sat Oct 4 14:35:16 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5C20C2F7450 for ; Fri, 15 Aug 2025 07:06:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755241613; cv=none; b=dle96hhR0xXK5wS37P5fiaCMWekA9hMYBhixlHVmvGBC2thFAUg/+glKOG3XWg4Uq7OSVjdztasrErV2kKiiQeKAqvVHMUNY8gC13FPR9cW58Qf8RF8+11LjZu77faRBe6GfLw0aVnL8bBpDhRahu8tcQ5PJU13vFupotCatvNg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755241613; c=relaxed/simple; bh=9z1Sdq4BhIr3DLajt8jgfRyN+bMto1EjY0iFvW8JoCs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=O/BrnKPt1yBGX8H6IuJzjR/RTU7gqhLLX9fpl45wVHdp09eSgXWrcSfGcSmMp+SmPidZhnHQKwqFu1GOEQ7mUzoA00q0mlvzBgYbqbRKLq3mpM2n8wtn+gb3YvUzXbqyx7cq1nErXYfPDcjggCOdNy6+2FaTy14x23FeBTJlQmA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=WolOd4bg; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=mmZh6UEo; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="WolOd4bg"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="mmZh6UEo" From: "Ahmed S. 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Peter Anvin" , David Woodhouse , Sean Christopherson , Peter Zijlstra , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v4 33/34] x86/cpuid: Parse CPUID(0x16) Date: Fri, 15 Aug 2025 09:02:26 +0200 Message-ID: <20250815070227.19981-34-darwi@linutronix.de> In-Reply-To: <20250815070227.19981-1-darwi@linutronix.de> References: <20250815070227.19981-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add CPUID(0x16) support to the CPUID parser. It enumerates processor frequency information. Query the leaf only for Intel machines, as this is where it is supported. This allows converting CPUID(0x16) call sites to the new CPUID parser APIs next. Signed-off-by: Ahmed S. Darwish --- arch/x86/include/asm/cpuid/types.h | 1 + arch/x86/kernel/cpu/cpuid_parser.h | 2 ++ 2 files changed, 3 insertions(+) diff --git a/arch/x86/include/asm/cpuid/types.h b/arch/x86/include/asm/cpui= d/types.h index 63d2569e2821..c044f7bc7137 100644 --- a/arch/x86/include/asm/cpuid/types.h +++ b/arch/x86/include/asm/cpuid/types.h @@ -217,6 +217,7 @@ struct cpuid_leaves { CPUID_LEAF(0x1, 0, 1); CPUID_LEAF(0x2, 0, 1); CPUID_LEAF(0x4, 0, 8); + CPUID_LEAF(0x16, 0, 1); CPUID_LEAF(0x80000000, 0, 1); CPUID_LEAF(0x80000005, 0, 1); CPUID_LEAF(0x80000006, 0, 1); diff --git a/arch/x86/kernel/cpu/cpuid_parser.h b/arch/x86/kernel/cpu/cpuid= _parser.h index 1d0d1a3c2bb8..9ac66abeae81 100644 --- a/arch/x86/kernel/cpu/cpuid_parser.h +++ b/arch/x86/kernel/cpu/cpuid_parser.h @@ -129,6 +129,7 @@ struct cpuid_parse_entry { /* Leaf Subleaf Reader function */ \ CPUID_PARSE_ENTRY(0x2, 0, 0x2), \ CPUID_PARSE_ENTRY(0x4, 0, deterministic_cache), \ + CPUID_PARSE_ENTRY(0x16, 0, generic), \ CPUID_PARSE_ENTRY(0x80000000, 0, 0x80000000), \ CPUID_PARSE_ENTRY(0x80000005, 0, generic), \ CPUID_PARSE_ENTRY(0x80000006, 0, generic), \ @@ -167,6 +168,7 @@ struct cpuid_vendor_entry { /* Leaf Vendor list */ \ CPUID_VENDOR_ENTRY(0x2, X86_VENDOR_INTEL, X86_VENDOR_CENTAUR, X86_VENDOR= _ZHAOXIN),\ CPUID_VENDOR_ENTRY(0x4, X86_VENDOR_INTEL, X86_VENDOR_CENTAUR, X86_VENDOR= _ZHAOXIN),\ + CPUID_VENDOR_ENTRY(0x16, X86_VENDOR_INTEL), \ CPUID_VENDOR_ENTRY(0x8000001d, X86_VENDOR_AMD, X86_VENDOR_HYGON), \ =20 #endif /* _ARCH_X86_CPUID_PARSER_H */ --=20 2.50.1 From nobody Sat Oct 4 14:35:16 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 58E7C2F83DA for ; Fri, 15 Aug 2025 07:06:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755241616; cv=none; b=YLZAsbajLLUkX9gDDdK6+QwVUQrRtqLw9eQMe5dxkoYRH2GwqeuC8ELxKq9ptQBgODE92Imx/+97/K0XjHOoPI+e0P5J70Kj0GlFZhtoUy7Vbxu4i2NLCbyOuWlmvNhsT5qEvFCoHds+IDQg0jvms0/NhnAb/1WjzSeiBXHVTsY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755241616; c=relaxed/simple; bh=2p3mVQR6Pei4EbU9vfHkMqnuC71LnqWy+OEui4qrQhk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=czlOEAdPsshzzXqr01DUD/HFYhph0917g4KlzfulYUZ7mNawjjHQ9nLjfmENomxh4mqcWdguAEr7CzRCl/jms30AiQ3UAeeviK9nxoK1lkZ+v8YynsHwDnqKoIb7gIVNndOJ/9CdXDdipBXc+h8bT7HSjH8KXYgQDx4D3jc4W4M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=wy0SeTkS; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=XfP1BrBq; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="wy0SeTkS"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="XfP1BrBq" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1755241614; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Lr8g2138fQgNu0HI5HEQ50NVYhPOnkdlyJJ7xfGQCns=; b=wy0SeTkS2d6Mdb9+Q1aIiW39aynWaseSM445L+/4iabdY6oC+Il0otO6B9YkbiD6TrJRcC QrsrKGq1PIord+n9sCTv6/SBc5Q3D4xildNm5RBTTMOKCT9+QpZRSimZLCEv3jcwg48xbW Gi+y1tBR7vZ1hyKXkbv5IpRlwiJBK302pHq8/ffGrhPYQOjCKkhC2x1jevNmIa5+aGjmh7 RnmE19XpnuNeENYpx2JI2MyDoteTNGWBn4QSmb1QAWmgr2JfFQWgOgLOcU2JVCaRUSrYMe FQ5zI7DjfHlNHNXspI4MkiFFJZGm0NLhZRX1vgs8bACz9umDBvOlvCgysE44ow== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1755241614; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Lr8g2138fQgNu0HI5HEQ50NVYhPOnkdlyJJ7xfGQCns=; b=XfP1BrBqt1e2Sww0FRaPWW3nSiAAUHedLKhuBdGHHmBAgouwJ8CTnJV5nOwt6IftaPa+FW b4RosLL7da4tdNBA== To: Borislav Petkov , Ingo Molnar , Dave Hansen Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , David Woodhouse , Sean Christopherson , Peter Zijlstra , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v4 34/34] x86/tsc: Use parsed CPUID(0x16) Date: Fri, 15 Aug 2025 09:02:27 +0200 Message-ID: <20250815070227.19981-35-darwi@linutronix.de> In-Reply-To: <20250815070227.19981-1-darwi@linutronix.de> References: <20250815070227.19981-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Use parsed CPUID(0x16) access instead of direct CPUID queries. Remove the "max standard CPUID level >=3D CPUID_LEVEL_FREQ" checks since the CPUID parser API's NULL check is equivalent. At cpu_khz_from_cpuid(), remove the Intel vendor check. The CPUID parser caches this leaf output for Intel machines only, thus the CPUID parser API's NULL check is also equivalent. Signed-off-by: Ahmed S. Darwish --- arch/x86/kernel/tsc.c | 24 +++++------------------- 1 file changed, 5 insertions(+), 19 deletions(-) diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c index 87e749106dda..34da49d45d85 100644 --- a/arch/x86/kernel/tsc.c +++ b/arch/x86/kernel/tsc.c @@ -662,6 +662,7 @@ static unsigned long quick_pit_calibrate(void) */ unsigned long native_calibrate_tsc(void) { + const struct leaf_0x16_0 *l16 =3D cpuid_leaf(&boot_cpu_data, 0x16); unsigned int eax_denominator, ebx_numerator, ecx_hz, edx; unsigned int crystal_khz; =20 @@ -703,13 +704,8 @@ unsigned long native_calibrate_tsc(void) * clock, but we can easily calculate it to a high degree of accuracy * by considering the crystal ratio and the CPU speed. */ - if (crystal_khz =3D=3D 0 && boot_cpu_data.cpuid_level >=3D CPUID_LEAF_FRE= Q) { - unsigned int eax_base_mhz, ebx, ecx, edx; - - cpuid(CPUID_LEAF_FREQ, &eax_base_mhz, &ebx, &ecx, &edx); - crystal_khz =3D eax_base_mhz * 1000 * - eax_denominator / ebx_numerator; - } + if (crystal_khz =3D=3D 0 && l16) + crystal_khz =3D l16->cpu_base_mhz * 1000 * eax_denominator / ebx_numerat= or; =20 if (crystal_khz =3D=3D 0) return 0; @@ -736,19 +732,9 @@ unsigned long native_calibrate_tsc(void) =20 static unsigned long cpu_khz_from_cpuid(void) { - unsigned int eax_base_mhz, ebx_max_mhz, ecx_bus_mhz, edx; - - if (boot_cpu_data.x86_vendor !=3D X86_VENDOR_INTEL) - return 0; - - if (boot_cpu_data.cpuid_level < CPUID_LEAF_FREQ) - return 0; - - eax_base_mhz =3D ebx_max_mhz =3D ecx_bus_mhz =3D edx =3D 0; - - cpuid(CPUID_LEAF_FREQ, &eax_base_mhz, &ebx_max_mhz, &ecx_bus_mhz, &edx); + const struct leaf_0x16_0 *l16 =3D cpuid_leaf(&boot_cpu_data, 0x16); =20 - return eax_base_mhz * 1000; + return l16 ? (l16->cpu_base_mhz * 1000) : 0; } =20 /* --=20 2.50.1