From nobody Sat Oct 4 14:17:00 2025 Received: from esa1.hc1455-7.c3s2.iphmx.com (esa1.hc1455-7.c3s2.iphmx.com [207.54.90.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DE5B91514F7; Fri, 15 Aug 2025 03:49:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=207.54.90.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755229782; cv=none; b=b/7RRgNQrcvDokeS9XhVR8t4RPUCbfplPLQZlDlG7Ml5k2SJYXcwMgnYF/Xrrl4RescMGDyFmbg2MhyH+pTugKfzESA41cqU63UWx2Kco4wTp/lof+PbVhGu/ufCzRaEBO64Ze7ashZYkiynWrvw/5/3O4pzXv8qYTE3w76Id9Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755229782; c=relaxed/simple; bh=cauXBFk4tE6lWLQXyaLXuOCAJb35Bq/CwMVdNesQLgo=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=dPTAZ4B5fFaAdwTUeBXRvFAyxHgf/lmWCYeqgPX8OoNVcHf2t+QXmw+LMhHjUJTAmYKUNOPoc8R0ZV6Y7SwrRpiR7YoOl6FIMQ160t+qiSPe+Tfc6k3PA1MyBNJDSEgmo638Qi5XN4uinGRzgjfGaxTIFCclnokGfjOY6K6S15g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=fujitsu.com; spf=pass smtp.mailfrom=fujitsu.com; dkim=pass (2048-bit key) header.d=fujitsu.com header.i=@fujitsu.com header.b=t+Zxn+B2; arc=none smtp.client-ip=207.54.90.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=fujitsu.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=fujitsu.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=fujitsu.com header.i=@fujitsu.com header.b="t+Zxn+B2" DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=fujitsu.com; i=@fujitsu.com; q=dns/txt; s=fj2; t=1755229781; x=1786765781; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=cauXBFk4tE6lWLQXyaLXuOCAJb35Bq/CwMVdNesQLgo=; b=t+Zxn+B2QDH3HrfjzYBxmWpj8N3fp96iIJex626xPG1sb018Vz0ho5Wq H46DVhCP2qIaecSsVlM7CZn7aaCSuJVwfPYIw1SKtRecMBORfkRcyBr6m xKiNGaZR2mkJC8TyQdvCZv8BmRRq80bXd2apTRpC1xJ6e9AFfzfRnm3Qe jPTK6eFmWJ4rcCoSd+vNXuhtNrwzot2Sa0O1txP4F1UUjHmsmcnLg5kLH DYCYr0J04VsBuMm19uajwTbPa+dtwBmOCylB6yGRtpFNnfzSjpnU2N/qJ LChejpptDf2G26gV7za3gTS27l/0u+oDcdPlv5DKr+fALyBTuqtRjHaw2 g==; X-CSE-ConnectionGUID: 9ldmbF0yQMi+lIzcLpvFFw== X-CSE-MsgGUID: MF39G4vAROKSNjOE61i6pg== X-IronPort-AV: E=McAfee;i="6800,10657,11522"; a="209397936" X-IronPort-AV: E=Sophos;i="6.17,290,1747666800"; d="scan'208";a="209397936" Received: from unknown (HELO az2nlsmgr4.o.css.fujitsu.com) ([51.138.80.169]) by esa1.hc1455-7.c3s2.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Aug 2025 12:48:29 +0900 Received: from az2nlsmgm4.fujitsu.com (unknown [10.150.26.204]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by az2nlsmgr4.o.css.fujitsu.com (Postfix) with ESMTPS id D09BB42A318; Fri, 15 Aug 2025 03:48:28 +0000 (UTC) Received: from az2nlsmom1.o.css.fujitsu.com (az2nlsmom1.o.css.fujitsu.com [10.150.26.198]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by az2nlsmgm4.fujitsu.com (Postfix) with ESMTPS id 8A1251020977; Fri, 15 Aug 2025 03:48:23 +0000 (UTC) Received: from sm-arm-grace07.ssoft.mng.com (sm-x86-stp01.soft.fujitsu.com [10.124.178.20]) by az2nlsmom1.o.css.fujitsu.com (Postfix) with ESMTP id DC24482918F; Fri, 15 Aug 2025 03:48:15 +0000 (UTC) From: Koichi Okuno To: Will Deacon , Mark Rutland , Jonathan Corbet , Catalin Marinas , Gowthami Thiagarajan , Linu Cherian , Robin Murphy , linux-arm-kernel@lists.infradead.org, Bjorn Andersson , Geert Uytterhoeven , Krzysztof Kozlowski , Konrad Dybcio , Neil Armstrong , Arnd Bergmann , =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= , Thomas Gleixner , Peter Zijlstra , Jonathan Cameron , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, Koichi Okuno Subject: [PATCH v7 1/2] perf: Fujitsu: Add the Uncore MAC PMU driver Date: Fri, 15 Aug 2025 12:47:28 +0900 Message-ID: <20250815034751.3726963-2-fj2767dz@fujitsu.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250815034751.3726963-1-fj2767dz@fujitsu.com> References: <20250815034751.3726963-1-fj2767dz@fujitsu.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds a new dynamic PMU to the Perf Events framework to program and control the Uncore MAC PMUs in Fujitsu chips. This driver was created with reference to drivers/perf/qcom_l3_pmu.c. This driver exports formatting and event information to sysfs so it can be used by the perf user space tools with the syntaxes: perf stat -e mac_iod0_mac0_ch0/ea-mac/ ls perf stat -e mac_iod0_mac0_ch0/event=3D0x80/ ls FUJITSU-MONAKA PMU Events Specification v1.1 URL: https://github.com/fujitsu/FUJITSU-MONAKA Signed-off-by: Koichi Okuno Reviewed-by: Jonathan Cameron --- .../admin-guide/perf/fujitsu_mac_pmu.rst | 73 +++ Documentation/admin-guide/perf/index.rst | 1 + drivers/perf/Kconfig | 9 + drivers/perf/Makefile | 1 + drivers/perf/fujitsu_mac_pmu.c | 552 ++++++++++++++++++ 5 files changed, 636 insertions(+) create mode 100644 Documentation/admin-guide/perf/fujitsu_mac_pmu.rst create mode 100644 drivers/perf/fujitsu_mac_pmu.c diff --git a/Documentation/admin-guide/perf/fujitsu_mac_pmu.rst b/Documenta= tion/admin-guide/perf/fujitsu_mac_pmu.rst new file mode 100644 index 000000000000..383f3c1bbde7 --- /dev/null +++ b/Documentation/admin-guide/perf/fujitsu_mac_pmu.rst @@ -0,0 +1,73 @@ +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D +Fujitsu Uncore MAC Performance Monitoring Unit (PMU) +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D + +This driver supports the Uncore MAC PMUs found in Fujitsu chips. +Each MAC PMU on these chips is exposed as a uncore perf PMU with device na= me +mac_iod_mac_ch. + +The driver provides a description of its available events and configuration +options in sysfs, see /sys/bus/event_sources/devices/mac_iod_mac= _ch/. +This driver exports: +- formats, used by perf user space and other tools to configure events +- events, used by perf user space and other tools to create events + symbolically, e.g.: + perf stat -a -e mac_iod0_mac0_ch0/event=3D0x21/ ls +- cpumask, used by perf user space and other tools to know on which CPUs + to open the events + +This driver supports the following events: +- cycles + This event counts MAC cycles at MAC frequency. +- read-count + This event counts the number of read requests to MAC. +- read-count-request + This event counts the number of read requests including retry to MAC. +- read-count-return + This event counts the number of responses to read requests to MAC. +- read-count-request-pftgt + This event counts the number of read requests including retry with PFTGT + flag. +- read-count-request-normal + This event counts the number of read requests including retry without PF= TGT + flag. +- read-count-return-pftgt-hit + This event counts the number of responses to read requests which hit the + PFTGT buffer. +- read-count-return-pftgt-miss + This event counts the number of responses to read requests which miss the + PFTGT buffer. +- read-wait + This event counts outstanding read requests issued by DDR memory control= ler + per cycle. +- write-count + This event counts the number of write requests to MAC (including zero wr= ite, + full write, partial write, write cancel). +- write-count-write + This event counts the number of full write requests to MAC (not including + zero write). +- write-count-pwrite + This event counts the number of partial write requests to MAC. +- memory-read-count + This event counts the number of read requests from MAC to memory. +- memory-write-count + This event counts the number of full write requests from MAC to memory. +- memory-pwrite-count + This event counts the number of partial write requests from MAC to memor= y. +- ea-mac + This event counts energy consumption of MAC. +- ea-memory + This event counts energy consumption of memory. +- ea-memory-mac-write + This event counts the number of write requests from MAC to memory. +- ea-ha + This event counts energy consumption of HA. + + 'ea' is the abbreviation for 'Energy Analyzer'. + +Examples for use with perf:: + + perf stat -e mac_iod0_mac0_ch0/ea-mac/ ls + +Given that these are uncore PMUs the driver does not support sampling, the= refore +"perf record" will not work. Per-task perf sessions are not supported. diff --git a/Documentation/admin-guide/perf/index.rst b/Documentation/admin= -guide/perf/index.rst index 072b510385c4..e0262060db17 100644 --- a/Documentation/admin-guide/perf/index.rst +++ b/Documentation/admin-guide/perf/index.rst @@ -29,3 +29,4 @@ Performance monitor support cxl ampere_cspmu mrvl-pem-pmu + fujitsu_mac_pmu diff --git a/drivers/perf/Kconfig b/drivers/perf/Kconfig index a9188dec36fe..ab4e44c99a53 100644 --- a/drivers/perf/Kconfig +++ b/drivers/perf/Kconfig @@ -178,6 +178,15 @@ config FSL_IMX9_DDR_PMU can give information about memory throughput and other related events. =20 +config FUJITSU_MAC_PMU + bool "Fujitsu Uncore MAC PMU" + depends on (ARM64 && (ACPI || COMPILE_TEST)) + help + Provides support for the Uncore MAC performance monitor unit (PMU) + in Fujitsu processors. + Adds the Uncore MAC PMU into the perf events subsystem for + monitoring Uncore MAC events. + config QCOM_L2_PMU bool "Qualcomm Technologies L2-cache PMU" depends on ARCH_QCOM && ARM64 && ACPI diff --git a/drivers/perf/Makefile b/drivers/perf/Makefile index 192fc8b16204..be7f74c3b14c 100644 --- a/drivers/perf/Makefile +++ b/drivers/perf/Makefile @@ -14,6 +14,7 @@ obj-$(CONFIG_ARM_SMMU_V3_PMU) +=3D arm_smmuv3_pmu.o obj-$(CONFIG_FSL_IMX8_DDR_PMU) +=3D fsl_imx8_ddr_perf.o obj-$(CONFIG_FSL_IMX9_DDR_PMU) +=3D fsl_imx9_ddr_perf.o obj-$(CONFIG_HISI_PMU) +=3D hisilicon/ +obj-$(CONFIG_FUJITSU_MAC_PMU) +=3D fujitsu_mac_pmu.o obj-$(CONFIG_QCOM_L2_PMU) +=3D qcom_l2_pmu.o obj-$(CONFIG_QCOM_L3_PMU) +=3D qcom_l3_pmu.o obj-$(CONFIG_RISCV_PMU) +=3D riscv_pmu.o diff --git a/drivers/perf/fujitsu_mac_pmu.c b/drivers/perf/fujitsu_mac_pmu.c new file mode 100644 index 000000000000..1031e0221bb2 --- /dev/null +++ b/drivers/perf/fujitsu_mac_pmu.c @@ -0,0 +1,552 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Driver for the Uncore MAC PMUs in Fujitsu chips. + * + * See Documentation/admin-guide/perf/fujitsu_mac_pmu.rst for more details. + * + * This driver is based on drivers/perf/qcom_l3_pmu.c + * Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. + * Copyright (c) 2024 Fujitsu. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Number of counters on each PMU */ +#define MAC_NUM_COUNTERS 8 +/* Mask for the event type field within perf_event_attr.config and EVTYPE = reg */ +#define MAC_EVTYPE_MASK 0xFF + +/* Perfmon registers */ +#define MAC_PM_EVCNTR(__cntr) (0x000 + (__cntr) * 8) +#define MAC_PM_CNTCTL(__cntr) (0x100 + (__cntr) * 8) +#define MAC_PM_CNTCTL_RESET 0 +#define MAC_PM_EVTYPE(__cntr) (0x200 + (__cntr) * 8) +#define MAC_PM_EVTYPE_EVSEL(__val) FIELD_GET(MAC_EVTYPE_MASK, __val) +#define MAC_PM_CR 0x400 +#define MAC_PM_CR_RESET BIT(1) +#define MAC_PM_CR_ENABLE BIT(0) +#define MAC_PM_CNTENSET 0x410 +#define MAC_PM_CNTENSET_IDX(__cntr) BIT(__cntr) +#define MAC_PM_CNTENCLR 0x418 +#define MAC_PM_CNTENCLR_IDX(__cntr) BIT(__cntr) +#define MAC_PM_CNTENCLR_RESET 0xFF +#define MAC_PM_INTENSET 0x420 +#define MAC_PM_INTENSET_IDX(__cntr) BIT(__cntr) +#define MAC_PM_INTENCLR 0x428 +#define MAC_PM_INTENCLR_IDX(__cntr) BIT(__cntr) +#define MAC_PM_INTENCLR_RESET 0xFF +#define MAC_PM_OVSR 0x440 +#define MAC_PM_OVSR_OVSRCLR_RESET 0xFF + +#define MAC_EVENT_CYCLES 0x000 +#define MAC_EVENT_READ_COUNT 0x010 +#define MAC_EVENT_READ_COUNT_REQUEST 0x011 +#define MAC_EVENT_READ_COUNT_RETURN 0x012 +#define MAC_EVENT_READ_COUNT_REQUEST_PFTGT 0x013 +#define MAC_EVENT_READ_COUNT_REQUEST_NORMAL 0x014 +#define MAC_EVENT_READ_COUNT_RETURN_PFTGT_HIT 0x015 +#define MAC_EVENT_READ_COUNT_RETURN_PFTGT_MISS 0x016 +#define MAC_EVENT_READ_WAIT 0x017 +#define MAC_EVENT_WRITE_COUNT 0x020 +#define MAC_EVENT_WRITE_COUNT_WRITE 0x021 +#define MAC_EVENT_WRITE_COUNT_PWRITE 0x022 +#define MAC_EVENT_MEMORY_READ_COUNT 0x040 +#define MAC_EVENT_MEMORY_WRITE_COUNT 0x050 +#define MAC_EVENT_MEMORY_PWRITE_COUNT 0x060 +#define MAC_EVENT_EA_MAC 0x080 +#define MAC_EVENT_EA_MEMORY 0x090 +#define MAC_EVENT_EA_MEMORY_MAC_WRITE 0x092 +#define MAC_EVENT_EA_HA 0x0a0 + +struct mac_pmu { + struct pmu pmu; + struct hlist_node node; + void __iomem *regs; + struct perf_event *events[MAC_NUM_COUNTERS]; + unsigned long used_mask[BITS_TO_LONGS(MAC_NUM_COUNTERS)]; + cpumask_t cpumask; +}; + +#define to_mac_pmu(p) (container_of(p, struct mac_pmu, pmu)) + +static int mac_pmu_cpuhp_state; + +static void fujitsu_mac_counter_start(struct perf_event *event) +{ + struct mac_pmu *macpmu =3D to_mac_pmu(event->pmu); + int idx =3D event->hw.idx; + + /* Initialize the hardware counter and reset prev_count*/ + local64_set(&event->hw.prev_count, 0); + writeq_relaxed(0, macpmu->regs + MAC_PM_EVCNTR(idx)); + + /* Set the event type */ + writeq_relaxed(MAC_PM_EVTYPE_EVSEL(event->attr.config), macpmu->regs + MA= C_PM_EVTYPE(idx)); + + /* Enable interrupt generation by this counter */ + writeq_relaxed(MAC_PM_INTENSET_IDX(idx), macpmu->regs + MAC_PM_INTENSET); + + /* Finally, enable the counter */ + writeq_relaxed(MAC_PM_CNTCTL_RESET, macpmu->regs + MAC_PM_CNTCTL(idx)); + writeq_relaxed(MAC_PM_CNTENSET_IDX(idx), macpmu->regs + MAC_PM_CNTENSET); +} + +static void fujitsu_mac_counter_stop(struct perf_event *event, + int flags) +{ + struct mac_pmu *macpmu =3D to_mac_pmu(event->pmu); + int idx =3D event->hw.idx; + + /* Disable the counter */ + writeq_relaxed(MAC_PM_CNTENCLR_IDX(idx), macpmu->regs + MAC_PM_CNTENCLR); + + /* Disable interrupt generation by this counter */ + writeq_relaxed(MAC_PM_INTENCLR_IDX(idx), macpmu->regs + MAC_PM_INTENCLR); +} + +static void fujitsu_mac_counter_update(struct perf_event *event) +{ + struct mac_pmu *macpmu =3D to_mac_pmu(event->pmu); + int idx =3D event->hw.idx; + u64 prev, new; + + do { + prev =3D local64_read(&event->hw.prev_count); + new =3D readq_relaxed(macpmu->regs + MAC_PM_EVCNTR(idx)); + } while (local64_cmpxchg(&event->hw.prev_count, prev, new) !=3D prev); + + local64_add(new - prev, &event->count); +} + +static inline void fujitsu_mac__init(struct mac_pmu *macpmu) +{ + int i; + + writeq_relaxed(MAC_PM_CR_RESET, macpmu->regs + MAC_PM_CR); + + writeq_relaxed(MAC_PM_CNTENCLR_RESET, macpmu->regs + MAC_PM_CNTENCLR); + writeq_relaxed(MAC_PM_INTENCLR_RESET, macpmu->regs + MAC_PM_INTENCLR); + writeq_relaxed(MAC_PM_OVSR_OVSRCLR_RESET, macpmu->regs + MAC_PM_OVSR); + + for (i =3D 0; i < MAC_NUM_COUNTERS; ++i) { + writeq_relaxed(MAC_PM_CNTCTL_RESET, macpmu->regs + MAC_PM_CNTCTL(i)); + writeq_relaxed(MAC_PM_EVTYPE_EVSEL(0), macpmu->regs + MAC_PM_EVTYPE(i)); + } + + /* + * Use writeq here to ensure all programming commands are done + * before proceeding + */ + writeq(MAC_PM_CR_ENABLE, macpmu->regs + MAC_PM_CR); +} + +static irqreturn_t fujitsu_mac__handle_irq(int irq_num, void *data) +{ + struct mac_pmu *macpmu =3D data; + /* Read the overflow status register */ + long status =3D readq_relaxed(macpmu->regs + MAC_PM_OVSR); + int idx; + + if (status =3D=3D 0) + return IRQ_NONE; + + /* Clear the bits we read on the overflow status register */ + writeq_relaxed(status, macpmu->regs + MAC_PM_OVSR); + + for_each_set_bit(idx, &status, MAC_NUM_COUNTERS) { + struct perf_event *event; + + event =3D macpmu->events[idx]; + if (!event) + continue; + + fujitsu_mac_counter_update(event); + } + + return IRQ_HANDLED; +} + +static void fujitsu_mac__pmu_enable(struct pmu *pmu) +{ + struct mac_pmu *macpmu =3D to_mac_pmu(pmu); + + /* Ensure the other programming commands are observed before enabling */ + wmb(); + + writeq_relaxed(MAC_PM_CR_ENABLE, macpmu->regs + MAC_PM_CR); +} + +static void fujitsu_mac__pmu_disable(struct pmu *pmu) +{ + struct mac_pmu *macpmu =3D to_mac_pmu(pmu); + + writeq_relaxed(0, macpmu->regs + MAC_PM_CR); + + /* Ensure the basic counter unit is stopped before proceeding */ + wmb(); +} + +/* + * We must NOT create groups containing events from multiple hardware PMUs, + * although mixing different software and hardware PMUs is allowed. + */ +static bool fujitsu_mac__validate_event_group(struct perf_event *event) +{ + struct perf_event *leader =3D event->group_leader; + struct perf_event *sibling; + int counters; + + if (leader->pmu !=3D event->pmu && !is_software_event(leader)) + return false; + + /* The sum of the counters used by the event and its leader event */ + counters =3D 2; + + for_each_sibling_event(sibling, leader) { + if (is_software_event(sibling)) + continue; + if (sibling->pmu !=3D event->pmu) + return false; + counters++; + } + + /* + * If the group requires more counters than the HW has, it + * cannot ever be scheduled. + */ + return counters <=3D MAC_NUM_COUNTERS; +} + +static int fujitsu_mac__event_init(struct perf_event *event) +{ + struct mac_pmu *macpmu =3D to_mac_pmu(event->pmu); + struct hw_perf_event *hwc =3D &event->hw; + + /* Is the event for this PMU? */ + if (event->attr.type !=3D event->pmu->type) + return -ENOENT; + + /* + * Sampling not supported since these events are not + * core-attributable. + */ + if (hwc->sample_period) + return -EINVAL; + + /* + * Task mode not available, we run the counters as socket counters, + * not attributable to any CPU and therefore cannot attribute per-task. + */ + if (event->cpu < 0) + return -EINVAL; + + /* Validate the group */ + if (!fujitsu_mac__validate_event_group(event)) + return -EINVAL; + + hwc->idx =3D -1; + + /* + * Many perf core operations (eg. events rotation) operate on a + * single CPU context. This is obvious for CPU PMUs, where one + * expects the same sets of events being observed on all CPUs, + * but can lead to issues for off-core PMUs, like this one, where + * each event could be theoretically assigned to a different CPU. + * To mitigate this, we enforce CPU assignment to one designated + * processor (the one described in the "cpumask" attribute exported + * by the PMU device). perf user space tools honor this and avoid + * opening more than one copy of the events. + */ + event->cpu =3D cpumask_first(&macpmu->cpumask); + + return 0; +} + +static void fujitsu_mac__event_start(struct perf_event *event, int flags) +{ + struct hw_perf_event *hwc =3D &event->hw; + + hwc->state =3D 0; + fujitsu_mac_counter_start(event); +} + +static void fujitsu_mac__event_stop(struct perf_event *event, int flags) +{ + struct hw_perf_event *hwc =3D &event->hw; + + if (hwc->state & PERF_HES_STOPPED) + return; + + fujitsu_mac_counter_stop(event, flags); + if (flags & PERF_EF_UPDATE) + fujitsu_mac_counter_update(event); + hwc->state |=3D PERF_HES_STOPPED | PERF_HES_UPTODATE; +} + +static int fujitsu_mac__event_add(struct perf_event *event, int flags) +{ + struct mac_pmu *macpmu =3D to_mac_pmu(event->pmu); + struct hw_perf_event *hwc =3D &event->hw; + int idx; + + /* Try to allocate a counter. */ + idx =3D bitmap_find_free_region(macpmu->used_mask, MAC_NUM_COUNTERS, 0); + if (idx < 0) + /* The counters are all in use. */ + return -EAGAIN; + + hwc->idx =3D idx; + hwc->state =3D PERF_HES_STOPPED | PERF_HES_UPTODATE; + macpmu->events[idx] =3D event; + + if (flags & PERF_EF_START) + fujitsu_mac__event_start(event, 0); + + /* Propagate changes to the userspace mapping. */ + perf_event_update_userpage(event); + + return 0; +} + +static void fujitsu_mac__event_del(struct perf_event *event, int flags) +{ + struct mac_pmu *macpmu =3D to_mac_pmu(event->pmu); + struct hw_perf_event *hwc =3D &event->hw; + + /* Stop and clean up */ + fujitsu_mac__event_stop(event, flags | PERF_EF_UPDATE); + macpmu->events[hwc->idx] =3D NULL; + bitmap_release_region(macpmu->used_mask, hwc->idx, 0); + + /* Propagate changes to the userspace mapping. */ + perf_event_update_userpage(event); +} + +static void fujitsu_mac__event_read(struct perf_event *event) +{ + fujitsu_mac_counter_update(event); +} + +#define MAC_PMU_FORMAT_ATTR(_name, _config) \ + (&((struct dev_ext_attribute[]) { \ + { .attr =3D __ATTR(_name, 0444, device_show_string, NULL), \ + .var =3D (void *) _config, } \ + })[0].attr.attr) + +static struct attribute *fujitsu_mac_pmu_formats[] =3D { + MAC_PMU_FORMAT_ATTR(event, "config:0-7"), + NULL +}; + +static const struct attribute_group fujitsu_mac_pmu_format_group =3D { + .name =3D "format", + .attrs =3D fujitsu_mac_pmu_formats, +}; + +static ssize_t mac_pmu_event_show(struct device *dev, + struct device_attribute *attr, char *page) +{ + struct perf_pmu_events_attr *pmu_attr; + + pmu_attr =3D container_of(attr, struct perf_pmu_events_attr, attr); + return sysfs_emit(page, "event=3D0x%02llx\n", pmu_attr->id); +} + +#define MAC_EVENT_ATTR(_name, _id) \ + PMU_EVENT_ATTR_ID(_name, mac_pmu_event_show, _id) + +static struct attribute *fujitsu_mac_pmu_events[] =3D { + MAC_EVENT_ATTR(cycles, MAC_EVENT_CYCLES), + MAC_EVENT_ATTR(read-count, MAC_EVENT_READ_COUNT), + MAC_EVENT_ATTR(read-count-request, MAC_EVENT_READ_COUNT_REQUEST), + MAC_EVENT_ATTR(read-count-return, MAC_EVENT_READ_COUNT_RETURN), + MAC_EVENT_ATTR(read-count-request-pftgt, MAC_EVENT_READ_COUNT_REQUEST_PFT= GT), + MAC_EVENT_ATTR(read-count-request-normal, MAC_EVENT_READ_COUNT_REQUEST_NO= RMAL), + MAC_EVENT_ATTR(read-count-return-pftgt-hit, MAC_EVENT_READ_COUNT_RETURN_P= FTGT_HIT), + MAC_EVENT_ATTR(read-count-return-pftgt-miss, MAC_EVENT_READ_COUNT_RETURN_= PFTGT_MISS), + MAC_EVENT_ATTR(read-wait, MAC_EVENT_READ_WAIT), + MAC_EVENT_ATTR(write-count, MAC_EVENT_WRITE_COUNT), + MAC_EVENT_ATTR(write-count-write, MAC_EVENT_WRITE_COUNT_WRITE), + MAC_EVENT_ATTR(write-count-pwrite, MAC_EVENT_WRITE_COUNT_PWRITE), + MAC_EVENT_ATTR(memory-read-count, MAC_EVENT_MEMORY_READ_COUNT), + MAC_EVENT_ATTR(memory-write-count, MAC_EVENT_MEMORY_WRITE_COUNT), + MAC_EVENT_ATTR(memory-pwrite-count, MAC_EVENT_MEMORY_PWRITE_COUNT), + MAC_EVENT_ATTR(ea-mac, MAC_EVENT_EA_MAC), + MAC_EVENT_ATTR(ea-memory, MAC_EVENT_EA_MEMORY), + MAC_EVENT_ATTR(ea-memory-mac-write, MAC_EVENT_EA_MEMORY_MAC_WRITE), + MAC_EVENT_ATTR(ea-ha, MAC_EVENT_EA_HA), + NULL +}; + +static const struct attribute_group fujitsu_mac_pmu_events_group =3D { + .name =3D "events", + .attrs =3D fujitsu_mac_pmu_events, +}; + +static ssize_t cpumask_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct mac_pmu *macpmu =3D to_mac_pmu(dev_get_drvdata(dev)); + + return cpumap_print_to_pagebuf(true, buf, &macpmu->cpumask); +} +static DEVICE_ATTR_RO(cpumask); + +static struct attribute *fujitsu_mac_pmu_cpumask_attrs[] =3D { + &dev_attr_cpumask.attr, + NULL +}; + +static const struct attribute_group fujitsu_mac_pmu_cpumask_attr_group =3D= { + .attrs =3D fujitsu_mac_pmu_cpumask_attrs, +}; + +static const struct attribute_group *fujitsu_mac_pmu_attr_grps[] =3D { + &fujitsu_mac_pmu_format_group, + &fujitsu_mac_pmu_events_group, + &fujitsu_mac_pmu_cpumask_attr_group, + NULL +}; + +static int fujitsu_mac_pmu_online_cpu(unsigned int cpu, struct hlist_node = *node) +{ + struct mac_pmu *macpmu =3D hlist_entry_safe(node, struct mac_pmu, node); + + /* If there is not a CPU/PMU association pick this CPU */ + if (cpumask_empty(&macpmu->cpumask)) + cpumask_set_cpu(cpu, &macpmu->cpumask); + + return 0; +} + +static int fujitsu_mac_pmu_offline_cpu(unsigned int cpu, struct hlist_node= *node) +{ + struct mac_pmu *macpmu =3D hlist_entry_safe(node, struct mac_pmu, node); + unsigned int target; + + if (!cpumask_test_and_clear_cpu(cpu, &macpmu->cpumask)) + return 0; + + target =3D cpumask_any_but(cpu_online_mask, cpu); + if (target >=3D nr_cpu_ids) + return 0; + + perf_pmu_migrate_context(&macpmu->pmu, cpu, target); + cpumask_set_cpu(target, &macpmu->cpumask); + + return 0; +} + +static int fujitsu_mac_pmu_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct acpi_device *acpi_dev; + struct mac_pmu *macpmu; + struct resource *memrc; + char *name; + int ret; + u64 uid; + + acpi_dev =3D ACPI_COMPANION(dev); + if (!acpi_dev) + return -ENODEV; + + ret =3D acpi_dev_uid_to_integer(acpi_dev, &uid); + if (ret) + return dev_err_probe(dev, ret, "unable to read ACPI uid\n"); + + macpmu =3D devm_kzalloc(dev, sizeof(*macpmu), GFP_KERNEL); + if (!macpmu) + return -ENOMEM; + + name =3D devm_kasprintf(dev, GFP_KERNEL, "mac_iod%llu_mac%llu_ch%llu", + (uid >> 8) & 0xF, (uid >> 4) & 0xF, uid & 0xF); + if (!name) + return -ENOMEM; + + macpmu->pmu =3D (struct pmu) { + .parent =3D dev, + .task_ctx_nr =3D perf_invalid_context, + + .pmu_enable =3D fujitsu_mac__pmu_enable, + .pmu_disable =3D fujitsu_mac__pmu_disable, + .event_init =3D fujitsu_mac__event_init, + .add =3D fujitsu_mac__event_add, + .del =3D fujitsu_mac__event_del, + .start =3D fujitsu_mac__event_start, + .stop =3D fujitsu_mac__event_stop, + .read =3D fujitsu_mac__event_read, + + .attr_groups =3D fujitsu_mac_pmu_attr_grps, + .capabilities =3D PERF_PMU_CAP_NO_EXCLUDE | PERF_PMU_CAP_NO_INTERRUPT, + }; + + macpmu->regs =3D devm_platform_get_and_ioremap_resource(pdev, 0, &memrc); + if (IS_ERR(macpmu->regs)) + return PTR_ERR(macpmu->regs); + + fujitsu_mac__init(macpmu); + + ret =3D platform_get_irq(pdev, 0); + if (ret < 0) + return ret; + + ret =3D devm_request_irq(dev, ret, fujitsu_mac__handle_irq, 0, + name, macpmu); + if (ret) + return dev_err_probe(dev, ret, "Request for IRQ failed for slice @%pa\n", + &memrc->start); + + /* Add this instance to the list used by the offline callback */ + ret =3D cpuhp_state_add_instance(mac_pmu_cpuhp_state, &macpmu->node); + if (ret) + return dev_err_probe(dev, ret, "Error registering hotplug"); + + ret =3D perf_pmu_register(&macpmu->pmu, name, -1); + if (ret < 0) + return dev_err_probe(dev, ret, "Failed to register MAC PMU\n"); + + dev_dbg(dev, "Registered %s, type: %d\n", name, macpmu->pmu.type); + + return 0; +} + +static const struct acpi_device_id fujitsu_mac_pmu_acpi_match[] =3D { + { "FUJI200C", }, + { } +}; +MODULE_DEVICE_TABLE(acpi, fujitsu_mac_pmu_acpi_match); + +static struct platform_driver fujitsu_mac_pmu_driver =3D { + .driver =3D { + .name =3D "fujitsu-mac-pmu", + .acpi_match_table =3D fujitsu_mac_pmu_acpi_match, + .suppress_bind_attrs =3D true, + }, + .probe =3D fujitsu_mac_pmu_probe, +}; + +static int __init register_fujitsu_mac_pmu_driver(void) +{ + int ret; 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Fri, 15 Aug 2025 03:48:34 +0000 (UTC) Received: from az2nlsmom1.o.css.fujitsu.com (az2nlsmom1.o.css.fujitsu.com [10.150.26.198]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by az2nlsmgm2.o.css.fujitsu.com (Postfix) with ESMTPS id AC8641C01DE7; Fri, 15 Aug 2025 03:48:33 +0000 (UTC) Received: from sm-arm-grace07.ssoft.mng.com (sm-x86-stp01.soft.fujitsu.com [10.124.178.20]) by az2nlsmom1.o.css.fujitsu.com (Postfix) with ESMTP id 250C8829190; Fri, 15 Aug 2025 03:48:25 +0000 (UTC) From: Koichi Okuno To: Will Deacon , Mark Rutland , Jonathan Corbet , Catalin Marinas , Gowthami Thiagarajan , Linu Cherian , Robin Murphy , linux-arm-kernel@lists.infradead.org, Bjorn Andersson , Geert Uytterhoeven , Krzysztof Kozlowski , Konrad Dybcio , Neil Armstrong , Arnd Bergmann , =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= , Thomas Gleixner , Peter Zijlstra , Jonathan Cameron , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, Koichi Okuno Subject: [PATCH v7 2/2] perf: Fujitsu: Add the Uncore PCI PMU driver Date: Fri, 15 Aug 2025 12:47:29 +0900 Message-ID: <20250815034751.3726963-3-fj2767dz@fujitsu.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250815034751.3726963-1-fj2767dz@fujitsu.com> References: <20250815034751.3726963-1-fj2767dz@fujitsu.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds a new dynamic PMU to the Perf Events framework to program and control the Uncore PCI PMUs in Fujitsu chips. This driver was created with reference to drivers/perf/qcom_l3_pmu.c. This driver exports formatting and event information to sysfs so it can be used by the perf user space tools with the syntaxes: perf stat -e pci_iod0_pci0/ea-pci/ ls perf stat -e pci_iod0_pci0/event=3D0x80/ ls FUJITSU-MONAKA PMU Events Specification v1.1 URL: https://github.com/fujitsu/FUJITSU-MONAKA Signed-off-by: Koichi Okuno Reviewed-by: Jonathan Cameron --- .../admin-guide/perf/fujitsu_pci_pmu.rst | 50 ++ Documentation/admin-guide/perf/index.rst | 1 + drivers/perf/Kconfig | 9 + drivers/perf/Makefile | 1 + drivers/perf/fujitsu_pci_pmu.c | 536 ++++++++++++++++++ 5 files changed, 597 insertions(+) create mode 100644 Documentation/admin-guide/perf/fujitsu_pci_pmu.rst create mode 100644 drivers/perf/fujitsu_pci_pmu.c diff --git a/Documentation/admin-guide/perf/fujitsu_pci_pmu.rst b/Documenta= tion/admin-guide/perf/fujitsu_pci_pmu.rst new file mode 100644 index 000000000000..117cefc4d185 --- /dev/null +++ b/Documentation/admin-guide/perf/fujitsu_pci_pmu.rst @@ -0,0 +1,50 @@ +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D +Fujitsu Uncore PCI Performance Monitoring Unit (PMU) +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D + +This driver supports the Uncore PCI PMUs found in Fujitsu chips. +Each PCI PMU on these chips is exposed as a uncore perf PMU with device na= me +pci_iod_pci. + +The driver provides a description of its available events and configuration +options in sysfs, see /sys/bus/event_sources/devices/pci_iod_pci= /. +This driver exports: +- formats, used by perf user space and other tools to configure events +- events, used by perf user space and other tools to create events + symbolically, e.g.: + perf stat -a -e pci_iod0_pci0/event=3D0x24/ ls +- cpumask, used by perf user space and other tools to know on which CPUs + to open the events + +This driver supports the following events: +- pci-port0-cycles + This event counts PCI cycles at PCI frequency in port0. +- pci-port0-read-count + This event counts read transactions for data transfer in port0. +- pci-port0-read-count-bus + This event counts read transactions for bus usage in port0. +- pci-port0-write-count + This event counts write transactions for data transfer in port0. +- pci-port0-write-count-bus + This event counts write transactions for bus usage in port0. +- pci-port1-cycles + This event counts PCI cycles at PCI frequency in port1. +- pci-port1-read-count + This event counts read transactions for data transfer in port1. +- pci-port1-read-count-bus + This event counts read transactions for bus usage in port1. +- pci-port1-write-count + This event counts write transactions for data transfer in port1. +- pci-port1-write-count-bus + This event counts write transactions for bus usage in port1. +- ea-pci + This event counts energy consumption of PCI. + + 'ea' is the abbreviation for 'Energy Analyzer'. + +Examples for use with perf:: + + perf stat -e pci_iod0_pci0/ea-pci/ ls + +Given that these are uncore PMUs the driver does not support sampling, the= refore +"perf record" will not work. Per-task perf sessions are not supported. diff --git a/Documentation/admin-guide/perf/index.rst b/Documentation/admin= -guide/perf/index.rst index e0262060db17..50cc039ad702 100644 --- a/Documentation/admin-guide/perf/index.rst +++ b/Documentation/admin-guide/perf/index.rst @@ -30,3 +30,4 @@ Performance monitor support ampere_cspmu mrvl-pem-pmu fujitsu_mac_pmu + fujitsu_pci_pmu diff --git a/drivers/perf/Kconfig b/drivers/perf/Kconfig index ab4e44c99a53..3d86710d9c73 100644 --- a/drivers/perf/Kconfig +++ b/drivers/perf/Kconfig @@ -187,6 +187,15 @@ config FUJITSU_MAC_PMU Adds the Uncore MAC PMU into the perf events subsystem for monitoring Uncore MAC events. =20 +config FUJITSU_PCI_PMU + bool "Fujitsu Uncore PCI PMU" + depends on (ARM64 && (ACPI || COMPILE_TEST)) + help + Provides support for the Uncore PCI performance monitor unit (PMU) + in Fujitsu processors. + Adds the Uncore PCI PMU into the perf events subsystem for + monitoring Uncore PCI events. + config QCOM_L2_PMU bool "Qualcomm Technologies L2-cache PMU" depends on ARCH_QCOM && ARM64 && ACPI diff --git a/drivers/perf/Makefile b/drivers/perf/Makefile index be7f74c3b14c..6d4a33cd8211 100644 --- a/drivers/perf/Makefile +++ b/drivers/perf/Makefile @@ -15,6 +15,7 @@ obj-$(CONFIG_FSL_IMX8_DDR_PMU) +=3D fsl_imx8_ddr_perf.o obj-$(CONFIG_FSL_IMX9_DDR_PMU) +=3D fsl_imx9_ddr_perf.o obj-$(CONFIG_HISI_PMU) +=3D hisilicon/ obj-$(CONFIG_FUJITSU_MAC_PMU) +=3D fujitsu_mac_pmu.o +obj-$(CONFIG_FUJITSU_PCI_PMU) +=3D fujitsu_pci_pmu.o obj-$(CONFIG_QCOM_L2_PMU) +=3D qcom_l2_pmu.o obj-$(CONFIG_QCOM_L3_PMU) +=3D qcom_l3_pmu.o obj-$(CONFIG_RISCV_PMU) +=3D riscv_pmu.o diff --git a/drivers/perf/fujitsu_pci_pmu.c b/drivers/perf/fujitsu_pci_pmu.c new file mode 100644 index 000000000000..dbe050eec711 --- /dev/null +++ b/drivers/perf/fujitsu_pci_pmu.c @@ -0,0 +1,536 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Driver for the Uncore PCI PMUs in Fujitsu chips. + * + * See Documentation/admin-guide/perf/fujitsu_pci_pmu.rst for more details. + * + * This driver is based on drivers/perf/qcom_l3_pmu.c + * Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. + * Copyright (c) 2024 Fujitsu. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Number of counters on each PMU */ +#define PCI_NUM_COUNTERS 8 +/* Mask for the event type field within perf_event_attr.config and EVTYPE = reg */ +#define PCI_EVTYPE_MASK 0xFF + +/* Perfmon registers */ +#define PCI_PM_EVCNTR(__cntr) (0x000 + (__cntr) * 8) +#define PCI_PM_CNTCTL(__cntr) (0x100 + (__cntr) * 8) +#define PCI_PM_CNTCTL_RESET 0 +#define PCI_PM_EVTYPE(__cntr) (0x200 + (__cntr) * 8) +#define PCI_PM_EVTYPE_EVSEL(__val) FIELD_GET(PCI_EVTYPE_MASK, __val) +#define PCI_PM_CR 0x400 +#define PCI_PM_CR_RESET BIT(1) +#define PCI_PM_CR_ENABLE BIT(0) +#define PCI_PM_CNTENSET 0x410 +#define PCI_PM_CNTENSET_IDX(__cntr) BIT(__cntr) +#define PCI_PM_CNTENCLR 0x418 +#define PCI_PM_CNTENCLR_IDX(__cntr) BIT(__cntr) +#define PCI_PM_CNTENCLR_RESET 0xFF +#define PCI_PM_INTENSET 0x420 +#define PCI_PM_INTENSET_IDX(__cntr) BIT(__cntr) +#define PCI_PM_INTENCLR 0x428 +#define PCI_PM_INTENCLR_IDX(__cntr) BIT(__cntr) +#define PCI_PM_INTENCLR_RESET 0xFF +#define PCI_PM_OVSR 0x440 +#define PCI_PM_OVSR_OVSRCLR_RESET 0xFF + +#define PCI_EVENT_PORT0_CYCLES 0x000 +#define PCI_EVENT_PORT0_READ_COUNT 0x010 +#define PCI_EVENT_PORT0_READ_COUNT_BUS 0x014 +#define PCI_EVENT_PORT0_WRITE_COUNT 0x020 +#define PCI_EVENT_PORT0_WRITE_COUNT_BUS 0x024 +#define PCI_EVENT_PORT1_CYCLES 0x040 +#define PCI_EVENT_PORT1_READ_COUNT 0x050 +#define PCI_EVENT_PORT1_READ_COUNT_BUS 0x054 +#define PCI_EVENT_PORT1_WRITE_COUNT 0x060 +#define PCI_EVENT_PORT1_WRITE_COUNT_BUS 0x064 +#define PCI_EVENT_EA_PCI 0x080 + +struct pci_pmu { + struct pmu pmu; + struct hlist_node node; + void __iomem *regs; + struct perf_event *events[PCI_NUM_COUNTERS]; + unsigned long used_mask[BITS_TO_LONGS(PCI_NUM_COUNTERS)]; + cpumask_t cpumask; +}; + +static int pci_pmu_cpuhp_state; + +#define to_pci_pmu(p) (container_of(p, struct pci_pmu, pmu)) + +static void fujitsu_pci_counter_start(struct perf_event *event) +{ + struct pci_pmu *pcipmu =3D to_pci_pmu(event->pmu); + int idx =3D event->hw.idx; + + /* Initialize the hardware counter and reset prev_count*/ + local64_set(&event->hw.prev_count, 0); + writeq_relaxed(0, pcipmu->regs + PCI_PM_EVCNTR(idx)); + + /* Set the event type */ + writeq_relaxed(PCI_PM_EVTYPE_EVSEL(event->attr.config), pcipmu->regs + PC= I_PM_EVTYPE(idx)); + + /* Enable interrupt generation by this counter */ + writeq_relaxed(PCI_PM_INTENSET_IDX(idx), pcipmu->regs + PCI_PM_INTENSET); + + /* Finally, enable the counter */ + writeq_relaxed(PCI_PM_CNTCTL_RESET, pcipmu->regs + PCI_PM_CNTCTL(idx)); + writeq_relaxed(PCI_PM_CNTENSET_IDX(idx), pcipmu->regs + PCI_PM_CNTENSET); +} + +static void fujitsu_pci_counter_stop(struct perf_event *event, + int flags) +{ + struct pci_pmu *pcipmu =3D to_pci_pmu(event->pmu); + int idx =3D event->hw.idx; + + /* Disable the counter */ + writeq_relaxed(PCI_PM_CNTENCLR_IDX(idx), pcipmu->regs + PCI_PM_CNTENCLR); + + /* Disable interrupt generation by this counter */ + writeq_relaxed(PCI_PM_INTENCLR_IDX(idx), pcipmu->regs + PCI_PM_INTENCLR); +} + +static void fujitsu_pci_counter_update(struct perf_event *event) +{ + struct pci_pmu *pcipmu =3D to_pci_pmu(event->pmu); + int idx =3D event->hw.idx; + u64 prev, new; + + do { + prev =3D local64_read(&event->hw.prev_count); + new =3D readq_relaxed(pcipmu->regs + PCI_PM_EVCNTR(idx)); + } while (local64_cmpxchg(&event->hw.prev_count, prev, new) !=3D prev); + + local64_add(new - prev, &event->count); +} + +static inline void fujitsu_pci__init(struct pci_pmu *pcipmu) +{ + int i; + + writeq_relaxed(PCI_PM_CR_RESET, pcipmu->regs + PCI_PM_CR); + + writeq_relaxed(PCI_PM_CNTENCLR_RESET, pcipmu->regs + PCI_PM_CNTENCLR); + writeq_relaxed(PCI_PM_INTENCLR_RESET, pcipmu->regs + PCI_PM_INTENCLR); + writeq_relaxed(PCI_PM_OVSR_OVSRCLR_RESET, pcipmu->regs + PCI_PM_OVSR); + + for (i =3D 0; i < PCI_NUM_COUNTERS; ++i) { + writeq_relaxed(PCI_PM_CNTCTL_RESET, pcipmu->regs + PCI_PM_CNTCTL(i)); + writeq_relaxed(PCI_PM_EVTYPE_EVSEL(0), pcipmu->regs + PCI_PM_EVTYPE(i)); + } + + /* + * Use writeq here to ensure all programming commands are done + * before proceeding + */ + writeq(PCI_PM_CR_ENABLE, pcipmu->regs + PCI_PM_CR); +} + +static irqreturn_t fujitsu_pci__handle_irq(int irq_num, void *data) +{ + struct pci_pmu *pcipmu =3D data; + /* Read the overflow status register */ + long status =3D readq_relaxed(pcipmu->regs + PCI_PM_OVSR); + int idx; + + if (status =3D=3D 0) + return IRQ_NONE; + + /* Clear the bits we read on the overflow status register */ + writeq_relaxed(status, pcipmu->regs + PCI_PM_OVSR); + + for_each_set_bit(idx, &status, PCI_NUM_COUNTERS) { + struct perf_event *event; + + event =3D pcipmu->events[idx]; + if (!event) + continue; + + fujitsu_pci_counter_update(event); + } + + return IRQ_HANDLED; +} + +static void fujitsu_pci__pmu_enable(struct pmu *pmu) +{ + struct pci_pmu *pcipmu =3D to_pci_pmu(pmu); + + /* Ensure the other programming commands are observed before enabling */ + wmb(); + + writeq_relaxed(PCI_PM_CR_ENABLE, pcipmu->regs + PCI_PM_CR); +} + +static void fujitsu_pci__pmu_disable(struct pmu *pmu) +{ + struct pci_pmu *pcipmu =3D to_pci_pmu(pmu); + + writeq_relaxed(0, pcipmu->regs + PCI_PM_CR); + + /* Ensure the basic counter unit is stopped before proceeding */ + wmb(); +} + +/* + * We must NOT create groups containing events from multiple hardware PMUs, + * although mixing different software and hardware PMUs is allowed. + */ +static bool fujitsu_pci__validate_event_group(struct perf_event *event) +{ + struct perf_event *leader =3D event->group_leader; + struct perf_event *sibling; + int counters; + + if (leader->pmu !=3D event->pmu && !is_software_event(leader)) + return false; + + /* The sum of the counters used by the event and its leader event */ + counters =3D 2; + + for_each_sibling_event(sibling, leader) { + if (is_software_event(sibling)) + continue; + if (sibling->pmu !=3D event->pmu) + return false; + counters++; + } + + /* + * If the group requires more counters than the HW has, it + * cannot ever be scheduled. + */ + return counters <=3D PCI_NUM_COUNTERS; +} + +static int fujitsu_pci__event_init(struct perf_event *event) +{ + struct pci_pmu *pcipmu =3D to_pci_pmu(event->pmu); + struct hw_perf_event *hwc =3D &event->hw; + + /* Is the event for this PMU? */ + if (event->attr.type !=3D event->pmu->type) + return -ENOENT; + + /* + * Sampling not supported since these events are not + * core-attributable. + */ + if (hwc->sample_period) + return -EINVAL; + + /* + * Task mode not available, we run the counters as socket counters, + * not attributable to any CPU and therefore cannot attribute per-task. + */ + if (event->cpu < 0) + return -EINVAL; + + /* Validate the group */ + if (!fujitsu_pci__validate_event_group(event)) + return -EINVAL; + + hwc->idx =3D -1; + + /* + * Many perf core operations (eg. events rotation) operate on a + * single CPU context. This is obvious for CPU PMUs, where one + * expects the same sets of events being observed on all CPUs, + * but can lead to issues for off-core PMUs, like this one, where + * each event could be theoretically assigned to a different CPU. + * To mitigate this, we enforce CPU assignment to one designated + * processor (the one described in the "cpumask" attribute exported + * by the PMU device). perf user space tools honor this and avoid + * opening more than one copy of the events. + */ + event->cpu =3D cpumask_first(&pcipmu->cpumask); + + return 0; +} + +static void fujitsu_pci__event_start(struct perf_event *event, int flags) +{ + struct hw_perf_event *hwc =3D &event->hw; + + hwc->state =3D 0; + fujitsu_pci_counter_start(event); +} + +static void fujitsu_pci__event_stop(struct perf_event *event, int flags) +{ + struct hw_perf_event *hwc =3D &event->hw; + + if (hwc->state & PERF_HES_STOPPED) + return; + + fujitsu_pci_counter_stop(event, flags); + if (flags & PERF_EF_UPDATE) + fujitsu_pci_counter_update(event); + hwc->state |=3D PERF_HES_STOPPED | PERF_HES_UPTODATE; +} + +static int fujitsu_pci__event_add(struct perf_event *event, int flags) +{ + struct pci_pmu *pcipmu =3D to_pci_pmu(event->pmu); + struct hw_perf_event *hwc =3D &event->hw; + int idx; + + /* Try to allocate a counter. */ + idx =3D bitmap_find_free_region(pcipmu->used_mask, PCI_NUM_COUNTERS, 0); + if (idx < 0) + /* The counters are all in use. */ + return -EAGAIN; + + hwc->idx =3D idx; + hwc->state =3D PERF_HES_STOPPED | PERF_HES_UPTODATE; + pcipmu->events[idx] =3D event; + + if (flags & PERF_EF_START) + fujitsu_pci__event_start(event, 0); + + /* Propagate changes to the userspace mapping. */ + perf_event_update_userpage(event); + + return 0; +} + +static void fujitsu_pci__event_del(struct perf_event *event, int flags) +{ + struct pci_pmu *pcipmu =3D to_pci_pmu(event->pmu); + struct hw_perf_event *hwc =3D &event->hw; + + /* Stop and clean up */ + fujitsu_pci__event_stop(event, flags | PERF_EF_UPDATE); + pcipmu->events[hwc->idx] =3D NULL; + bitmap_release_region(pcipmu->used_mask, hwc->idx, 0); + + /* Propagate changes to the userspace mapping. */ + perf_event_update_userpage(event); +} + +static void fujitsu_pci__event_read(struct perf_event *event) +{ + fujitsu_pci_counter_update(event); +} + +#define PCI_PMU_FORMAT_ATTR(_name, _config) \ + (&((struct dev_ext_attribute[]) { \ + { .attr =3D __ATTR(_name, 0444, device_show_string, NULL), \ + .var =3D (void *) _config, } \ + })[0].attr.attr) + +static struct attribute *fujitsu_pci_pmu_formats[] =3D { + PCI_PMU_FORMAT_ATTR(event, "config:0-7"), + NULL +}; + +static const struct attribute_group fujitsu_pci_pmu_format_group =3D { + .name =3D "format", + .attrs =3D fujitsu_pci_pmu_formats, +}; + +static ssize_t pci_pmu_event_show(struct device *dev, + struct device_attribute *attr, char *page) +{ + struct perf_pmu_events_attr *pmu_attr; + + pmu_attr =3D container_of(attr, struct perf_pmu_events_attr, attr); + return sysfs_emit(page, "event=3D0x%02llx\n", pmu_attr->id); +} + +#define PCI_EVENT_ATTR(_name, _id) \ + PMU_EVENT_ATTR_ID(_name, pci_pmu_event_show, _id) + +static struct attribute *fujitsu_pci_pmu_events[] =3D { + PCI_EVENT_ATTR(pci-port0-cycles, PCI_EVENT_PORT0_CYCLES), + PCI_EVENT_ATTR(pci-port0-read-count, PCI_EVENT_PORT0_READ_COUNT), + PCI_EVENT_ATTR(pci-port0-read-count-bus, PCI_EVENT_PORT0_READ_COUNT_BUS), + PCI_EVENT_ATTR(pci-port0-write-count, PCI_EVENT_PORT0_WRITE_COUNT), + PCI_EVENT_ATTR(pci-port0-write-count-bus, PCI_EVENT_PORT0_WRITE_COUNT_BUS= ), + PCI_EVENT_ATTR(pci-port1-cycles, PCI_EVENT_PORT1_CYCLES), + PCI_EVENT_ATTR(pci-port1-read-count, PCI_EVENT_PORT1_READ_COUNT), + PCI_EVENT_ATTR(pci-port1-read-count-bus, PCI_EVENT_PORT1_READ_COUNT_BUS), + PCI_EVENT_ATTR(pci-port1-write-count, PCI_EVENT_PORT1_WRITE_COUNT), + PCI_EVENT_ATTR(pci-port1-write-count-bus, PCI_EVENT_PORT1_WRITE_COUNT_BUS= ), + PCI_EVENT_ATTR(ea-pci, PCI_EVENT_EA_PCI), + NULL +}; + +static const struct attribute_group fujitsu_pci_pmu_events_group =3D { + .name =3D "events", + .attrs =3D fujitsu_pci_pmu_events, +}; + +static ssize_t cpumask_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct pci_pmu *pcipmu =3D to_pci_pmu(dev_get_drvdata(dev)); + + return cpumap_print_to_pagebuf(true, buf, &pcipmu->cpumask); +} +static DEVICE_ATTR_RO(cpumask); + +static struct attribute *fujitsu_pci_pmu_cpumask_attrs[] =3D { + &dev_attr_cpumask.attr, + NULL +}; + +static const struct attribute_group fujitsu_pci_pmu_cpumask_attr_group =3D= { + .attrs =3D fujitsu_pci_pmu_cpumask_attrs, +}; + +static const struct attribute_group *fujitsu_pci_pmu_attr_grps[] =3D { + &fujitsu_pci_pmu_format_group, + &fujitsu_pci_pmu_events_group, + &fujitsu_pci_pmu_cpumask_attr_group, + NULL +}; + +static int fujitsu_pci_pmu_online_cpu(unsigned int cpu, struct hlist_node = *node) +{ + struct pci_pmu *pcipmu =3D hlist_entry_safe(node, struct pci_pmu, node); + + /* If there is not a CPU/PMU association pick this CPU */ + if (cpumask_empty(&pcipmu->cpumask)) + cpumask_set_cpu(cpu, &pcipmu->cpumask); + + return 0; +} + +static int fujitsu_pci_pmu_offline_cpu(unsigned int cpu, struct hlist_node= *node) +{ + struct pci_pmu *pcipmu =3D hlist_entry_safe(node, struct pci_pmu, node); + unsigned int target; + + if (!cpumask_test_and_clear_cpu(cpu, &pcipmu->cpumask)) + return 0; + + target =3D cpumask_any_but(cpu_online_mask, cpu); + if (target >=3D nr_cpu_ids) + return 0; + + perf_pmu_migrate_context(&pcipmu->pmu, cpu, target); + cpumask_set_cpu(target, &pcipmu->cpumask); + + return 0; +} + +static int fujitsu_pci_pmu_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct acpi_device *acpi_dev; + struct pci_pmu *pcipmu; + struct resource *memrc; + char *name; + int ret; + u64 uid; + + acpi_dev =3D ACPI_COMPANION(dev); + if (!acpi_dev) + return -ENODEV; + + ret =3D acpi_dev_uid_to_integer(acpi_dev, &uid); + if (ret) + return dev_err_probe(dev, ret, "unable to read ACPI uid\n"); + + pcipmu =3D devm_kzalloc(dev, sizeof(*pcipmu), GFP_KERNEL); + if (!pcipmu) + return -ENOMEM; + + name =3D devm_kasprintf(dev, GFP_KERNEL, "pci_iod%llu_pci%llu", + (uid >> 4) & 0xF, uid & 0xF); + if (!name) + return -ENOMEM; + + pcipmu->pmu =3D (struct pmu) { + .parent =3D dev, + .task_ctx_nr =3D perf_invalid_context, + + .pmu_enable =3D fujitsu_pci__pmu_enable, + .pmu_disable =3D fujitsu_pci__pmu_disable, + .event_init =3D fujitsu_pci__event_init, + .add =3D fujitsu_pci__event_add, + .del =3D fujitsu_pci__event_del, + .start =3D fujitsu_pci__event_start, + .stop =3D fujitsu_pci__event_stop, + .read =3D fujitsu_pci__event_read, + + .attr_groups =3D fujitsu_pci_pmu_attr_grps, + .capabilities =3D PERF_PMU_CAP_NO_EXCLUDE | PERF_PMU_CAP_NO_INTERRUPT, + }; + + pcipmu->regs =3D devm_platform_get_and_ioremap_resource(pdev, 0, &memrc); + if (IS_ERR(pcipmu->regs)) + return PTR_ERR(pcipmu->regs); + + fujitsu_pci__init(pcipmu); + + ret =3D platform_get_irq(pdev, 0); + if (ret < 0) + return ret; + + ret =3D devm_request_irq(dev, ret, fujitsu_pci__handle_irq, 0, + name, pcipmu); + if (ret) + return dev_err_probe(dev, ret, "Request for IRQ failed for slice @%pa\n", + &memrc->start); + + /* Add this instance to the list used by the offline callback */ + ret =3D cpuhp_state_add_instance(pci_pmu_cpuhp_state, &pcipmu->node); + if (ret) + return dev_err_probe(dev, ret, "Error registering hotplug"); + + ret =3D perf_pmu_register(&pcipmu->pmu, name, -1); + if (ret < 0) + return dev_err_probe(dev, ret, "Failed to register PCI PMU\n"); + + dev_dbg(dev, "Registered %s, type: %d\n", name, pcipmu->pmu.type); + + return 0; +} + +static const struct acpi_device_id fujitsu_pci_pmu_acpi_match[] =3D { + { "FUJI200D", }, + { } +}; +MODULE_DEVICE_TABLE(acpi, fujitsu_pci_pmu_acpi_match); + +static struct platform_driver fujitsu_pci_pmu_driver =3D { + .driver =3D { + .name =3D "fujitsu-pci-pmu", + .acpi_match_table =3D fujitsu_pci_pmu_acpi_match, + .suppress_bind_attrs =3D true, + }, + .probe =3D fujitsu_pci_pmu_probe, +}; + +static int __init register_fujitsu_pci_pmu_driver(void) +{ + int ret; + + /* Install a hook to update the reader CPU in case it goes offline */ + ret =3D cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN, + "perf/fujitsu/pci:online", + fujitsu_pci_pmu_online_cpu, + fujitsu_pci_pmu_offline_cpu); + if (ret < 0) + return ret; + + pci_pmu_cpuhp_state =3D ret; + return platform_driver_register(&fujitsu_pci_pmu_driver); +} +device_initcall(register_fujitsu_pci_pmu_driver); --=20 2.43.0