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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250815-mgx4u_devicetree-v1-1-66db6fa5a7e4@nvidia.com> References: <20250815-mgx4u_devicetree-v1-0-66db6fa5a7e4@nvidia.com> In-Reply-To: <20250815-mgx4u_devicetree-v1-0-66db6fa5a7e4@nvidia.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org, Marc Olberding X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1755287229; l=872; i=molberding@nvidia.com; s=20250815; h=from:subject:message-id; bh=bZryK9TBxMPATAVJWuEQPUK/avnzaPB+Qc6/3YZVDH8=; b=6R0Z9B9Y55JMHM14fRJHaqmFb14f0c32ab2ZJnGvvX5Loeddgea99h4VBh5a2VnAZz7C7oOY8 GL6y5ucJJ8bAChY9E2+uVAfpzSXdf72HkiTect1dP2WR/oYxbt5UWtu X-Developer-Key: i=molberding@nvidia.com; a=ed25519; pk=qCpZ1WFEf5YiaL88PDdYhG+A/bKk7rHp7KF2K3GmkH0= X-ClientProxiedBy: MW4P221CA0023.NAMP221.PROD.OUTLOOK.COM (2603:10b6:303:8b::28) To CH1PPFDAD84AB72.namprd12.prod.outlook.com (2603:10b6:61f:fc00::627) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PPFDAD84AB72:EE_|SN7PR12MB6864:EE_ X-MS-Office365-Filtering-Correlation-Id: 0abe8903-755b-446a-8268-08dddc348780 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|376014|1800799024; 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Signed-off-by: Marc Olberding Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml b/Doc= umentation/devicetree/bindings/arm/aspeed/aspeed.yaml index a3736f13413057ed45791bd0bf655030e90ce3e4..b7ee725c3bdbd99b6ac0c8d5184= 648bfe6740921 100644 --- a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml +++ b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml @@ -99,6 +99,7 @@ properties: - inventec,transformer-bmc - jabil,rbp-bmc - nvidia,gb200nvl-bmc + - nvidia,mgx4u - qcom,dc-scm-v1-bmc - quanta,s6q-bmc - ufispace,ncplite-bmc --=20 2.34.1 From nobody Sat Oct 4 12:46:56 2025 Received: from NAM02-DM3-obe.outbound.protection.outlook.com (mail-dm3nam02on2059.outbound.protection.outlook.com [40.107.95.59]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EDB9A29BD93; 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+ reg =3D <0x56>; +}; + +gpio@26 { + compatible =3D "nxp,pca9555"; + reg =3D <0x26>; + gpio-controller; + #gpio-cells =3D <2>; + gpio-line-names =3D "WP_QSPI_CX0", "RST_SEQ_CX0_L", + "BOOT_COMPLT_CX0", "FNP_CX0_L", + "WP_FRU_CX0", "OVT_SHUTDOWN_CX0", + "", "", + "", "", + "TMP_WARNING_CX0", "USB_HUB1_RST_L", + "I2C_SWITCH1_RESET", "MCU1_GPIO", + "MCU1_RST_N", "MCU1_RECOVERY_N"; + +}; + +i2c-mux@72 { + compatible =3D "nxp,pca9546"; + reg =3D <0x72>; + i2c-mux-idle-disconnect; + #address-cells =3D <1>; + #size-cells =3D <0>; + + i2c@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + }; + i2c@1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <1>; + }; + i2c@2 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <2>; + gpio@20 { + reg =3D <0x20>; + gpio-controller; + compatible =3D "nxp,pca6408"; + #gpio-cells =3D <2>; + gpio-line-names =3D "GLOBAL_WP", "OOB_RST_N", + "OOB_RECOVERY", "MCU_RECOVERY_N", + "MCU_RST_N", "MCU_BYPASS_N", + "SMBUS_FRU_EEPROM_WP", ""; + }; + eeprom@50 { + reg =3D <0x50>; + compatible =3D "atmel,24c128"; + }; + }; + i2c@3 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <3>; + gpio@20 { + reg =3D <0x20>; + gpio-controller; + compatible =3D "nxp,pca6408"; + #gpio-cells =3D <2>; + gpio-line-names =3D "GLOBAL_WP", "OOB_RST_N", + "OOB_RECOVERY", "MCU_RECOVERY_N", + "MCU_RST_N", "MCU_BYPASS_N", + "SMBUS_FRU_EEPROM_WP", ""; + }; + eeprom@50 { + reg =3D <0x50>; + compatible =3D "atmel,24c128"; + }; + }; +}; + diff --git a/arch/arm/boot/dts/aspeed/nvidia-mgx-cx8-switch-south.dtsi b/ar= ch/arm/boot/dts/aspeed/nvidia-mgx-cx8-switch-south.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..cc8e71f374e100ba7f977138a21= ea27a83ca36ed --- /dev/null +++ b/arch/arm/boot/dts/aspeed/nvidia-mgx-cx8-switch-south.dtsi @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// Copyright 2025 Nvidia + +eeprom@56 { + compatible =3D "atmel,24c128"; + reg =3D <0x56>; +}; + +gpio@26 { + compatible =3D "nxp,pca9555"; + reg =3D <0x26>; + gpio-controller; + #gpio-cells =3D <2>; + gpio-line-names =3D "WP_QSPI_CX1", "RST_SEQ_CX1_L", + "BOOT_CMPLT_CX1", "FNP_CX1_L", + "WP_FRU_CX1", "OVT_SHUTDOWN_CX1", + "TMP_WARNING_CX1", "USB_HUB2_RST_L", + "I2C_SWITCH2_RESET", "", + "", "", + "", "", + "", ""; +}; + +i2c-mux@72 { + compatible =3D "nxp,pca9546"; + reg =3D <0x72>; + i2c-mux-idle-disconnect; + #address-cells =3D <1>; + #size-cells =3D <0>; + + i2c@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + }; + i2c@1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <1>; + }; + i2c@2 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <2>; + gpio@20 { + reg =3D <0x20>; + gpio-controller; + compatible =3D "nxp,pca6408"; + #gpio-cells =3D <2>; + gpio-line-names =3D "GLOBAL_WP", "OOB_RST_N", + "OOB_RECOVERY", "MCU_RECOVERY_N", + "MCU_RST_N", "MCU_BYPASS_N", + "SMBUS_FRU_EEPROM_WP", ""; + }; + eeprom@50 { + reg =3D <0x50>; + compatible =3D "atmel,24c128"; + }; + }; + i2c@3 { + #address-cells =3D <1>; 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Signed-off-by: Marc Olberding --- arch/arm/boot/dts/aspeed/Makefile | 1 + .../boot/dts/aspeed/aspeed-bmc-nvidia-mgx4u.dts | 1078 ++++++++++++++++= ++++ 2 files changed, 1079 insertions(+) diff --git a/arch/arm/boot/dts/aspeed/Makefile b/arch/arm/boot/dts/aspeed/M= akefile index b3170fdd30969b5b064c5333aea136d3abfcbe72..f150ed0f2e48edb804b0588ef09= 8edb3282b6292 100644 --- a/arch/arm/boot/dts/aspeed/Makefile +++ b/arch/arm/boot/dts/aspeed/Makefile @@ -51,6 +51,7 @@ dtb-$(CONFIG_ARCH_ASPEED) +=3D \ aspeed-bmc-lenovo-hr855xg2.dtb \ aspeed-bmc-microsoft-olympus.dtb \ aspeed-bmc-nvidia-gb200nvl-bmc.dtb \ + aspeed-bmc-nvidia-mgx4u.dtb \ aspeed-bmc-opp-lanyang.dtb \ aspeed-bmc-opp-mowgli.dtb \ aspeed-bmc-opp-nicole.dtb \ diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-mgx4u.dts b/arch/ar= m/boot/dts/aspeed/aspeed-bmc-nvidia-mgx4u.dts new file mode 100644 index 0000000000000000000000000000000000000000..beaf68d5b4bd73ec219a0d2d400= f93cf05b0d34f --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-mgx4u.dts @@ -0,0 +1,1078 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +/dts-v1/; + +#include "aspeed-g6.dtsi" +#include +#include + +/ { + model =3D "MGX4U"; + compatible =3D "nvidia,mgx4u", "aspeed,ast2600"; + + aliases { + serial0 =3D &uart1; + serial1 =3D &uart2; + serial2 =3D &uart3; + serial3 =3D &uart4; + serial4 =3D &uart5; + + i2c16 =3D &i2c5_mux_0; + i2c17 =3D &i2c5_mux_1; + i2c18 =3D &i2c5_mux_2; + i2c19 =3D &i2c5_mux_3; + i2c20 =3D &i2c5_mux_4; + i2c21 =3D &i2c5_mux_5; + i2c22 =3D &i2c5_mux_6; + i2c23 =3D &i2c5_mux_7; + + i2c24 =3D &i2c6_mux_0; + i2c25 =3D &i2c6_mux_1; + i2c26 =3D &i2c6_mux_2; + i2c27 =3D &i2c6_mux_3; + i2c28 =3D &i2c6_mux_4; + i2c29 =3D &i2c6_mux_5; + i2c30 =3D &i2c6_mux_6; + i2c31 =3D &i2c6_mux_7; + + i2c32 =3D &i2c7_1_mux_0; + i2c33 =3D &i2c7_1_mux_1; + i2c35 =3D &i2c7_1_mux_2; + i2c36 =3D &i2c7_1_mux_3; + i2c37 =3D &i2c7_mux_0; + i2c38 =3D &i2c7_mux_1; + i2c39 =3D &i2c7_mux_2; + i2c40 =3D &i2c7_mux_3; + i2c41 =3D &i2c7_mux_4; + i2c42 =3D &i2c7_mux_5; + i2c43 =3D &i2c7_mux_6; + i2c44 =3D &i2c7_mux_7; + + i2c45 =3D &i2c0_mux_0; + i2c46 =3D &i2c0_mux_1; + i2c47 =3D &i2c0_mux_2; + i2c48 =3D &i2c0_mux_3; + i2c49 =3D &i2c0_mux_4; + i2c50 =3D &i2c0_mux_5; + i2c51 =3D &i2c0_mux_6; + i2c52 =3D &i2c0_mux_7; + + i2c53 =3D &i2c0_1_mux_0; + i2c54 =3D &i2c0_1_mux_1; + i2c55 =3D &i2c0_1_mux_2; + i2c56 =3D &i2c0_1_mux_3; + i2c57 =3D &i2c0_1_mux_4; + i2c58 =3D &i2c0_1_mux_5; + i2c59 =3D &i2c0_1_mux_6; + i2c60 =3D &i2c0_1_mux_7; + + i2c61 =3D &i2c3_mux_6; + i2c62 =3D &i2c3_mux_7; + + i2c63 =3D &i2c9_mux_0; + i2c64 =3D &i2c9_mux_1; + i2c65 =3D &i2c9_mux_2; + i2c66 =3D &i2c9_mux_3; + i2c67 =3D &i2c9_mux_4; + i2c68 =3D &i2c9_mux_5; + i2c69 =3D &i2c9_mux_6; + i2c70 =3D &i2c9_mux_7; + }; + + chosen { + bootargs =3D "console=3DttyS4,115200n8"; + }; + + memory@80000000 { + device_type =3D "memory"; + reg =3D <0x80000000 0x80000000>; + }; + + reserved-memory { + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges; + + gfx_memory: framebuffer { + size =3D <0x01000000>; + alignment =3D <0x01000000>; + compatible =3D "shared-dma-pool"; + reusable; + }; + + video_engine_memory: jpegbuffer { + size =3D <0x02000000>; /* 32M */ + alignment =3D <0x01000000>; + compatible =3D "shared-dma-pool"; + reusable; + }; + }; +}; + +&ehci1 { + status =3D "okay"; +}; + +&emmc_controller { + status =3D "okay"; +}; + +&emmc { + non-removable; + bus-width =3D <4>; + max-frequency =3D <100000000>; + clk-phase-mmc-hs200 =3D <9>, <225>; +}; + +&fmc { + status =3D "okay"; + + flash@0 { + status =3D "okay"; + m25p,fast-read; + label =3D "bmc"; + spi-rx-bus-width =3D <4>; + spi-tx-bus-width =3D <4>; + spi-max-frequency =3D <50000000>; +#include "openbmc-flash-layout-128.dtsi" + }; +}; + +&gfx { + memory-region =3D <&gfx_memory>; + status =3D "okay"; +}; + +&gpio0 { + gpio-line-names =3D + /*A0-A7*/ "","","","","","","","", + /*B0-B7*/ "","","","","","","","RST_BMC_8211F_N", + /*C0-C7*/ "","","","","","","","", + /*D0-D7*/ "","","","","","","","", + /*E0-E7*/ "","","","","","","","", + /*F0-F7*/ "","RST_BIOSROM_1_BMC_N","","RST_SPI_PFRM1_R_N","","","SPI_BIOS= _MUX_SEL","", + /*G0-G7*/ "","","","","","","","", + /*H0-H7*/ "","","","","","","","", + /*I0-I7*/ "","","","","","","","", + /*J0-J7*/ "","","","","","","","", + /*K0-K7*/ "","","","","","","","", + /*L0-L7*/ "","","","","","","","", + /*M0-M7*/ "","","","","","","","", + /*N0-N7*/ "","","","","","","","", + /*O0-O7*/ "","","","","","","","", + /*P0-P7*/ "","","","","","","","", + /*Q0-Q7*/ "","","","","","","","", + /*R0-R7*/ "","","","","","","","", + /*S0-S7*/ "","","","","","","","", + /*T0-T7*/ "","","","","","","","", + /*U0-U7*/ "","","","","","","","", + /*V0-V7*/ "","","SCM_HPM_STBY_RST_N","","SCM_HPM_STBY_EN","","","", + /*W0-W7*/ "","","","","","","","", + /*X0-X7*/ "","","","","","","","", + /*Y0-Y7*/ "","","","","","","","", + /*Z0-Z7*/ "","","","","","","",""; + status =3D "okay"; +}; + +&gpio1 { + gpio-line-names =3D + /*18A0-18A7*/ "","","","","","","","", + /*18B0-18B7*/ "","","","","SW_MAIN_EN","HOST_GLOBAL_WP_N","","", + /*18C0-18C7*/ "","","","","","","","", + /*18D0-18D7*/ "","","","","","","","", + /*18E0-18E3*/ "","","",""; + status =3D "okay"; +}; + +&i2c0 { + status =3D "okay"; + + i2c-mux@73 { + compatible =3D "nxp,pca9548"; + reg =3D <0x73>; + #address-cells =3D <1>; + #size-cells =3D <0>; + i2c-mux-idle-disconnect; + + i2c0_mux_0: i2c@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c0_mux_1: i2c@1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <1>; + }; + + i2c0_mux_2: i2c@2 { + reg =3D <2>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c0_mux_3: i2c@3 { + reg =3D <3>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + eeprom@51 { + compatible =3D "atmel,24c02"; + reg =3D <0x51>; + }; + }; + + i2c0_mux_4: i2c@4 { + reg =3D <4>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c0_mux_5: i2c@5 { + reg =3D <5>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c0_mux_6: i2c@6 { + reg =3D <6>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + tmp75@4c { + compatible =3D "ti,tmp75"; + reg =3D <0x4c>; + }; + }; + + i2c0_mux_7: i2c@7 { + reg =3D <7>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; + + i2c-mux@77 { + compatible =3D "nxp,pca9548"; + reg =3D <0x77>; + #address-cells =3D <1>; + #size-cells =3D <0>; + i2c-mux-idle-disconnect; + + i2c0_1_mux_0: i2c@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c0_1_mux_1: i2c@1 { + reg =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c0_1_mux_2: i2c@2 { + reg =3D <2>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c0_1_mux_3: i2c@3 { + reg =3D <3>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c0_1_mux_4: i2c@4 { + reg =3D <4>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c0_1_mux_5: i2c@5 { + reg =3D <5>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c0_1_mux_6: i2c@6 { + reg =3D <6>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c0_1_mux_7: i2c@7 { + reg =3D <7>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; +}; + +&i2c3 { + status =3D "okay"; + + i2c-mux@72 { + compatible =3D "nxp,pca9548"; + reg =3D <0x72>; + #address-cells =3D <1>; + #size-cells =3D <0>; + i2c-mux-idle-disconnect; + + i2c3_mux_6: i2c@6 { + reg =3D <6>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c3_mux_7: i2c@7 { + reg =3D <7>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; +}; + +&i2c4 { + status =3D "okay"; +}; + +&i2c5 { + status =3D "okay"; + + i2c-mux@77 { + compatible =3D "nxp,pca9548"; + reg =3D <0x77>; + #address-cells =3D <1>; + #size-cells =3D <0>; + i2c-mux-idle-disconnect; + + i2c5_mux_0: i2c@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c5_mux_1: i2c@1 { + reg =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c5_mux_2: i2c@2 { + reg =3D <2>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c5_mux_3: i2c@3 { + reg =3D <3>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c5_mux_4: i2c@4 { + reg =3D <4>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c5_mux_5: i2c@5 { + reg =3D <5>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c5_mux_6: i2c@6 { + reg =3D <6>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c5_mux_7: i2c@7 { + reg =3D <7>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; +}; + +&i2c6 { + status =3D "okay"; + + i2c-mux@70 { + reg =3D <0x70>; + compatible =3D "nxp,pca9548"; + #address-cells =3D <1>; + #size-cells =3D <0>; + i2c-mux-idle-disconnect; + + i2c6_mux_0: i2c@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + tmp75@4a { + compatible =3D "ti,tmp75"; + reg =3D <0x4a>; + }; + + tmp75@4b { + compatible =3D "ti,tmp75"; + reg =3D <0x4b>; + }; + + eeprom@51 { + compatible =3D "atmel,24c64"; + reg =3D <0x51>; + pagesize =3D <32>; + }; + }; + + i2c6_mux_1: i2c@1 { + reg =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + /*fan controller 0*/ + max31790@20 { + compatible =3D "maxim,max31790"; + reg =3D <0x20>; + }; + + /*fan controller 1*/ + max31790@21 { + compatible =3D "maxim,max31790"; + reg =3D <0x21>; + }; + + eeprom@57 { + compatible =3D "atmel,24c64"; + reg =3D <0x57>; + pagesize =3D <32>; + }; + + hpmfanio: pca9555@27 { + compatible =3D "nxp,pca9555"; + reg =3D <0x27>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + interrupt-parent =3D <&gpio0>; + interrupts =3D <11 0>; + gpio-line-names =3D + "HPM_FAN1_INSTALL", "HPM_FAN2_INSTALL", + "HPM_FAN3_INSTALL", "HPM_FAN4_INSTALL", + "HPM_FAN5_INSTALL", "", + "",""; + }; + }; + + i2c6_mux_2: i2c@2 { + reg =3D <2>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c6_mux_3: i2c@3 { + reg =3D <3>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + /* 4056 fan board_EEPROM*/ + eeprom@57 { + compatible =3D "atmel,24c64"; + reg =3D <0x57>; + pagesize =3D <32>; + }; + + /*fan controller 0*/ + max31790@20 { + compatible =3D "maxim,max31790"; + reg =3D <0x20>; + }; + /*fan controller 1*/ + max31790@21 { + compatible =3D "maxim,max31790"; + reg =3D <0x21>; + }; + + gpufanio: pca9555@27 { + compatible =3D "nxp,pca9555"; + reg =3D <0x27>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + interrupt-parent =3D <&gpio0>; + interrupts =3D <11 0>; + gpio-line-names =3D + "GPU_FAN1_INSTALL", "GPU_FAN2_INSTALL", + "GPU_FAN3_INSTALL", "GPU_FAN4_INSTALL", + "GPU_FAN5_INSTALL", "", + "",""; + }; + }; + + i2c6_mux_4: i2c@4 { + reg =3D <4>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + /* IO board EEPROM*/ + eeprom@57 { + compatible =3D "atmel,24c64"; + reg =3D <0x57>; + pagesize =3D <32>; + }; + }; + + i2c6_mux_5: i2c@5 { + reg =3D <5>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c6_mux_6: i2c@6 { + reg =3D <6>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c6_mux_7: i2c@7 { + reg =3D <7>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; +}; + +&i2c7 { + multi-master; + status =3D "okay"; + + i2c-mux@70 { + compatible =3D "nxp,pca9548"; + reg =3D <0x70>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + i2c7_mux_0: i2c@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c7_mux_1: i2c@1 { + reg =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + i2c-mux@71 { + compatible =3D "nxp,pca9545"; + reg =3D <0x71>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + i2c7_1_mux_0: i2c@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c7_1_mux_1: i2c@1 { + reg =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + eeprom@55 { + compatible =3D "atmel,24c64"; + reg =3D <0x55>; + pagesize =3D <32>; + }; + + eeprom@50 { + compatible =3D "atmel,24c02"; + reg =3D <0x50>; + pagesize =3D <32>; + }; + + eeprom@53 { + compatible =3D "atmel,24c02"; + reg =3D <0x53>; + pagesize =3D <32>; + }; + }; + + i2c7_1_mux_2: i2c@2 { + reg =3D <2>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c7_1_mux_3: i2c@3 { + reg =3D <3>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; + }; + + i2c7_mux_2: i2c@2 { + reg =3D <2>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c7_mux_3: i2c@3 { + reg =3D <3>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + /* XDPE19284B - CPU0 PVCCIN VR */ + xdpe152c4@60 { + compatible =3D "infineon,xdpe152c4"; + reg =3D <0x60>; + }; + + /* XDPE19284B - CPU0 PVCCFA EHV FIVRA / PVCCINF_VR*/ + xdpe152c4@62 { + compatible =3D "infineon,xdpe152c4"; + reg =3D <0x62>; + }; + + /* XDPE19284B - CPU0 PVCCA EHV PVCCIN VR */ + xdpe152c4@74 { + compatible =3D "infineon,xdpe152c4"; + reg =3D <0x74>; + }; + + /* XDPE19284B - CPU0 PVVCCD0 & D1 VR */ + xdpe152c4@76 { + compatible =3D "infineon,xdpe152c4"; + reg =3D <0x76>; + }; + }; + + i2c7_mux_4: i2c@4 { + reg =3D <4>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + /* XDPE19284B - CPU1 PVCCIN VR */ + xdpe152c4@60 { + compatible =3D "infineon,xdpe152c4"; + reg =3D <0x60>; + }; + + /* XDPE19284B - CPU1 PVCCFA EHV FIVRA / PVCCINF_VR*/ + xdpe152c4@62 { + compatible =3D "infineon,xdpe152c4"; + reg =3D <0x62>; + }; + + /* XDPE19284B - CPU1 PVCCA EHV PVCCIN VR */ + xdpe152c4@74 { + compatible =3D "infineon,xdpe152c4"; + reg =3D <0x74>; + }; + + /* XDPE19284B - CPU1 PVVCCD0 & D1 VR */ + xdpe152c4@76 { + compatible =3D "infineon,xdpe152c4"; + reg =3D <0x76>; + }; + }; + + i2c7_mux_5: i2c@5 { + reg =3D <5>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c7_mux_6: i2c@6 { + reg =3D <6>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c7_mux_7: i2c@7 { + reg =3D <7>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; +}; + +&i2c8 { + status =3D "okay"; +}; + +&i2c9 { + status =3D "okay"; + + i2c-mux@70 { + compatible =3D "nxp,pca9548"; + reg =3D <0x70>; + #address-cells =3D <1>; + #size-cells =3D <0>; + i2c-mux-idle-disconnect; + + i2c9_mux_0: i2c@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; +#include "nvidia-mgx-cx8-switch-north.dtsi" + }; + + i2c9_mux_1: i2c@1 { + reg =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; +#include "nvidia-mgx-cx8-switch-south.dtsi" + }; + + i2c9_mux_2: i2c@2 { + reg =3D <2>; + #address-cells =3D <1>; + #size-cells =3D <0>; +#include "nvidia-mgx-cx8-switch-north.dtsi" + }; + + i2c9_mux_3: i2c@3 { + reg =3D <3>; + #address-cells =3D <1>; + #size-cells =3D <0>; +#include "nvidia-mgx-cx8-switch-south.dtsi" + }; + + i2c9_mux_4: i2c@4 { + reg =3D <4>; + #address-cells =3D <1>; + #size-cells =3D <0>; +#include "nvidia-mgx-cx8-switch-north.dtsi" + }; + + i2c9_mux_5: i2c@5 { + reg =3D <5>; + #address-cells =3D <1>; + #size-cells =3D <0>; +#include "nvidia-mgx-cx8-switch-south.dtsi" + }; + + i2c9_mux_6: i2c@6 { + reg =3D <6>; + #address-cells =3D <1>; + #size-cells =3D <0>; +#include "nvidia-mgx-cx8-switch-north.dtsi" + }; + + i2c9_mux_7: i2c@7 { + reg =3D <7>; + #address-cells =3D <1>; + #size-cells =3D <0>; +#include "nvidia-mgx-cx8-switch-south.dtsi" + }; + }; +}; + +&i2c10 { + status =3D "okay"; + + i2c-mux@70 { + compatible =3D "nxp,pca9548"; + reg =3D <0x70>; + #address-cells =3D <1>; + #size-cells =3D <0>; + i2c-mux-idle-disconnect; + + i2c10_mux_0: i2c@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c10_mux_1: i2c@1 { + reg =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c10_mux_2: i2c@2 { + reg =3D <2>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c10_mux_3: i2c@3 { + reg =3D <3>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c10_mux_4: i2c@4 { + reg =3D <4>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c10_mux_5: i2c@5 { + reg =3D <5>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c10_mux_6: i2c@6 { + reg =3D <6>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c10_mux_7: i2c@7 { + reg =3D <7>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; +}; + +&i2c12 { + status =3D "okay"; + + rtc@6f { + compatible =3D "nuvoton,nct3018y"; + reg =3D <0x6f>; + }; + + eeprom@50 { + compatible =3D "atmel,24c02"; + reg =3D <0x50>; + }; +}; + +&mdio3 { + status =3D "okay"; + + ethphy3: ethernet-phy@0 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <0>; + }; +}; + +&mac2 { + pinctrl-names =3D "default"; + phy-mode =3D "rmii"; + pinctrl-0 =3D <&pinctrl_rmii3_default>; + use-ncsi; + status =3D "okay"; +}; + +&mac3 { + phy-mode =3D "rgmii"; + phy-handle =3D <ðphy3>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_rgmii4_default>; + status =3D "okay"; +}; + +&peci0 { + status =3D "okay"; +}; + +&rtc { + status =3D "okay"; +}; + +&sdc { + status =3D "okay"; +}; + +&sgpiom0 { + ngpios =3D <128>; + gpio-line-names =3D + "","LED_PORT80_0_N", + "","LED_PORT80_1_N", + "","LED_PORT80_2_N", + "","LED_PORT80_3_N", + "","LED_PORT80_4_N", + "","LED_PORT80_5_N", + "","LED_PORT80_6_N", + "","LED_PORT80_7_N", + "","CPLD_JTAG_OE_R_N", + "","RST_PE_SLOT_I2C_MUX_N", + "","ASSERT_CPU0_PROCHOT_N", + "","ASSERT_CPU1_PROCHOT_N", + "","BMC_CPU0_NMI_OUT_N", + "","BMC_CPU1_NMI_OUT_N", + "","CPLD_PWRBRK_N", + "","SPD_SWITCH_CTRL_N", + "","COM_DBG_MODE", + "","RST_CPU0_RTCRST_PLD","", + "EN_MON_VBAT","","BMC_RST_BTN_OUT", + "","BMC_PWR_BTN_OUT", + "","BMC_WAKE", + "","CPU_FRBK_OUT", + "","CPU0_BMC_INIT", + "","CPU1_BMC_INIT", + "","NCSI_BMC_CLK_EN", + "","NCSI_OCP_CLK_EN", + "","IRQ_CPU0_TPM", + "","UART_HPM_MUX", + "","DEBUG_BIT_0","","DEBUG_BIT_1", + "","DEBUG_BIT_2", + "FAN_4056_BOARD_ID_0","DEBUG_BIT_3", + "FAN_4056_BOARD_ID_1","DEBUG_BIT_4", + "FAN_4056_BOARD_ID_2","DEBUG_BIT_5", + "FAN_4056_BOARD_ID_3","DEBUG_BIT_6", + "FAN_8080_BOARD_ID_0","DEBUG_BIT_7", + "FAN_8080_BOARD_ID_1","LED_BMC_HBLED_CPLD_N", + "FAN_8080_BOARD_ID_2","LED_SYS_ALERT_CPLD", + "FAN_8080_BOARD_ID_3","LED_PWR_YEL_CPLD", + "FAN1_FRONT_TOP_INSTALL","", + "FAN2_FRONT_TOP_INSTALL","", + "FAN3_FRONT_TOP_INSTALL","", + "FAN4_FRONT_TOP_INSTALL","", + "FAN5_FRONT_TOP_INSTALL","", + "","", + "","", + "","", + "FAN9_REAR_INSTALL","", + "FAN_FRONT_SW0_FAIL","", + "FAN_REAR_SW0_FAIL","", + "FAN1_FRONT_BOT_INSTALL","", + "FAN2_FRONT_BOT_INSTALL","LED_UID_N", + "FAN3_FRONT_BOT_INSTALL","", + "FAN4_FRONT_BOT_INSTALL","", + "FAN5_FRONT_BOT_INSTALL","SPI_MUX3_EN", + "FAN1_REAR_INSTALL","SPI_MUX2_EN", + "FAN2_REAR_INSTALL","SPI_MUX1_EN", + "FAN3_REAR_INSTALL","SPI_MUX3_SEL", + "FAN4_REAR_INSTALL","SPI_MUX2_SEL", + "FAN5_REAR_INSTALL","SPI_MUX1_SEL", + "FAN6_REAR_INSTALL","PDB_RST", + "FAN7_REAR_INSTALL","PRE_STANDBY_DROP", + "FAN8_REAR_INSTALL","", + "MLB_BRD_SKU_ID0","", + "MLB_BRD_SKU_ID1","", + "MLB_BRD_SKU_ID2","", + "MLB_BRD_SKU_ID3","", + "MLB_BRD_REV_ID0","", + "MLB_BRD_REV_ID1","", + "M2_1_PRESENT","", + "M2_2_PRESENT","", + "M2_1_ALERT","", + "PASSWORD_CLEAR","", + "IRQ_PSYS_CRIT","", + "LEAKAGE_MONITOR_ALERT","", + "M2_2_ALERT","", + "RST_BTN","", + "PWR_BTN","", + "","", + "CPU1_MEM_VRHOT","", + "CPU0_MEM_VRHOT","", + "CPU1_VRHOT","", + "CPU0_VRHOT","", + "RST_PLTRST_MONITOR","", + "CPU_SLP_S3","", + "TPM_PRSNT","", + "HPM_HMC_PCIE_PERST","", + "CPU1_THERMTRIP","", + "CPU0_THERMTRIP","", + "CPU1_PROCHOT_CPLD","", + "CPU0_PROCHOT_CPLD","", + "CPU1_MEMTRIP","", + "CPU0_MEMTRIP","", + "CPU0_MEMHOT","", + "CPU1_MEMHOT","", + "CPU_ERR2","", + "CPU_ERR1","", + "CPU_ERR0","", + "CPU_CATERR","", + "CPU_RMCA","", + "","", + "CPU1_MON_FAIL","", + "CPU0_MON_FAIL","", + "PUS4_PRSNT_N","", + "PUS5_PRSNT_N","", + "PUS6_PRSNT_N","", + "PUS7_PRSNT_N","", + "PUS8_PRSNT_N","", + "PUS9_PRSNT_N","", + "PUS10_PRSNT_N","", + "PUS11_PRSNT_N","", + "PWRGD_CPU1_S0_PWROK","", + "PWRGD_CPU0_S0_PWROK","", + "","", + "PSU_SMBUS_ALERT_N","", + "PSU0_PRSNT_N","", + "PSU1_PRSNT_N","", + "PUS2_PRSNT_N","", + "PUS3_PRSNT_N","", + "CPU0_PRSNT_N","", + "CPU1_PRSNT_N","", + "CPU0_PWR_GOOD","", + "CPU1_PWR_GOOD","", + "PGD_SYS_PWROK","", + "BIOS_POST_CMPLT_N","", + "CPU0_CD_INIT_ERROR","", + "CPU1_CD_INIT_ERROR",""; + status =3D "okay"; +}; + +&spi1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_spi1_default>; + fmc-spi-user-mode; + status =3D "okay"; + + flash@0 { + m25p,fast-read; + label =3D "bios"; + spi-max-frequency =3D <20000000>; + spi-rx-bus-width =3D <2>; + status =3D "okay"; + }; +}; + +&syscon { + status =3D "okay"; +}; + +&uart1 { + status =3D "okay"; +}; + +&uart2 { + status =3D "okay"; +}; + +&uart3 { + status =3D "okay"; +}; + +&uart4 { + status =3D "okay"; +}; + +&uart5 { + status =3D "okay"; +}; + +&uart_routing { + status =3D "okay"; +}; + +&uhci { + status =3D "okay"; +}; + +&vhub { + status =3D "okay"; +}; + +&video { + memory-region =3D <&video_engine_memory>; + status =3D "okay"; +}; --=20 2.34.1