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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b472d7944e6sm1256386a12.54.2025.08.15.06.18.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Aug 2025 06:18:30 -0700 (PDT) From: Yuanfang Zhang Date: Fri, 15 Aug 2025 06:18:13 -0700 Subject: [PATCH 2/3] coresight-tnoc: add platform driver to support Interconnect TNOC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250815-itnoc-v1-2-62c8e4f7ad32@oss.qualcomm.com> References: <20250815-itnoc-v1-0-62c8e4f7ad32@oss.qualcomm.com> In-Reply-To: <20250815-itnoc-v1-0-62c8e4f7ad32@oss.qualcomm.com> To: Suzuki K Poulose , Mike Leach , James Clark , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alexander Shishkin Cc: kernel@oss.qualcomm.com, coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Yuanfang Zhang X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1755263906; l=7610; i=yuanfang.zhang@oss.qualcomm.com; s=20250814; h=from:subject:message-id; bh=h3BCc5LPt2vD2oa0GKj6H4bBZnHTi5frgwQGvlfz1zI=; b=L6M1QO3uxWCvsmlpAc7nM/HnmxBagv9W0cZsbsZBPJCSwwVXLss7mP6acRlSf2VThYC6pSqcJ gVp+CKtKrozD0olcJbQAsOrXzL3YxGhzVLZgKtZTe2IaW3IUWK+D6UH X-Developer-Key: i=yuanfang.zhang@oss.qualcomm.com; a=ed25519; pk=9oS/FoPW5k0CsqSDDrPlnV+kVIOUaAe0O5pr4M1wHgY= X-Authority-Analysis: v=2.4 cv=G6EcE8k5 c=1 sm=1 tr=0 ts=689f33a7 cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=2OwXVqhp2XgA:10 a=EUspDBNiAAAA:8 a=CwSfzSRg63tsHDaJLfgA:9 a=QEXdDO2ut3YA:10 a=uG9DUKGECoFWVXl0Dc02:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODExMDA5NyBTYWx0ZWRfX/Acnp8gdumu8 WKvapy/82tobsr4fG80QCBo2Yo7XqBRmBDaxM5THvZlkyx7lV+a4UjK/u18z/HOnpvgwykUh1PC KJAUu4OS8xQHF3OiWF+hZk61/M9jgsP9ZKvR4lO+hav42SVjc6etlh+MUWAeguvQFZDlzjnGWjs 7tWDVlFfEG37o7hJMYEx1PdHE5SK2acNXWHhNiDil6Lh70ooaZK9vvLcCDshIoihl9SV2jJQODT 3Zw9MuR8mb5h0iOcpsSb7RAdr9RTUPxaStB3wv1M6oG3Ju8S9tYayBnlJQSjQEsDlWHSz06v+Zw i7q7WYLlMhPaCx9PL/u2ZkuOD1irpfhGWFQMPRU9WoNB8wED/CgFpH/wNzQkVyQkIEi/hWdA/fj 4Vnn+kCv X-Proofpoint-ORIG-GUID: uxMaiE5RNobpgZQ7iJUoDHpmOK5wQENY X-Proofpoint-GUID: uxMaiE5RNobpgZQ7iJUoDHpmOK5wQENY X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-15_04,2025-08-14_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 priorityscore=1501 bulkscore=0 spamscore=0 phishscore=0 malwarescore=0 adultscore=0 impostorscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508110097 This patch adds platform driver support for the CoreSight Interconnect TNOC, Interconnect TNOC is a CoreSight link that forwards trace data from a subsystem to the Aggregator TNOC. Compared to Aggregator TNOC, it does not have aggregation and ATID functionality. Key changes: - Add platform driver `coresight-itnoc` with device tree match support. - Refactor probe logic into a common `_tnoc_probe()` function. - Conditionally initialize ATID only for AMBA-based TNOC blocks. Signed-off-by: Yuanfang Zhang --- drivers/hwtracing/coresight/coresight-tnoc.c | 153 +++++++++++++++++++----= ---- 1 file changed, 106 insertions(+), 47 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-tnoc.c b/drivers/hwtraci= ng/coresight/coresight-tnoc.c index d542df46ea39314605290311f683010337bfd4bd..aa6f48d838c00d71eff22c18e34= e00b93755fd82 100644 --- a/drivers/hwtracing/coresight/coresight-tnoc.c +++ b/drivers/hwtracing/coresight/coresight-tnoc.c @@ -34,6 +34,7 @@ * @base: memory mapped base address for this component. * @dev: device node for trace_noc_drvdata. * @csdev: component vitals needed by the framework. + * @pclk: APB clock if present, otherwise NULL * @spinlock: serialize enable/disable operation. * @atid: id for the trace packet. */ @@ -41,6 +42,7 @@ struct trace_noc_drvdata { void __iomem *base; struct device *dev; struct coresight_device *csdev; + struct clk *pclk; spinlock_t spinlock; u32 atid; }; @@ -51,25 +53,27 @@ static void trace_noc_enable_hw(struct trace_noc_drvdat= a *drvdata) { u32 val; =20 - /* Set ATID */ - writel_relaxed(drvdata->atid, drvdata->base + TRACE_NOC_XLD); - - /* Set the data word count between 'SYNC' packets */ - writel_relaxed(TRACE_NOC_SYNC_INTERVAL, drvdata->base + TRACE_NOC_SYNCR); - - /* Set the Control register: - * - Set the FLAG packets to 'FLAG' packets - * - Set the FREQ packets to 'FREQ_TS' packets - * - Enable generation of output ATB traffic - */ - - val =3D readl_relaxed(drvdata->base + TRACE_NOC_CTRL); - - val &=3D ~TRACE_NOC_CTRL_FLAGTYPE; - val |=3D TRACE_NOC_CTRL_FREQTYPE; - val |=3D TRACE_NOC_CTRL_PORTEN; - - writel(val, drvdata->base + TRACE_NOC_CTRL); + if (drvdata->atid) { + /* Set ATID */ + writel_relaxed(drvdata->atid, drvdata->base + TRACE_NOC_XLD); + + /* Set the data word count between 'SYNC' packets */ + writel_relaxed(TRACE_NOC_SYNC_INTERVAL, drvdata->base + TRACE_NOC_SYNCR); + /* Set the Control register: + * - Set the FLAG packets to 'FLAG' packets + * - Set the FREQ packets to 'FREQ_TS' packets + * - Enable generation of output ATB traffic + */ + + val =3D readl_relaxed(drvdata->base + TRACE_NOC_CTRL); + + val &=3D ~TRACE_NOC_CTRL_FLAGTYPE; + val |=3D TRACE_NOC_CTRL_FREQTYPE; + val |=3D TRACE_NOC_CTRL_PORTEN; + writel(val, drvdata->base + TRACE_NOC_CTRL); + } else { + writel(0x1, drvdata->base + TRACE_NOC_CTRL); + } } =20 static int trace_noc_enable(struct coresight_device *csdev, struct coresig= ht_connection *inport, @@ -120,19 +124,6 @@ static const struct coresight_ops trace_noc_cs_ops =3D= { .link_ops =3D &trace_noc_link_ops, }; =20 -static int trace_noc_init_default_data(struct trace_noc_drvdata *drvdata) -{ - int atid; - - atid =3D coresight_trace_id_get_system_id(); - if (atid < 0) - return atid; - - drvdata->atid =3D atid; - - return 0; -} - static ssize_t traceid_show(struct device *dev, struct device_attribute *attr, char *buf) { @@ -158,13 +149,12 @@ static const struct attribute_group *coresight_tnoc_g= roups[] =3D { NULL, }; =20 -static int trace_noc_probe(struct amba_device *adev, const struct amba_id = *id) +static int _tnoc_probe(struct device *dev, struct resource *res, bool has_= id) { - struct device *dev =3D &adev->dev; struct coresight_platform_data *pdata; struct trace_noc_drvdata *drvdata; struct coresight_desc desc =3D { 0 }; - int ret; + int ret, atid =3D 0; =20 desc.name =3D coresight_alloc_device_name(&trace_noc_devs, dev); if (!desc.name) @@ -173,42 +163,61 @@ static int trace_noc_probe(struct amba_device *adev, = const struct amba_id *id) pdata =3D coresight_get_platform_data(dev); if (IS_ERR(pdata)) return PTR_ERR(pdata); - adev->dev.platform_data =3D pdata; + dev->platform_data =3D pdata; =20 drvdata =3D devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); if (!drvdata) return -ENOMEM; =20 - drvdata->dev =3D &adev->dev; + drvdata->dev =3D dev; dev_set_drvdata(dev, drvdata); =20 - drvdata->base =3D devm_ioremap_resource(dev, &adev->res); + ret =3D coresight_get_enable_clocks(dev, &drvdata->pclk, NULL); + if (ret) + return ret; + + drvdata->base =3D devm_ioremap_resource(dev, res); if (IS_ERR(drvdata->base)) return PTR_ERR(drvdata->base); =20 spin_lock_init(&drvdata->spinlock); =20 - ret =3D trace_noc_init_default_data(drvdata); - if (ret) - return ret; + if (has_id) { + atid =3D coresight_trace_id_get_system_id(); + if (atid < 0) + return atid; + } + + drvdata->atid =3D atid; =20 desc.ops =3D &trace_noc_cs_ops; desc.type =3D CORESIGHT_DEV_TYPE_LINK; desc.subtype.link_subtype =3D CORESIGHT_DEV_SUBTYPE_LINK_MERG; - desc.pdata =3D adev->dev.platform_data; - desc.dev =3D &adev->dev; + desc.pdata =3D pdata; + desc.dev =3D dev; desc.access =3D CSDEV_ACCESS_IOMEM(drvdata->base); - desc.groups =3D coresight_tnoc_groups; + if (has_id) + desc.groups =3D coresight_tnoc_groups; drvdata->csdev =3D coresight_register(&desc); - if (IS_ERR(drvdata->csdev)) { + if (IS_ERR(drvdata->csdev) && has_id) { coresight_trace_id_put_system_id(drvdata->atid); return PTR_ERR(drvdata->csdev); } - pm_runtime_put(&adev->dev); =20 return 0; } =20 +static int trace_noc_probe(struct amba_device *adev, const struct amba_id = *id) +{ + int ret; + + ret =3D _tnoc_probe(&adev->dev, &adev->res, true); + if (!ret) + pm_runtime_put(&adev->dev); + + return ret; +} + static void trace_noc_remove(struct amba_device *adev) { struct trace_noc_drvdata *drvdata =3D dev_get_drvdata(&adev->dev); @@ -236,7 +245,57 @@ static struct amba_driver trace_noc_driver =3D { .id_table =3D trace_noc_ids, }; =20 -module_amba_driver(trace_noc_driver); +static int itnoc_probe(struct platform_device *pdev) +{ + struct resource *res =3D platform_get_resource(pdev, IORESOURCE_MEM, 0); + int ret; + + pm_runtime_get_noresume(&pdev->dev); + pm_runtime_set_active(&pdev->dev); + pm_runtime_enable(&pdev->dev); + + ret =3D _tnoc_probe(&pdev->dev, res, false); + pm_runtime_put(&pdev->dev); + if (ret) + pm_runtime_disable(&pdev->dev); + + return ret; +} + +static void itnoc_remove(struct platform_device *pdev) +{ + struct trace_noc_drvdata *drvdata =3D platform_get_drvdata(pdev); + + coresight_unregister(drvdata->csdev); + pm_runtime_disable(&pdev->dev); +} + +static const struct of_device_id itnoc_of_match[] =3D { + { .compatible =3D "qcom,coresight-itnoc" }, + {} +}; +MODULE_DEVICE_TABLE(of, itnoc_of_match); + +static struct platform_driver itnoc_driver =3D { + .probe =3D itnoc_probe, + .remove =3D itnoc_remove, + .driver =3D { + .name =3D "coresight-itnoc", + .of_match_table =3D itnoc_of_match, + }, +}; + +static int __init tnoc_init(void) +{ + return coresight_init_driver("tnoc", &trace_noc_driver, &itnoc_driver, TH= IS_MODULE); +} + +static void __exit tnoc_exit(void) +{ + coresight_remove_driver(&trace_noc_driver, &itnoc_driver); +} +module_init(tnoc_init); +module_exit(tnoc_exit); =20 MODULE_LICENSE("GPL"); MODULE_DESCRIPTION("Trace NOC driver"); --=20 2.34.1