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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b472d7944e6sm1256386a12.54.2025.08.15.06.18.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Aug 2025 06:18:28 -0700 (PDT) From: Yuanfang Zhang Date: Fri, 15 Aug 2025 06:18:12 -0700 Subject: [PATCH 1/3] dt-bindings: arm: qcom: Add Coresight Interconnect TNOC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250815-itnoc-v1-1-62c8e4f7ad32@oss.qualcomm.com> References: <20250815-itnoc-v1-0-62c8e4f7ad32@oss.qualcomm.com> In-Reply-To: <20250815-itnoc-v1-0-62c8e4f7ad32@oss.qualcomm.com> To: Suzuki K Poulose , Mike Leach , James Clark , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alexander Shishkin Cc: kernel@oss.qualcomm.com, coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Yuanfang Zhang X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1755263906; l=3400; i=yuanfang.zhang@oss.qualcomm.com; s=20250814; h=from:subject:message-id; bh=iFGrvpCpH4OzqPsKWLDwUClOVbka/29o5GG8qAczHik=; b=qyemCdR3P2VMmp7XSc+HQGGmjYmMzyTQG+snL1xiWIJZY/XORmtMi4kBRE3qJEpQsRwMvRJDo 3CPb/IldSn1BjS12mEqgCgJiZjyfgJan0lEIGyUKjWy9sFlDUSulzWF X-Developer-Key: i=yuanfang.zhang@oss.qualcomm.com; a=ed25519; pk=9oS/FoPW5k0CsqSDDrPlnV+kVIOUaAe0O5pr4M1wHgY= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODExMDEwNyBTYWx0ZWRfX5sXbEXlFwoGl 8tmynoSWXgvVe+y/tVw/0cPpaqNJ2s+S7V364FmvuifdaD7a6o4pSVPvC9JcPw7pE+Kg51i/e4w 1wnx20ofdXmmKXdX2eocZmzN9UNhuVBO42CkqJ2q994Mm9uDuq8K/fsLLPIn+L7usl2hNlJh7eK DlEfLjf9OCM92O2XUleHHvAXVfxerBiy+yAv3h52LOvsZeV4tqSJu8/F9atAXqp4o9STaXYGGcG LKywJZsDoTqsV93Zfm7ITgyQwhv7DWj4+wz0LNg4xcx1srLo4JMtLjZL0uu5f3/cPLJ+k1MO/Qh VAj1si/MlRUIhPgqE+BOrdEivol4f1HSOQ0rCEdOqT9yeYaq1Ju8+q9H5dOq32i9lwNc2L1yrMt dEFufCRT X-Proofpoint-GUID: p0-8CANflTkS4k4LsjQv4XbYMhfe9a35 X-Authority-Analysis: v=2.4 cv=A+1sP7WG c=1 sm=1 tr=0 ts=689f33a7 cx=c_pps a=Qgeoaf8Lrialg5Z894R3/Q==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=2OwXVqhp2XgA:10 a=gEfo2CItAAAA:8 a=EUspDBNiAAAA:8 a=v7KY3twRVyNl3kJcRO4A:9 a=QEXdDO2ut3YA:10 a=x9snwWr2DeNwDh03kgHS:22 a=sptkURWiP4Gy88Gu7hUp:22 X-Proofpoint-ORIG-GUID: p0-8CANflTkS4k4LsjQv4XbYMhfe9a35 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-15_04,2025-08-14_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 suspectscore=0 priorityscore=1501 malwarescore=0 spamscore=0 phishscore=0 clxscore=1015 adultscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508110107 Add device tree binding for Qualcomm Coresight Interconnect Trace Netwrok On Chip (ITNOC). This TNOC acts as a CoreSight graph link that forwards trace data from a subsystem to the Aggregator TNOC, without aggregation or ATID functionality. Signed-off-by: Yuanfang Zhang --- .../bindings/arm/qcom,coresight-itnoc.yaml | 108 +++++++++++++++++= ++++ 1 file changed, 108 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-itnoc.yam= l b/Documentation/devicetree/bindings/arm/qcom,coresight-itnoc.yaml new file mode 100644 index 0000000000000000000000000000000000000000..fd224e07ce68918b453210763aa= cda585d5a5ca2 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-itnoc.yaml @@ -0,0 +1,108 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/qcom,coresight-itnoc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Interconnect Trace Network On Chip - ITNOC + +maintainers: + - Yuanfang Zhang + +description: | + The Interconnect TNOC is a CoreSight graph link that forwards trace data + from a subsystem to the Aggregator TNOC. Compared to Aggregator TNOC, it + does not have aggregation and ATID functionality. + +select: + properties: + compatible: + contains: + enum: + - qcom,coresight-itnoc + required: + - compatible + +properties: + $nodename: + pattern: "^tnoc(@[0-9a-f]+)?$" + + compatible: + items: + - const: qcom,coresight-itnoc + + reg: + maxItems: 1 + description: Base address and size of the ITNOC registers. + + clock-names: + items: + - const: apb + + clocks: + maxItems: 1 + + in-ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + '#address-cells': + const: 1 + '#size-cells': + const: 0 + + patternProperties: + '^port(@[0-9a-f]{1,2})?$': + description: Input connections from CoreSight Trace Bus + $ref: /schemas/graph.yaml#/properties/port + additionalProperties: false + + out-ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port: + description: out connections to aggregator TNOC + $ref: /schemas/graph.yaml#/properties/port + additionalProperties: false + +required: + - compatible + - reg + - clocks + - clock-names + - in-ports + - out-ports + +additionalProperties: false + +examples: + - | + tnoc@109ac000 { + compatible =3D "qcom,coresight-itnoc"; + reg =3D <0x109ac000 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb"; + + in-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + port@0 { + reg =3D <0>; + tn_ic_in_tpdm_dcc: endpoint { + remote-endpoint =3D <&tpdm_dcc_out_tn_ic>; + }; + }; + }; + + out-ports { + port { + tn_ic_out_tnoc_aggr: endpoint { + /* to Aggregator TNOC input */ + remote-endpoint =3D <&tn_ag_in_tn_ic>; + }; + }; + }; + }; +... --=20 2.34.1