From nobody Sat Oct 4 14:16:58 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9519B2E5D2F; Fri, 15 Aug 2025 16:56:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755277015; cv=none; b=qoNSyfcEyqopImnHwRkaW1V1FQ5AYcjFPojtWhBzyzZv8sLxXHq+3MvXPx48CrkvT5SH/5v5JSIfMHzlOqnz4YEW9vn2MuGcnKKD1yc+rHXL7cwQwtS8eDjlY3St22ODfiQLPa9LleteRVXS7jawLyKEQPzzF114O2CVz5SGhSQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755277015; c=relaxed/simple; bh=qkFRHrnku+8IhPnvvclol2lWXtFk7tOS52R0VQGPaSg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=qPSufM7jAOSyfH88i3ngsQ1g6PGYR0cVXRUfbkkE3e0fRc4IqiA/tvHg3ntCJSHk+ZLS+02asOvyPH9v/ROSYXZWCKQvElfovm+s4y86ZPF7HYgbgk4aN4CWmLs12eChCbA/XKqnMHuICvDVlYl2Az9yNkEuQ6/LdcHTcjU7paY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=SqhR9X2F; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="SqhR9X2F" Received: by smtp.kernel.org (Postfix) with ESMTPS id 1D68DC4CEF6; Fri, 15 Aug 2025 16:56:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755277014; bh=qkFRHrnku+8IhPnvvclol2lWXtFk7tOS52R0VQGPaSg=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=SqhR9X2FX17kOMV2bHUujwqMohN3xJ2d+RdlabUdb9Ku2I6VrWr/Mi9YByP821pzg t7BUXgbr4J/aHHqcV34YlMQx34U34/IiOr2gT1mJnUHRNBKB3A54+bJcRiZ9SgUtgm jsheCuEPTaJ9uWpNyKWRP8tbHrftk27FHT7nhMHznVGekLe+Pdz5mAOMMsdcoZ98h5 S9quiQ72xn204IDvYeMUNyafVAUkbxITfztf3g8zW7ryXeQPzekK+hGAvAa73h+nfx zl33mg1YXtXX8v37/9dyYSzmZVvdogQNMqdafIi8FyhCrdsLavX4NN062hpenetL+f cX2E/xngXPzbA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0CD66CA0EE4; Fri, 15 Aug 2025 16:56:54 +0000 (UTC) From: Nickolay Goppen via B4 Relay Date: Fri, 15 Aug 2025 19:56:52 +0300 Subject: [PATCH 2/2] clk: qcom: gcc-sdm660: Add missing LPASS/CDSP vote clocks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250815-gcc-sdm660-vote-clocks-and-gdscs-v1-2-c5a8af040093@yandex.ru> References: <20250815-gcc-sdm660-vote-clocks-and-gdscs-v1-0-c5a8af040093@yandex.ru> In-Reply-To: <20250815-gcc-sdm660-vote-clocks-and-gdscs-v1-0-c5a8af040093@yandex.ru> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Nickolay Goppen , Konrad Dybcio X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1755277013; l=3670; i=setotau@yandex.ru; s=20250815; h=from:subject:message-id; bh=X6/ri844i2ly7ZOG0yiJaP7SUffxbwteMISWIbXh6r0=; b=HuolyR9GWC21w2uCY+YDwdApm9VK5PTQTV9zv+Iyv+j47UnMQ0TChMXhDiz1mi/kNU9pS0Cxk zccW+gYqsH8Cgdmf0cWJnjd3tkEahbU7MOkwgIfABI2afTNaz1wxDrM X-Developer-Key: i=setotau@yandex.ru; a=ed25519; pk=Og7YO6LfW+M2QfcJfjaUaXc8oOr5zoK8+4AtX5ICr4o= X-Endpoint-Received: by B4 Relay for setotau@yandex.ru/20250815 with auth_id=492 X-Original-From: Nickolay Goppen Reply-To: setotau@yandex.ru From: Nickolay Goppen For the proper functioning of SMMUs related to the audio/compute DSPs, it makes sense that the clocks and power domains they rely on for communication should be online. Add the vote clocks & GDSCs that, when enabled, ensure all such requirements are met, through various internal mechanisms. Co-developed-by: Konrad Dybcio Signed-off-by: Konrad Dybcio Signed-off-by: Nickolay Goppen Reviewed-by: Dmitry Baryshkov --- drivers/clk/qcom/gcc-sdm660.c | 72 +++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 72 insertions(+) diff --git a/drivers/clk/qcom/gcc-sdm660.c b/drivers/clk/qcom/gcc-sdm660.c index 01a76f1b5b4c146937a4f5fa0011309fd6ed6be8..20253a06a5839b7265548b4f9fd= c1ffc9cf6f9f5 100644 --- a/drivers/clk/qcom/gcc-sdm660.c +++ b/drivers/clk/qcom/gcc-sdm660.c @@ -2247,6 +2247,45 @@ static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk= =3D { }, }; =20 +static struct clk_branch hlos1_vote_lpass_adsp_smmu_clk =3D { + .halt_reg =3D 0x7d014, + .halt_check =3D BRANCH_VOTED, + .clkr =3D { + .enable_reg =3D 0x7d014, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "hlos1_vote_lpass_adsp_smmu_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch hlos1_vote_turing_adsp_smmu_clk =3D { + .halt_reg =3D 0x7d048, + .halt_check =3D BRANCH_VOTED, + .clkr =3D { + .enable_reg =3D 0x7d048, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "hlos1_vote_turing_adsp_smmu_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch hlos2_vote_turing_adsp_smmu_clk =3D { + .halt_reg =3D 0x7e048, + .halt_check =3D BRANCH_VOTED, + .clkr =3D { + .enable_reg =3D 0x7e048, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "hlos2_vote_turing_adsp_smmu_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + static struct gdsc ufs_gdsc =3D { .gdscr =3D 0x75004, .gds_hw_ctrl =3D 0x0, @@ -2277,6 +2316,33 @@ static struct gdsc pcie_0_gdsc =3D { .flags =3D VOTABLE, }; =20 +static struct gdsc hlos1_vote_turing_adsp_gdsc =3D { + .gdscr =3D 0x7d04c, + .pd =3D { + .name =3D "hlos1_vote_turing_adsp_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D VOTABLE, +}; + +static struct gdsc hlos2_vote_turing_adsp_gdsc =3D { + .gdscr =3D 0x7e04c, + .pd =3D { + .name =3D "hlos2_vote_turing_adsp_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D VOTABLE, +}; + +static struct gdsc hlos1_vote_lpass_adsp_gdsc =3D { + .gdscr =3D 0x7d034, + .pd =3D { + .name =3D "hlos1_vote_lpass_adsp_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D VOTABLE, +}; + static struct clk_hw *gcc_sdm660_hws[] =3D { &xo.hw, &gpll0_early_div.hw, @@ -2409,12 +2475,18 @@ static struct clk_regmap *gcc_sdm660_clocks[] =3D { [USB30_MASTER_CLK_SRC] =3D &usb30_master_clk_src.clkr, [USB30_MOCK_UTMI_CLK_SRC] =3D &usb30_mock_utmi_clk_src.clkr, [USB3_PHY_AUX_CLK_SRC] =3D &usb3_phy_aux_clk_src.clkr, + [GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK] =3D &hlos1_vote_lpass_adsp_smmu_clk.= clkr, + [GCC_HLOS1_VOTE_TURING_ADSP_SMMU_CLK] =3D &hlos1_vote_turing_adsp_smmu_cl= k.clkr, + [GCC_HLOS2_VOTE_TURING_ADSP_SMMU_CLK] =3D &hlos2_vote_turing_adsp_smmu_cl= k.clkr, }; =20 static struct gdsc *gcc_sdm660_gdscs[] =3D { [UFS_GDSC] =3D &ufs_gdsc, [USB_30_GDSC] =3D &usb_30_gdsc, [PCIE_0_GDSC] =3D &pcie_0_gdsc, + [HLOS1_VOTE_TURING_ADSP_GDSC] =3D &hlos1_vote_turing_adsp_gdsc, + [HLOS2_VOTE_TURING_ADSP_GDSC] =3D &hlos2_vote_turing_adsp_gdsc, + [HLOS1_VOTE_LPASS_ADSP_GDSC] =3D &hlos1_vote_lpass_adsp_gdsc, }; =20 static const struct qcom_reset_map gcc_sdm660_resets[] =3D { --=20 2.50.1