From nobody Sat Oct 4 17:33:51 2025 Received: from lelvem-ot02.ext.ti.com (lelvem-ot02.ext.ti.com [198.47.23.235]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CA9DD1F9F7A; Thu, 14 Aug 2025 22:39:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.235 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755211167; cv=none; b=FI5lu9bdDRtGEAcPMBLPjPcYRkvF6952ylFMCduRuiPWSXMNyrvy0/6dm/jcqjejflns62ZcKbzpVOb3wj+mdMC1uzgT00PZvR8s1wD4W7My5oM/P8jQZN0x9Oi+W1QCzUnpHZPZ19Oy1b0DQyOQsmNtQTZdh0vf8fECxJh9dbM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755211167; c=relaxed/simple; bh=/wEWHXoHa/qzzH2DR+RZyMubfRLLC06wvIOwGE/6YmE=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=SVc687QXJmG+b1JX3M1r41gzIBttC52E4Cv2AAXN5khbE5Miy1LRdc0bK9UADxJURl1Wtzy9c8i9ovqqSae0zi4BXk3VwBZPqIFxk5BHyUdqnin1iq+HBoLYo/r3A5xwbNAp7Vu/pSSyzSlQXfhiHPJWNyDH7EnqjKygHxJyMYY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=mKQUeQFD; arc=none smtp.client-ip=198.47.23.235 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="mKQUeQFD" Received: from lelvem-sh01.itg.ti.com ([10.180.77.71]) by lelvem-ot02.ext.ti.com (8.15.2/8.15.2) with ESMTP id 57EMdKpW2478865; Thu, 14 Aug 2025 17:39:20 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1755211160; bh=psWBlSyyw4DdpBB8/QiNlEKW7KQ4LaMIx3LmqaR26/Y=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=mKQUeQFDScfr9SJSFmfGGsRJEFNrXWIAdP7b1f9iOihRaz7Qb2W6VZSeerRc6Pbaf 5H4pWlKaLf37+nDI7RzfEN0wC4Ml9CtPAYNET/rQ1M4AM8Ppo68AAGhNFo/sJkXHZL h3zTVGOY4V4dRczpXNjNf/YS9vNn9NS+E9y2cPe0= Received: from DFLE102.ent.ti.com (dfle102.ent.ti.com [10.64.6.23]) by lelvem-sh01.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 57EMdKEb1158695 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Thu, 14 Aug 2025 17:39:20 -0500 Received: from DFLE108.ent.ti.com (10.64.6.29) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Thu, 14 Aug 2025 17:39:19 -0500 Received: from lelvem-mr06.itg.ti.com (10.180.75.8) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Thu, 14 Aug 2025 17:39:19 -0500 Received: from uda0510294.dhcp.ti.com (uda0510294.dhcp.ti.com [172.24.234.212]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 57EMcw4c096792; Thu, 14 Aug 2025 17:39:15 -0500 From: Beleswar Padhi To: , , , , , CC: , , , , , , , Subject: [PATCH 03/33] Revert "arm64: dts: ti: k3-j721e-sk: Fix reversed C6x carveout locations" Date: Fri, 15 Aug 2025 04:08:09 +0530 Message-ID: <20250814223839.3256046-4-b-padhi@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250814223839.3256046-1-b-padhi@ti.com> References: <20250814223839.3256046-1-b-padhi@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" This reverts commit 9f3814a7c06b7c7296cf8c1622078ad71820454b. The C6x carveouts are reversed intentionally. This is due to the requirement to keep the DMA memory region as non-cached, however the minimum granular cache region for C6x is 16MB. So, C66x_0 marks the entire C66x_1 16MB memory carveouts as non-cached, and uses the DMA memory region of C66x_1 as its own, and vice-versa. This was also called out in the original commit which introduced these reversed carveouts: "The minimum granularity on the Cache settings on C66x DSP cores is 16MB, so the DMA memory regions are chosen such that they are in separate 16MB regions for each DSP, while reserving a total of 16 MB for each DSP and not changing the overall DSP remoteproc carveouts." Fixes: 9f3814a7c06b ("arm64: dts: ti: k3-j721e-sk: Fix reversed C6x carveou= t locations") Signed-off-by: Beleswar Padhi --- arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/t= i/k3-j721e-sk.dts index ffef3d1cfd55..9882bb1e8097 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts @@ -120,7 +120,8 @@ main_r5fss1_core1_memory_region: r5f-memory@a5100000 { no-map; }; =20 - c66_0_dma_memory_region: c66-dma-memory@a6000000 { + /* Carveout locations are flipped due to caching */ + c66_1_dma_memory_region: c66-dma-memory@a6000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa6000000 0x00 0x100000>; no-map; @@ -132,7 +133,8 @@ c66_0_memory_region: c66-memory@a6100000 { no-map; }; =20 - c66_1_dma_memory_region: c66-dma-memory@a7000000 { + /* Carveout locations are flipped due to caching */ + c66_0_dma_memory_region: c66-dma-memory@a7000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa7000000 0x00 0x100000>; no-map; --=20 2.34.1