From nobody Sat Oct 4 17:33:48 2025 Received: from lelvem-ot02.ext.ti.com (lelvem-ot02.ext.ti.com [198.47.23.235]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C4D6629C35F; Thu, 14 Aug 2025 22:41:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.235 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755211288; cv=none; b=frLnpf6jN7Bk9O/naF1eO2tqiYJI93VEd1S/WxHr+ST0+8qoB5oruEN1gFnbwqY9YerMDsMM4cUg0cXQ2ILXrSPEFbA92icPhWsBMIBLLncKvStZiNc0qkJGYJd58bjCWeELvJ/9mgFyxUBBG1NKQBEF1kfO6Qbtj20vWLFh0SY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755211288; c=relaxed/simple; bh=O8SsgYcfTyUo6xbb+Nc5dSj/A9EDNJ+AhQ8hTmSSW+8=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=OS/dD8+f3zqevaIl2wVRjQ9gtNNadjbfoGyMIHdl15LY+rH+uHJat9KcJtlPkijVKpNHev2jMRhAtaegLtaJvIfzc7fh7kp09enN/6QjLjXHSMC1v+lvSIIQhc36BwYW8YCS3d0R+5mj1ilrvP6P3XrDbunXcUD2ruMHkgwmips= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=mYMU7nNq; arc=none smtp.client-ip=198.47.23.235 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="mYMU7nNq" Received: from fllvem-sh04.itg.ti.com ([10.64.41.54]) by lelvem-ot02.ext.ti.com (8.15.2/8.15.2) with ESMTP id 57EMfMbd2479189; Thu, 14 Aug 2025 17:41:22 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1755211282; bh=MgpQF8NEHM74XK+XoauEt9uMlStviBrFN7z5i09pP4s=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=mYMU7nNqUPT6trdGPAzCcT748XjIicawUOBr2840bYYnvUA1JnWfRpTUGGzmwu4O9 /cYmGr84NwWMkqlyZq4xa0onxB19GAnR26bnxT6lTNs3DVQDtSjjVhTTJ5Okvxjo4V IRmnkHy1CpChr4cIb77laLDhkKJ1C6AAjKNocT0k= Received: from DFLE113.ent.ti.com (dfle113.ent.ti.com [10.64.6.34]) by fllvem-sh04.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 57EMfMZZ2150815 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Thu, 14 Aug 2025 17:41:22 -0500 Received: from DFLE115.ent.ti.com (10.64.6.36) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Thu, 14 Aug 2025 17:41:22 -0500 Received: from lelvem-mr06.itg.ti.com (10.180.75.8) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Thu, 14 Aug 2025 17:41:22 -0500 Received: from uda0510294.dhcp.ti.com (uda0510294.dhcp.ti.com [172.24.234.212]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 57EMcw56096792; Thu, 14 Aug 2025 17:41:18 -0500 From: Beleswar Padhi To: , , , , , CC: , , , , , , , Subject: [PATCH 31/33] arm64: dts: ti: k3-am65: Enable remote processors at board level Date: Fri, 15 Aug 2025 04:08:37 +0530 Message-ID: <20250814223839.3256046-32-b-padhi@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250814223839.3256046-1-b-padhi@ti.com> References: <20250814223839.3256046-1-b-padhi@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Remote Processors defined in top-level AM65x SoC dtsi files are incomplete without the memory carveouts and mailbox assignments which are only known at board integration level. Therefore, disable the remote processors at SoC level and enable them at board level where above information is available. Signed-off-by: Beleswar Padhi --- arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi | 6 ++++++ arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi | 3 +++ arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 6 ++++++ 3 files changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi b/arch/arm6= 4/boot/dts/ti/k3-am65-iot2050-common.dtsi index b86ee00d48f7..6cd499ea53e7 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi @@ -602,16 +602,22 @@ mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { }; }; =20 +&mcu_r5fss0 { + status =3D "okay"; +}; + &mcu_r5fss0_core0 { memory-region =3D <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; mboxes =3D <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; + status =3D "okay"; }; =20 &mcu_r5fss0_core1 { memory-region =3D <&mcu_r5fss0_core1_dma_memory_region>, <&mcu_r5fss0_core1_memory_region>; mboxes =3D <&mailbox0_cluster1 &mbox_mcu_r5fss0_core1>; + status =3D "okay"; }; =20 &mcu_rti1 { diff --git a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi b/arch/arm64/boot/dts/= ti/k3-am65-mcu.dtsi index 7cf1f646500a..f6d9a5779918 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi @@ -408,6 +408,7 @@ mcu_r5fss0: r5fss@41000000 { ranges =3D <0x41000000 0x00 0x41000000 0x20000>, <0x41400000 0x00 0x41400000 0x20000>; power-domains =3D <&k3_pds 129 TI_SCI_PD_EXCLUSIVE>; + status =3D "disabled"; =20 mcu_r5fss0_core0: r5f@41000000 { compatible =3D "ti,am654-r5f"; @@ -422,6 +423,7 @@ mcu_r5fss0_core0: r5f@41000000 { ti,atcm-enable =3D <1>; ti,btcm-enable =3D <1>; ti,loczrama =3D <1>; + status =3D "disabled"; }; =20 mcu_r5fss0_core1: r5f@41400000 { @@ -437,6 +439,7 @@ mcu_r5fss0_core1: r5f@41400000 { ti,atcm-enable =3D <1>; ti,btcm-enable =3D <1>; ti,loczrama =3D <1>; + status =3D "disabled"; }; }; =20 diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/bo= ot/dts/ti/k3-am654-base-board.dts index d48171212ac9..e532ea0a22b2 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -541,16 +541,22 @@ mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { }; }; =20 +&mcu_r5fss0 { + status =3D "okay"; +}; + &mcu_r5fss0_core0 { memory-region =3D <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; mboxes =3D <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; + status =3D "okay"; }; =20 &mcu_r5fss0_core1 { memory-region =3D <&mcu_r5fss0_core1_dma_memory_region>, <&mcu_r5fss0_core1_memory_region>; mboxes =3D <&mailbox0_cluster1 &mbox_mcu_r5fss0_core1>; + status =3D "okay"; }; =20 &ospi0 { --=20 2.34.1