From nobody Sat Oct 4 17:33:45 2025 Received: from lelvem-ot01.ext.ti.com (lelvem-ot01.ext.ti.com [198.47.23.234]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8D16F283FF8; Thu, 14 Aug 2025 22:41:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.234 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755211283; cv=none; b=L9ywdaZgIM1s2jEsnhF1ORzsAPuGngWFVplB7vBlFN7Wzf0BSYROl+5B9kzb/HtKUJ3JTKSKloCoLjGCppSe9l58ods01VT08fQ91fRQlhZOJ6zp23HzFL5eZgZGWqPuuNY0qS+QazfeS0WHVIBAAxPEoYvT1y2jGcCIkk9gSfM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755211283; c=relaxed/simple; bh=KDPU6uPE4SSMZx4adpSgR02L5gg2e7ud/PwcOMDCqnA=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=YPzRZpOfFjbx154Q0QiOlykrVFlC2w6w99sCizEZCGSlMkhqZnGqiRTWKIX+3oJu96mDXnaBIdaCdnEXU+jZJ+aDmikEz18s8wE/OX3C/KNyRrdATk6mVtar1HthHJnowsgDfuHWgwaU1B+XfbpoKg6f8pxt2wKBmhRuRABmN8g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=tfgtjKjh; arc=none smtp.client-ip=198.47.23.234 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="tfgtjKjh" Received: from lelvem-sh01.itg.ti.com ([10.180.77.71]) by lelvem-ot01.ext.ti.com (8.15.2/8.15.2) with ESMTP id 57EMfENj2027605; Thu, 14 Aug 2025 17:41:14 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1755211274; bh=QR9W2rOLQodKkRjHEIxKYAwbxgT4Y1WxdqyyMQYNCVU=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=tfgtjKjhWiPt2oq56roNDk6svKU60YyHYZw6W3EdMIvUml6FP73cQCnaUjps7xcOV 4UICg03Dld1SBaLR5VeVhf/UuJUWzyf1uGqd1XjO5yvj7sxvefa+X6pLW7cy3oQ/LW FQdm8an/smF+uWMXKbtoSbbszjBHPvjDs0JSfz+4= Received: from DFLE113.ent.ti.com (dfle113.ent.ti.com [10.64.6.34]) by lelvem-sh01.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 57EMfEr91159572 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Thu, 14 Aug 2025 17:41:14 -0500 Received: from DFLE105.ent.ti.com (10.64.6.26) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Thu, 14 Aug 2025 17:41:14 -0500 Received: from lelvem-mr06.itg.ti.com (10.180.75.8) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Thu, 14 Aug 2025 17:41:13 -0500 Received: from uda0510294.dhcp.ti.com (uda0510294.dhcp.ti.com [172.24.234.212]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 57EMcw54096792; Thu, 14 Aug 2025 17:41:09 -0500 From: Beleswar Padhi To: , , , , , CC: , , , , , , , , Matthias Schiffer Subject: [PATCH 29/33] arm64: dts: ti: k3-am642-tqma64xxl: Add missing cfg for TI IPC Firmware Date: Fri, 15 Aug 2025 04:08:35 +0530 Message-ID: <20250814223839.3256046-30-b-padhi@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250814223839.3256046-1-b-padhi@ti.com> References: <20250814223839.3256046-1-b-padhi@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Currently, only R5F remote processors are enabled for k3-am642-tqma64xxl whereas the M4F in MCU domain is disabled. Enable the M4F remote processor at board level by reserving memory carveouts and assigning mailboxes. While at it, reserve the MAIN domain timers that are used by R5F remote processors for ticks to avoid rproc crashes. This config aligns with other AM64 boards and can be refactored out later. Signed-off-by: Beleswar Padhi --- Cc: Matthias Schiffer Request for review/test of this patch. .../arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi | 39 +++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi b/arch/arm64/bo= ot/dts/ti/k3-am642-tqma64xxl.dtsi index 40b619c9a6c9..860b79aa5ef5 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi @@ -79,6 +79,18 @@ main_r5fss1_core1_memory_region: r5f-memory@a3100000 { no-map; }; =20 + mcu_m4fss_dma_memory_region: m4f-dma-memory@a4000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa4000000 0x00 0x100000>; + no-map; + }; + + mcu_m4fss_memory_region: m4f-memory@a4100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa4100000 0x00 0xf00000>; + no-map; + }; + rtos_ipc_memory_region: ipc-memories@a5000000 { reg =3D <0x00 0xa5000000 0x00 0x00800000>; alignment =3D <0x1000>; @@ -167,6 +179,26 @@ mbox_m4_0: mbox-m4-0 { }; }; =20 +/* main_timer8 is used by r5f0-0 */ +&main_timer8 { + status =3D "reserved"; +}; + +/* main_timer9 is used by r5f0-1 */ +&main_timer9 { + status =3D "reserved"; +}; + +/* main_timer10 is used by r5f1-0 */ +&main_timer10 { + status =3D "reserved"; +}; + +/* main_timer11 is used by r5f1-1 */ +&main_timer11 { + status =3D "reserved"; +}; + &main_r5fss0 { status =3D "okay"; }; @@ -203,6 +235,13 @@ &main_r5fss1_core1 { status =3D "okay"; }; =20 +&mcu_m4fss { + mboxes =3D <&mailbox0_cluster6 &mbox_m4_0>; + memory-region =3D <&mcu_m4fss_dma_memory_region>, + <&mcu_m4fss_memory_region>; + status =3D "okay"; +}; + &ospi0 { status =3D "okay"; pinctrl-names =3D "default"; --=20 2.34.1