From nobody Sat Oct 4 17:33:45 2025 Received: from lelvem-ot01.ext.ti.com (lelvem-ot01.ext.ti.com [198.47.23.234]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B355228724F; Thu, 14 Aug 2025 22:41:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.234 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755211275; cv=none; b=mMUeu1Iw9ujy8yWP2UahYMTUi4miJDSMTfNLo8rV9CZDWcRJGOHm72js/mEj83pkbe+WlWtwR/deFGQx8vkFbp99nwy2ichq/BW7L+pIDlO441hftOuhk12HCVqN5Wd4yqNbrRMt0DzGssBp3mnIP66MmRK/+Xx2YFlyEAZxl5M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755211275; c=relaxed/simple; bh=NfeHYpY7ijrLFT9xJPSVlvOnVZ0s6qogcPO0l58qJ7o=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=GY4uzEnpK972hWnqpeJWq/sI10ooceRk5G3oVH01JXAUYIOn62CNqyapNbbFCW2dqGLsbQMUXX8fV4AhouccGp8lzDSaApIi5NIsP/IEiGRR+B/70fnZA8TphzUXB+WoTKM/R89Y9jtC9HdOcMc+kMuuXKNkXgsiKZH3wLEsSp8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=ZXPVRqis; arc=none smtp.client-ip=198.47.23.234 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="ZXPVRqis" Received: from lelvem-sh02.itg.ti.com ([10.180.78.226]) by lelvem-ot01.ext.ti.com (8.15.2/8.15.2) with ESMTP id 57EMf4lI2027589; Thu, 14 Aug 2025 17:41:04 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1755211264; bh=vFo+wZGWy123BnkAseyt/jYwgUH3fS7+pfcXSlYcsic=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=ZXPVRqisHppz4I/ECioQcA2JPUZydh1PIeswsw+YpgzMmY5kfzM1ODALxWFo+IgWX HzlQg8tEBw6Xp48Fmludt0CHf4hg1JQNl7oFw+rdcg2RvAdRJ1P4C2CuPREj8sd9K8 TmnLOCYrTjkAvryaMzvxlm7d1YKyPxlqxaFmuQps= Received: from DFLE108.ent.ti.com (dfle108.ent.ti.com [10.64.6.29]) by lelvem-sh02.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 57EMf4Bu2016548 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Thu, 14 Aug 2025 17:41:04 -0500 Received: from DFLE110.ent.ti.com (10.64.6.31) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Thu, 14 Aug 2025 17:41:03 -0500 Received: from lelvem-mr06.itg.ti.com (10.180.75.8) by DFLE110.ent.ti.com (10.64.6.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Thu, 14 Aug 2025 17:41:03 -0500 Received: from uda0510294.dhcp.ti.com (uda0510294.dhcp.ti.com [172.24.234.212]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 57EMcw52096792; Thu, 14 Aug 2025 17:40:59 -0500 From: Beleswar Padhi To: , , , , , CC: , , , , , , , , Josua Mayer , Logan Bristol , Matthias Schiffer Subject: [PATCH 27/33] arm64: dts: ti: k3-am642-sr-som: Add missing cfg for TI IPC Firmware Date: Fri, 15 Aug 2025 04:08:33 +0530 Message-ID: <20250814223839.3256046-28-b-padhi@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250814223839.3256046-1-b-padhi@ti.com> References: <20250814223839.3256046-1-b-padhi@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Currently, only R5F remote processors are enabled for k3-am642-sr SoMs, whereas the M4F in MCU domain is disabled. Enable the M4F remote processor at board level by reserving memory carveouts and assigning mailboxes. While at it, reserve the MAIN domain timers that are used by R5F remote processors for ticks to avoid rproc crashes. This config aligns with other AM64 boards and can be refactored out later. Signed-off-by: Beleswar Padhi --- Cc: Josua Mayer Cc: Logan Bristol Cc: Matthias Schiffer Requesting for review/test of this patch. arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi | 54 +++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi b/arch/arm64/boot/= dts/ti/k3-am642-sr-som.dtsi index 81adae0a8e55..8cb61f831734 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi @@ -162,6 +162,24 @@ main_r5fss1_core1_memory_region: r5f-memory@a3100000 { reg =3D <0x00 0xa3100000 0x00 0xf00000>; no-map; }; + + mcu_m4fss_dma_memory_region: m4f-dma-memory@a4000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa4000000 0x00 0x100000>; + no-map; + }; + + mcu_m4fss_memory_region: m4f-memory@a4100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa4100000 0x00 0xf00000>; + no-map; + }; + + rtos_ipc_memory_region: ipc-memories@a5000000 { + reg =3D <0x00 0xa5000000 0x00 0x00800000>; + alignment =3D <0x1000>; + no-map; + }; }; =20 vdd_mmc0: regulator-vdd-mmc0 { @@ -291,6 +309,35 @@ mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { }; }; =20 +&mailbox0_cluster6 { + status =3D "okay"; + + mbox_m4_0: mbox-m4-0 { + ti,mbox-rx =3D <0 0 2>; + ti,mbox-tx =3D <1 0 2>; + }; +}; + +/* main_timer8 is used by r5f0-0 */ +&main_timer8 { + status =3D "reserved"; +}; + +/* main_timer9 is used by r5f0-1 */ +&main_timer9 { + status =3D "reserved"; +}; + +/* main_timer10 is used by r5f1-0 */ +&main_timer10 { + status =3D "reserved"; +}; + +/* main_timer11 is used by r5f1-1 */ +&main_timer11 { + status =3D "reserved"; +}; + &main_i2c0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&main_i2c0_default_pins>; @@ -524,6 +571,13 @@ &main_r5fss1_core1 { status =3D "okay"; }; =20 +&mcu_m4fss { + mboxes =3D <&mailbox0_cluster6 &mbox_m4_0>; + memory-region =3D <&mcu_m4fss_dma_memory_region>, + <&mcu_m4fss_memory_region>; + status =3D "okay"; +}; + /* SoC default UART console */ &main_uart0 { pinctrl-names =3D "default"; --=20 2.34.1