From nobody Sat Oct 4 17:33:47 2025 Received: from fllvem-ot03.ext.ti.com (fllvem-ot03.ext.ti.com [198.47.19.245]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 55A08283FD8; Thu, 14 Aug 2025 22:41:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.245 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755211267; cv=none; b=MQdB96rfycNsItKR4mRmgX+lL/F8L9l7VWVSlueQELD7DQOJgAhuRLe0p+FuVNYeeahG1ulsqhKMSHAlM27fcb9p0AWNwegG0JuGApBGyCEqvqxsWzRZ8tqxllthaySAb+tjURe1YR/OMcN55WdWukzsu0btwFBDrimQTnnkBY8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755211267; c=relaxed/simple; bh=JtDs6xCWP769a3UXXfJ+DvFaKGihvknGGVlWhJ/zwXE=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=cYnHGSMpA7ENcFJC9iefX6DBGRed45Wrjzr5Po1Rul8qdebaZVIquslphYQNCwDx2yzb9W27Y8WZGszS1dTSfc/HxUqVfnLxr4bcK71XhKn/39mQU6uPSTRj7V8MZm/zc2OZ45ATENOIEM0eJWghomg1+Ztdv8gL+IqFNxA0QEs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=WLE/vXle; arc=none smtp.client-ip=198.47.19.245 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="WLE/vXle" Received: from lelvem-sh01.itg.ti.com ([10.180.77.71]) by fllvem-ot03.ext.ti.com (8.15.2/8.15.2) with ESMTP id 57EMexIa1973656; Thu, 14 Aug 2025 17:40:59 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1755211259; bh=kbAW5ng+SYlR1q+G1mS7UKdIHCAtbTtw6qU91pbk3nU=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=WLE/vXleuZ27Gpv7EE6L7WgcWU8BQufhS9wQ30GdxjGNVtTbzUuOqGWK5W8cxa8u2 0UCQb0VlE7nxNbXFFxTkJXInD+6U/R3ZxLcMsaHhx/yYOORc+myPgBbPAxyR3iSFi2 4JnVf6UvzrKseoMe19PXLws3Thll1IN4TVM+5Xsw= Received: from DLEE104.ent.ti.com (dlee104.ent.ti.com [157.170.170.34]) by lelvem-sh01.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 57EMexHt1159325 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Thu, 14 Aug 2025 17:40:59 -0500 Received: from DLEE102.ent.ti.com (157.170.170.32) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Thu, 14 Aug 2025 17:40:58 -0500 Received: from lelvem-mr06.itg.ti.com (10.180.75.8) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Thu, 14 Aug 2025 17:40:58 -0500 Received: from uda0510294.dhcp.ti.com (uda0510294.dhcp.ti.com [172.24.234.212]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 57EMcw51096792; Thu, 14 Aug 2025 17:40:55 -0500 From: Beleswar Padhi To: , , , , , CC: , , , , , , , Subject: [PATCH 26/33] arm64: dts: ti: k3-am64: Enable remote processors at board level Date: Fri, 15 Aug 2025 04:08:32 +0530 Message-ID: <20250814223839.3256046-27-b-padhi@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250814223839.3256046-1-b-padhi@ti.com> References: <20250814223839.3256046-1-b-padhi@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Remote Processors defined in top-level AM64x SoC dtsi files are incomplete without the memory carveouts and mailbox assignments which are only known at board integration level. Therefore, disable the remote processors at SoC level and enable them at board level where above information is available. Signed-off-by: Beleswar Padhi --- arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 6 ++++++ arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi | 12 ++++++++++++ arch/arm64/boot/dts/ti/k3-am642-evm.dts | 12 ++++++++++++ arch/arm64/boot/dts/ti/k3-am642-sk.dts | 12 ++++++++++++ arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi | 12 ++++++++++++ arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi | 12 ++++++++++++ 6 files changed, 66 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts= /ti/k3-am64-main.dtsi index c7e5da37486a..d872cc671094 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi @@ -921,6 +921,7 @@ main_r5fss0: r5fss@78000000 { <0x78200000 0x00 0x78200000 0x08000>, <0x78300000 0x00 0x78300000 0x08000>; power-domains =3D <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>; + status =3D "disabled"; =20 main_r5fss0_core0: r5f@78000000 { compatible =3D "ti,am64-r5f"; @@ -935,6 +936,7 @@ main_r5fss0_core0: r5f@78000000 { ti,atcm-enable =3D <1>; ti,btcm-enable =3D <1>; ti,loczrama =3D <1>; + status =3D "disabled"; }; =20 main_r5fss0_core1: r5f@78200000 { @@ -950,6 +952,7 @@ main_r5fss0_core1: r5f@78200000 { ti,atcm-enable =3D <1>; ti,btcm-enable =3D <1>; ti,loczrama =3D <1>; + status =3D "disabled"; }; }; =20 @@ -963,6 +966,7 @@ main_r5fss1: r5fss@78400000 { <0x78600000 0x00 0x78600000 0x08000>, <0x78700000 0x00 0x78700000 0x08000>; power-domains =3D <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; + status =3D "disabled"; =20 main_r5fss1_core0: r5f@78400000 { compatible =3D "ti,am64-r5f"; @@ -977,6 +981,7 @@ main_r5fss1_core0: r5f@78400000 { ti,atcm-enable =3D <1>; ti,btcm-enable =3D <1>; ti,loczrama =3D <1>; + status =3D "disabled"; }; =20 main_r5fss1_core1: r5f@78600000 { @@ -992,6 +997,7 @@ main_r5fss1_core1: r5f@78600000 { ti,atcm-enable =3D <1>; ti,btcm-enable =3D <1>; ti,loczrama =3D <1>; + status =3D "disabled"; }; }; =20 diff --git a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi b/arch/arm64/b= oot/dts/ti/k3-am64-phycore-som.dtsi index d9d491b12c33..03c46d74ebb5 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi @@ -349,28 +349,40 @@ &main_pktdma { bootph-all; }; =20 +&main_r5fss0 { + status =3D "okay"; +}; + &main_r5fss0_core0 { mboxes =3D <&mailbox0_cluster2 &mbox_main_r5fss0_core0>; memory-region =3D <&main_r5fss0_core0_dma_memory_region>, <&main_r5fss0_core0_memory_region>; + status =3D "okay"; }; =20 &main_r5fss0_core1 { mboxes =3D <&mailbox0_cluster2 &mbox_main_r5fss0_core1>; memory-region =3D <&main_r5fss0_core1_dma_memory_region>, <&main_r5fss0_core1_memory_region>; + status =3D "okay"; +}; + +&main_r5fss1 { + status =3D "okay"; }; =20 &main_r5fss1_core0 { mboxes =3D <&mailbox0_cluster4 &mbox_main_r5fss1_core0>; memory-region =3D <&main_r5fss1_core0_dma_memory_region>, <&main_r5fss1_core0_memory_region>; + status =3D "okay"; }; =20 &main_r5fss1_core1 { mboxes =3D <&mailbox0_cluster4 &mbox_main_r5fss1_core1>; memory-region =3D <&main_r5fss1_core1_dma_memory_region>, <&main_r5fss1_core1_memory_region>; + status =3D "okay"; }; =20 &mcu_m4fss { diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/= ti/k3-am642-evm.dts index b9f472ed1d8e..7640c5efe9b8 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts @@ -764,28 +764,40 @@ mbox_m4_0: mbox-m4-0 { }; }; =20 +&main_r5fss0 { + status =3D "okay"; +}; + &main_r5fss0_core0 { mboxes =3D <&mailbox0_cluster2 &mbox_main_r5fss0_core0>; memory-region =3D <&main_r5fss0_core0_dma_memory_region>, <&main_r5fss0_core0_memory_region>; + status =3D "okay"; }; =20 &main_r5fss0_core1 { mboxes =3D <&mailbox0_cluster2 &mbox_main_r5fss0_core1>; memory-region =3D <&main_r5fss0_core1_dma_memory_region>, <&main_r5fss0_core1_memory_region>; + status =3D "okay"; +}; + +&main_r5fss1 { + status =3D "okay"; }; =20 &main_r5fss1_core0 { mboxes =3D <&mailbox0_cluster4 &mbox_main_r5fss1_core0>; memory-region =3D <&main_r5fss1_core0_dma_memory_region>, <&main_r5fss1_core0_memory_region>; + status =3D "okay"; }; =20 &main_r5fss1_core1 { mboxes =3D <&mailbox0_cluster4 &mbox_main_r5fss1_core1>; memory-region =3D <&main_r5fss1_core1_dma_memory_region>, <&main_r5fss1_core1_memory_region>; + status =3D "okay"; }; =20 &mcu_m4fss { diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/t= i/k3-am642-sk.dts index 37a5ab0b6b68..fb8bd66f2f94 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts @@ -679,28 +679,40 @@ mbox_m4_0: mbox-m4-0 { }; }; =20 +&main_r5fss0 { + status =3D "okay"; +}; + &main_r5fss0_core0 { mboxes =3D <&mailbox0_cluster2 &mbox_main_r5fss0_core0>; memory-region =3D <&main_r5fss0_core0_dma_memory_region>, <&main_r5fss0_core0_memory_region>; + status =3D "okay"; }; =20 &main_r5fss0_core1 { mboxes =3D <&mailbox0_cluster2 &mbox_main_r5fss0_core1>; memory-region =3D <&main_r5fss0_core1_dma_memory_region>, <&main_r5fss0_core1_memory_region>; + status =3D "okay"; +}; + +&main_r5fss1 { + status =3D "okay"; }; =20 &main_r5fss1_core0 { mboxes =3D <&mailbox0_cluster4 &mbox_main_r5fss1_core0>; memory-region =3D <&main_r5fss1_core0_dma_memory_region>, <&main_r5fss1_core0_memory_region>; + status =3D "okay"; }; =20 &main_r5fss1_core1 { mboxes =3D <&mailbox0_cluster4 &mbox_main_r5fss1_core1>; memory-region =3D <&main_r5fss1_core1_dma_memory_region>, <&main_r5fss1_core1_memory_region>; + status =3D "okay"; }; =20 &mcu_m4fss { diff --git a/arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi b/arch/arm64/boot/= dts/ti/k3-am642-sr-som.dtsi index ad41479eba73..81adae0a8e55 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi @@ -488,28 +488,40 @@ AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* USB0_DRVVBUS.US= B0_DRVVBUS */ }; }; =20 +&main_r5fss0 { + status =3D "okay"; +}; + &main_r5fss0_core0 { mboxes =3D <&mailbox0_cluster2 &mbox_main_r5fss0_core0>; memory-region =3D <&main_r5fss0_core0_dma_memory_region>, <&main_r5fss0_core0_memory_region>; + status =3D "okay"; }; =20 &main_r5fss0_core1 { mboxes =3D <&mailbox0_cluster2 &mbox_main_r5fss0_core1>; memory-region =3D <&main_r5fss0_core1_dma_memory_region>, <&main_r5fss0_core1_memory_region>; + status =3D "okay"; +}; + +&main_r5fss1 { + status =3D "okay"; }; =20 &main_r5fss1_core0 { mboxes =3D <&mailbox0_cluster4 &mbox_main_r5fss1_core0>; memory-region =3D <&main_r5fss1_core0_dma_memory_region>, <&main_r5fss1_core0_memory_region>; + status =3D "okay"; }; =20 &main_r5fss1_core1 { mboxes =3D <&mailbox0_cluster4 &mbox_main_r5fss1_core1>; memory-region =3D <&main_r5fss1_core1_dma_memory_region>, <&main_r5fss1_core1_memory_region>; + status =3D "okay"; }; =20 /* SoC default UART console */ diff --git a/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi b/arch/arm64/bo= ot/dts/ti/k3-am642-tqma64xxl.dtsi index df05a124804c..40b619c9a6c9 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi @@ -167,28 +167,40 @@ mbox_m4_0: mbox-m4-0 { }; }; =20 +&main_r5fss0 { + status =3D "okay"; +}; + &main_r5fss0_core0 { mboxes =3D <&mailbox0_cluster2 &mbox_main_r5fss0_core0>; memory-region =3D <&main_r5fss0_core0_dma_memory_region>, <&main_r5fss0_core0_memory_region>; + status =3D "okay"; }; =20 &main_r5fss0_core1 { mboxes =3D <&mailbox0_cluster2 &mbox_main_r5fss0_core1>; memory-region =3D <&main_r5fss0_core1_dma_memory_region>, <&main_r5fss0_core1_memory_region>; + status =3D "okay"; +}; + +&main_r5fss1 { + status =3D "okay"; }; =20 &main_r5fss1_core0 { mboxes =3D <&mailbox0_cluster4 &mbox_main_r5fss1_core0>; memory-region =3D <&main_r5fss1_core0_dma_memory_region>, <&main_r5fss1_core0_memory_region>; + status =3D "okay"; }; =20 &main_r5fss1_core1 { mboxes =3D <&mailbox0_cluster4 &mbox_main_r5fss1_core1>; memory-region =3D <&main_r5fss1_core1_dma_memory_region>, <&main_r5fss1_core1_memory_region>; + status =3D "okay"; }; =20 &ospi0 { --=20 2.34.1