From nobody Sat Oct 4 17:33:44 2025 Received: from fllvem-ot04.ext.ti.com (fllvem-ot04.ext.ti.com [198.47.19.246]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 431DD29344F; Thu, 14 Aug 2025 22:40:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.246 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755211256; cv=none; b=uhzrDjfpvdaazRbOp0ndl0+pNLeF5wEyIF5EQXY/G5UkVeBMhzF1h0mPu5PtW+c+4lBpGXhLuvSFf5LIw5aq13Uasp7LVhutS+FmERjMp+Zjyafkd8jEeNR98lOLCt4wMosCbaEQPUsxx9udsvc0d5Hy1EKjOmkSKlccXEBl6zo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755211256; c=relaxed/simple; bh=UXHllwbbd6BIOwvFb2ctQbB8/5a5SP2AXF6Sfzot2fM=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Va3SqlRSfHSxom1OKUCSy4jw30WT2g53R6VApI67FabnyKx+Jm3V7pGR7jf57aYKF/1L60LzpeukEPqfMwyt5izdflA5pSIUqFLLUPqG2cO+lm9/HptezRg9l1KtJU28F502E2HfENnG2H4QcxS/fdwqRGQmGRuK4p9n2MU4vgI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=TdFUoGLp; arc=none smtp.client-ip=198.47.19.246 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="TdFUoGLp" Received: from fllvem-sh03.itg.ti.com ([10.64.41.86]) by fllvem-ot04.ext.ti.com (8.15.2/8.15.2) with ESMTP id 57EMepYa2398917; Thu, 14 Aug 2025 17:40:51 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1755211251; bh=j82CinVRxafDu5LuPyRRUIOs60GOOCYs++avFWSLYlo=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=TdFUoGLpVNV9CHXyMht3OrJNmqps0+0hZWcPv4r8WtIzxk+33tnkvTGcISZFOlpl7 A1s3cZ1QSB2M6Ur5bk2wLtjkBnH5y0b4pcpQek8GfPUPJTW9pSVsOJjWbyCtxGfzez Q1I/dczRdswqUU8SOXvzvWevUVuYGXpLlAl4vCQ8= Received: from DLEE110.ent.ti.com (dlee110.ent.ti.com [157.170.170.21]) by fllvem-sh03.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 57EMepg11462182 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Thu, 14 Aug 2025 17:40:51 -0500 Received: from DLEE110.ent.ti.com (157.170.170.21) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Thu, 14 Aug 2025 17:40:50 -0500 Received: from lelvem-mr06.itg.ti.com (10.180.75.8) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Thu, 14 Aug 2025 17:40:50 -0500 Received: from uda0510294.dhcp.ti.com (uda0510294.dhcp.ti.com [172.24.234.212]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 57EMcw4x096792; Thu, 14 Aug 2025 17:40:46 -0500 From: Beleswar Padhi To: , , , , , CC: , , , , , , , Subject: [PATCH 24/33] arm64: dts: ti: k3-am62a: Enable remote processors at board level Date: Fri, 15 Aug 2025 04:08:30 +0530 Message-ID: <20250814223839.3256046-25-b-padhi@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250814223839.3256046-1-b-padhi@ti.com> References: <20250814223839.3256046-1-b-padhi@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Remote Processors defined in top-level AM62A SoC dtsi files are incomplete without the memory carveouts and mailbox assignments which are only known at board integration level. Therefore, disable the remote processors at SoC level and enable them at board level where above information is available. Signed-off-by: Beleswar Padhi --- arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi | 1 + arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi | 2 ++ arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi | 1 + arch/arm64/boot/dts/ti/k3-am62a7-sk.dts | 2 ++ arch/arm64/boot/dts/ti/k3-am62d2-evm.dts | 1 + 5 files changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi b/arch/arm64/boot/dts= /ti/k3-am62a-mcu.dtsi index ee961ced7208..d22caa7c346b 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi @@ -197,6 +197,7 @@ mcu_r5fss0_core0: r5f@79000000 { ti,sci =3D <&dmsc>; ti,sci-dev-id =3D <9>; ti,sci-proc-ids =3D <0x03 0xff>; + status =3D "disabled"; }; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi b/arch/arm64/= boot/dts/ti/k3-am62a-phycore-som.dtsi index 57a499759910..3108e9b0c804 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi @@ -406,6 +406,7 @@ &mcu_r5fss0_core0 { mboxes =3D <&mailbox0_cluster2 &mbox_mcu_r5_0>; memory-region =3D <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; + status =3D "okay"; }; =20 &ospi0 { @@ -444,4 +445,5 @@ &wkup_r5fss0_core0 { mboxes =3D <&mailbox0_cluster0 &mbox_r5_0>; memory-region =3D <&wkup_r5fss0_core0_dma_memory_region>, <&wkup_r5fss0_core0_memory_region>; + status =3D "okay"; }; diff --git a/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi b/arch/arm64/boot/= dts/ti/k3-am62a-wakeup.dtsi index 9ef1c829a9df..23877dadc98d 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi @@ -127,6 +127,7 @@ wkup_r5fss0_core0: r5f@78000000 { ti,sci =3D <&dmsc>; ti,sci-dev-id =3D <121>; ti,sci-proc-ids =3D <0x01 0xff>; + status =3D "disabled"; }; }; =20 diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts b/arch/arm64/boot/dts/= ti/k3-am62a7-sk.dts index 3f4c6fe2999b..7ebcfe8edfe1 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts @@ -870,6 +870,7 @@ &wkup_r5fss0_core0 { mboxes =3D <&mailbox0_cluster0>, <&mbox_r5_0>; memory-region =3D <&wkup_r5fss0_core0_dma_memory_region>, <&wkup_r5fss0_core0_memory_region>; + status =3D "okay"; }; =20 &mcu_r5fss0 { @@ -880,6 +881,7 @@ &mcu_r5fss0_core0 { mboxes =3D <&mailbox0_cluster2>, <&mbox_mcu_r5_0>; memory-region =3D <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; + status =3D "okay"; }; =20 &c7x_0 { diff --git a/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts b/arch/arm64/boot/dts= /ti/k3-am62d2-evm.dts index dbee37f38b7b..41860ac42f3c 100644 --- a/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts @@ -586,6 +586,7 @@ &wkup_r5fss0_core0 { mboxes =3D <&mailbox0_cluster0 &mbox_r5_0>; memory-region =3D <&wkup_r5fss0_core0_dma_memory_region>, <&wkup_r5fss0_core0_memory_region>; + status =3D "okay"; bootph-pre-ram; }; =20 --=20 2.34.1